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8b0bfc68 WD |
1 | /* |
2 | * Copyright (C) 2004 Arabella Software Ltd. | |
3 | * Yuli Barcohen <yuli@arabellasw.com> | |
4 | * | |
5 | * U-Boot configuration for Analogue&Micro Rattler boards. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | #ifdef CONFIG_MPC8248 | |
30 | #define CPU_ID_STR "MPC8248" | |
31 | #else | |
32 | #define CONFIG_MPC8260 | |
33 | #define CPU_ID_STR "MPC8250" | |
34 | #endif /* CONFIG_MPC8248 */ | |
35 | ||
2ae18241 WD |
36 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
37 | ||
9c4c5ae3 JL |
38 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
39 | ||
8b0bfc68 WD |
40 | #define CONFIG_RATTLER /* Analogue&Micro Rattler board */ |
41 | ||
8b0bfc68 WD |
42 | /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ |
43 | #define CONFIG_ENV_OVERWRITE | |
44 | ||
45 | /* | |
46 | * Select serial console configuration | |
47 | * | |
48 | * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
49 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
50 | * for SCC). | |
51 | */ | |
52 | #define CONFIG_CONS_ON_SMC /* Console is on SMC */ | |
53 | #undef CONFIG_CONS_ON_SCC /* It's not on SCC */ | |
54 | #undef CONFIG_CONS_NONE /* It's not on external UART */ | |
55 | #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ | |
56 | ||
57 | /* | |
58 | * Select ethernet configuration | |
59 | * | |
60 | * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, | |
61 | * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for | |
62 | * SCC, 1-3 for FCC) | |
63 | * | |
64 | * If CONFIG_ETHER_NONE is defined, then either the ethernet routines | |
639221c7 JL |
65 | * must be defined elsewhere (as for the console), or CONFIG_CMD_NET |
66 | * must be unset. | |
8b0bfc68 WD |
67 | */ |
68 | #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ | |
69 | #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ | |
70 | #undef CONFIG_ETHER_NONE /* No external Ethernet */ | |
71 | ||
72 | #ifdef CONFIG_ETHER_ON_FCC | |
73 | ||
74 | #define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ | |
75 | ||
76 | #if (CONFIG_ETHER_INDEX == 1) | |
77 | ||
78 | /* - Rx clock is CLK11 | |
79 | * - Tx clock is CLK10 | |
80 | * - BDs/buffers on 60x bus | |
81 | * - Full duplex | |
82 | */ | |
d4590da4 MF |
83 | #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) |
84 | #define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) | |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
86 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
8b0bfc68 WD |
87 | |
88 | #elif (CONFIG_ETHER_INDEX == 2) | |
89 | ||
90 | /* - Rx clock is CLK15 | |
91 | * - Tx clock is CLK14 | |
92 | * - BDs/buffers on 60x bus | |
93 | * - Full duplex | |
94 | */ | |
d4590da4 MF |
95 | #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
96 | #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14) | |
6d0f6bcf JCPV |
97 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
98 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
8b0bfc68 WD |
99 | |
100 | #endif /* CONFIG_ETHER_INDEX */ | |
101 | ||
102 | #define CONFIG_MII /* MII PHY management */ | |
103 | #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ | |
104 | /* | |
105 | * GPIO pins used for bit-banged MII communications | |
106 | */ | |
107 | #define MDIO_PORT 2 /* Port C */ | |
be225442 LCM |
108 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
109 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
110 | #define MDC_DECLARE MDIO_DECLARE | |
111 | ||
8b0bfc68 WD |
112 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
113 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
114 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
115 | ||
116 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
117 | else iop->pdat &= ~0x00400000 | |
118 | ||
119 | #define MDC(bit) if(bit) iop->pdat |= 0x00800000; \ | |
120 | else iop->pdat &= ~0x00800000 | |
121 | ||
122 | #define MIIDELAY udelay(1) | |
123 | ||
124 | #endif /* CONFIG_ETHER_ON_FCC */ | |
125 | ||
126 | #ifndef CONFIG_8260_CLKIN | |
127 | #define CONFIG_8260_CLKIN 100000000 /* in Hz */ | |
128 | #endif | |
129 | ||
130 | #define CONFIG_BAUDRATE 38400 | |
131 | ||
8b0bfc68 | 132 | |
a1aa0bb5 JL |
133 | /* |
134 | * BOOTP options | |
135 | */ | |
136 | #define CONFIG_BOOTP_BOOTFILESIZE | |
137 | #define CONFIG_BOOTP_BOOTPATH | |
138 | #define CONFIG_BOOTP_GATEWAY | |
139 | #define CONFIG_BOOTP_HOSTNAME | |
140 | ||
141 | ||
e9a0f8f1 JL |
142 | /* |
143 | * Command line configuration. | |
144 | */ | |
145 | #include <config_cmd_default.h> | |
146 | ||
147 | #define CONFIG_CMD_DHCP | |
148 | #define CONFIG_CMD_IMMAP | |
149 | #define CONFIG_CMD_JFFS2 | |
150 | #define CONFIG_CMD_MII | |
151 | #define CONFIG_CMD_PING | |
152 | ||
8b0bfc68 WD |
153 | |
154 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
155 | #define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */ | |
156 | #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)" | |
157 | ||
e9a0f8f1 | 158 | #if defined(CONFIG_CMD_KGDB) |
8b0bfc68 WD |
159 | #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
160 | #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ | |
161 | #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ | |
162 | #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ | |
163 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ | |
164 | #endif | |
165 | ||
166 | #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ | |
167 | #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ | |
168 | ||
169 | /* | |
170 | * Miscellaneous configurable options | |
171 | */ | |
6d0f6bcf | 172 | #define CONFIG_SYS_HUSH_PARSER |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
174 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
e9a0f8f1 | 175 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 176 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8b0bfc68 | 177 | #else |
6d0f6bcf | 178 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8b0bfc68 | 179 | #endif |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
181 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
182 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8b0bfc68 | 183 | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
185 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
8b0bfc68 | 186 | |
6d0f6bcf | 187 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
8b0bfc68 | 188 | |
6d0f6bcf | 189 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
8b0bfc68 | 190 | |
6d0f6bcf | 191 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
8b0bfc68 | 192 | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
194 | #define CONFIG_SYS_FLASH_CFI | |
00b1883a | 195 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
197 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ | |
8b0bfc68 | 198 | |
6d0f6bcf | 199 | #define CONFIG_SYS_DIRECT_FLASH_TFTP |
8b0bfc68 | 200 | |
e9a0f8f1 | 201 | #if defined(CONFIG_CMD_JFFS2) |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS |
203 | #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS | |
700a0c64 WD |
204 | |
205 | /* | |
206 | * JFFS2 partitions | |
207 | * | |
208 | */ | |
209 | /* No command line, one static partition */ | |
68d7d651 | 210 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
211 | #define CONFIG_JFFS2_DEV "nor0" |
212 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
213 | #define CONFIG_JFFS2_PART_OFFSET 0x00100000 | |
214 | ||
215 | /* mtdparts command line support */ | |
216 | /* Note: fake mtd_id used, no linux mtd map file */ | |
217 | /* | |
68d7d651 | 218 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
219 | #define MTDIDS_DEFAULT "nor0=rattler-0" |
220 | #define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)" | |
221 | */ | |
a1aa0bb5 | 222 | #endif /* CONFIG_CMD_JFFS2 */ |
8b0bfc68 | 223 | |
14d0a02a | 224 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
225 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
226 | #define CONFIG_SYS_RAMBOOT | |
8b0bfc68 WD |
227 | #endif |
228 | ||
6d0f6bcf | 229 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
8b0bfc68 | 230 | |
5a1aceb0 | 231 | #define CONFIG_ENV_IS_IN_FLASH |
8b0bfc68 | 232 | |
5a1aceb0 | 233 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 234 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
6d0f6bcf | 235 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
5a1aceb0 | 236 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
8b0bfc68 | 237 | |
6d0f6bcf | 238 | #define CONFIG_SYS_DEFAULT_IMMR 0xFF010000 |
8b0bfc68 | 239 | |
6d0f6bcf | 240 | #define CONFIG_SYS_IMMR 0xF0000000 |
8b0bfc68 | 241 | |
6d0f6bcf | 242 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 243 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ |
25ddd1fb | 244 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 245 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
8b0bfc68 | 246 | |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
248 | #define CONFIG_SYS_SDRAM_SIZE 32 | |
249 | #define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041) | |
250 | #define CONFIG_SYS_SDRAM_OR 0xFE002EC0 | |
8b0bfc68 | 251 | |
6d0f6bcf | 252 | #define CONFIG_SYS_BCSR 0xFC000000 |
8b0bfc68 WD |
253 | |
254 | /* Hard reset configuration word */ | |
6d0f6bcf | 255 | #define CONFIG_SYS_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */ |
8b0bfc68 | 256 | /* No slaves */ |
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
258 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
259 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
260 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
261 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
262 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
263 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
8b0bfc68 | 264 | |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ |
266 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
8b0bfc68 | 267 | |
6d0f6bcf | 268 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ |
e9a0f8f1 | 269 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 270 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
8b0bfc68 WD |
271 | #endif |
272 | ||
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_HID0_INIT 0 |
274 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) | |
8b0bfc68 | 275 | |
6d0f6bcf | 276 | #define CONFIG_SYS_HID2 0 |
8b0bfc68 | 277 | |
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_SIUMCR 0x0E04C000 |
279 | #define CONFIG_SYS_SYPCR 0xFFFFFFC3 | |
280 | #define CONFIG_SYS_BCR 0x00000000 | |
281 | #define CONFIG_SYS_SCCR SCCR_DFBRG01 | |
8b0bfc68 | 282 | |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_RMR RMR_CSRE |
284 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
285 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
286 | #define CONFIG_SYS_RCCR 0 | |
8b0bfc68 | 287 | |
6d0f6bcf JCPV |
288 | #define CONFIG_SYS_PSDMR 0x8249A452 |
289 | #define CONFIG_SYS_PSRT 0x1F | |
290 | #define CONFIG_SYS_MPTPR 0x2000 | |
8b0bfc68 | 291 | |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001001) |
293 | #define CONFIG_SYS_OR0_PRELIM 0xFF001ED6 | |
294 | #define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801) | |
295 | #define CONFIG_SYS_OR7_PRELIM 0xFFFF87F6 | |
8b0bfc68 | 296 | |
6d0f6bcf | 297 | #define CONFIG_SYS_RESET_ADDRESS 0xC0000000 |
8b0bfc68 WD |
298 | |
299 | #endif /* __CONFIG_H */ |