[people/ms/u-boot.git] / include / configs / Rattler.h

/*
 * Copyright (C) 2004 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 *
 * U-Boot configuration for Analogue&Micro Rattler boards.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifdef CONFIG_MPC8248
#define CPU_ID_STR		"MPC8248"
#else
#define CONFIG_MPC8260
#define CPU_ID_STR		"MPC8250"
#endif /* CONFIG_MPC8248 */

#define CONFIG_CPM2		1	/* Has a CPM2 */

#define CONFIG_RATTLER			/* Analogue&Micro Rattler board */

/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE

/*
 * Select serial console configuration
 *
 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 */
#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
#undef	CONFIG_CONS_NONE		/* It's not on external UART */
#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */

/*
 * Select ethernet configuration
 *
 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 * SCC, 1-3 for FCC)
 *
 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 * must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */

#ifdef CONFIG_ETHER_ON_FCC

#define CONFIG_ETHER_INDEX	1	/* FCC1 is used for Ethernet */

#if   (CONFIG_ETHER_INDEX == 1)

/* - Rx clock is CLK11
 * - Tx clock is CLK10
 * - BDs/buffers on 60x bus
 * - Full duplex
 */
#define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
#define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
#define CFG_CPMFCR_RAMTYPE	0
#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#elif (CONFIG_ETHER_INDEX == 2)

/* - Rx clock is CLK15
 * - Tx clock is CLK14
 * - BDs/buffers on 60x bus
 * - Full duplex
 */
#define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
#define CFG_CPMFCR_RAMTYPE	0
#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#endif /* CONFIG_ETHER_INDEX */

#define CONFIG_MII			/* MII PHY management        */
#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT		2	/* Port C */
#define MDIO_ACTIVE		(iop->pdir |=  0x00400000)
#define MDIO_TRISTATE		(iop->pdir &= ~0x00400000)
#define MDIO_READ		((iop->pdat &  0x00400000) != 0)

#define MDIO(bit)		if(bit) iop->pdat |=  0x00400000; \
				else	iop->pdat &= ~0x00400000

#define MDC(bit)		if(bit) iop->pdat |=  0x00800000; \
				else	iop->pdat &= ~0x00800000

#define MIIDELAY		udelay(1)

#endif /* CONFIG_ETHER_ON_FCC */

#ifndef CONFIG_8260_CLKIN
#define CONFIG_8260_CLKIN	100000000	/* in Hz */
#endif

#define CONFIG_BAUDRATE		38400


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING


#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND	"bootm FE040000"	/* autoboot command */
#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"

#if defined(CONFIG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
#endif

#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
#define CFG_MAXARGS		16		/* max number of command args */
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CFG_FLASH_BASE		0xFE000000
#define CFG_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#define	CFG_DIRECT_FLASH_TFTP

#if defined(CONFIG_CMD_JFFS2)
#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
#define CFG_JFFS2_SORT_FRAGMENTS

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00100000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=rattler-0"
#define MTDPARTS_DEFAULT	"mtdparts=rattler-0:-@1m(jffs2)"
*/
#endif /* CONFIG_CMD_JFFS2 */

#define CFG_MONITOR_BASE	TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/

#define CONFIG_ENV_IS_IN_FLASH

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#endif /* CONFIG_ENV_IS_IN_FLASH */

#define CFG_DEFAULT_IMMR	0xFF010000

#define CFG_IMMR		0xF0000000

#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_SDRAM_BASE		0x00000000
#define CFG_SDRAM_SIZE		32
#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00000041)
#define CFG_SDRAM_OR		0xFE002EC0

#define CFG_BCSR		0xFC000000

/* Hard reset configuration word */
#define CFG_HRCW_MASTER		0x0A06875A /* Not used - provided by FPGA */
/* No slaves */
#define CFG_HRCW_SLAVE1		0
#define CFG_HRCW_SLAVE2		0
#define CFG_HRCW_SLAVE3		0
#define CFG_HRCW_SLAVE4		0
#define CFG_HRCW_SLAVE5		0
#define CFG_HRCW_SLAVE6		0
#define CFG_HRCW_SLAVE7		0

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot                  */

#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)

#define CFG_HID2		0

#define CFG_SIUMCR		0x0E04C000
#define CFG_SYPCR		0xFFFFFFC3
#define CFG_BCR			0x00000000
#define CFG_SCCR		SCCR_DFBRG01

#define CFG_RMR			RMR_CSRE
#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_RCCR		0

#define CFG_PSDMR		0x8249A452
#define CFG_PSRT		0x1F
#define CFG_MPTPR		0x2000

#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001001)
#define CFG_OR0_PRELIM		0xFF001ED6
#define CFG_BR7_PRELIM		(CFG_BCSR | 0x00000801)
#define CFG_OR7_PRELIM		0xFFFF87F6

#define CFG_RESET_ADDRESS	0xC0000000

#endif /* __CONFIG_H */
Commit	Line	Data
8b0bfc68 WD	1	/*
	2	* Copyright (C) 2004 Arabella Software Ltd.
	3	* Yuli Barcohen <yuli@arabellasw.com>
	4	*
	5	* U-Boot configuration for Analogue&Micro Rattler boards.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	#ifdef CONFIG_MPC8248
	30	#define CPU_ID_STR "MPC8248"
	31	#else
	32	#define CONFIG_MPC8260
	33	#define CPU_ID_STR "MPC8250"
	34	#endif /* CONFIG_MPC8248 */
	35
9c4c5ae3 JL	36	#define CONFIG_CPM2 1 /* Has a CPM2 */
9c4c5ae3 JL	37
8b0bfc68 WD	38	#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
8b0bfc68 WD	39
8b0bfc68 WD	40	/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
	41	#define CONFIG_ENV_OVERWRITE
	42
	43	/*
	44	* Select serial console configuration
	45	*
	46	* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	47	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	48	* for SCC).
	49	*/
	50	#define CONFIG_CONS_ON_SMC /* Console is on SMC */
	51	#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
	52	#undef CONFIG_CONS_NONE /* It's not on external UART */
	53	#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
	54
	55	/*
	56	* Select ethernet configuration
	57	*
	58	* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
	59	* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
	60	* SCC, 1-3 for FCC)
	61	*
	62	* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
639221c7 JL	63	* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
639221c7 JL	64	* must be unset.
8b0bfc68 WD	65	*/
	66	#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
	67	#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
	68	#undef CONFIG_ETHER_NONE /* No external Ethernet */
	69
	70	#ifdef CONFIG_ETHER_ON_FCC
	71
	72	#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
	73
	74	#if (CONFIG_ETHER_INDEX == 1)
	75
	76	/* - Rx clock is CLK11
	77	* - Tx clock is CLK10
	78	* - BDs/buffers on 60x bus
	79	* - Full duplex
	80	*/
	81	#define CFG_CMXFCR_MASK (CMXFCR_FC1 \| CMXFCR_RF1CS_MSK \| CMXFCR_TF1CS_MSK)
	82	#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 \| CMXFCR_TF1CS_CLK10)
	83	#define CFG_CPMFCR_RAMTYPE 0
	84	#define CFG_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
	85
	86	#elif (CONFIG_ETHER_INDEX == 2)
	87
	88	/* - Rx clock is CLK15
	89	* - Tx clock is CLK14
	90	* - BDs/buffers on 60x bus
	91	* - Full duplex
	92	*/
	93	#define CFG_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	94	#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 \| CMXFCR_TF2CS_CLK14)
	95	#define CFG_CPMFCR_RAMTYPE 0
	96	#define CFG_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
	97
	98	#endif /* CONFIG_ETHER_INDEX */
	99
	100	#define CONFIG_MII /* MII PHY management */
	101	#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
	102	/*
	103	* GPIO pins used for bit-banged MII communications
	104	*/
	105	#define MDIO_PORT 2 /* Port C */
	106	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	107	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	108	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
	109
	110	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
	111	else iop->pdat &= ~0x00400000
	112
	113	#define MDC(bit) if(bit) iop->pdat \|= 0x00800000; \
	114	else iop->pdat &= ~0x00800000
	115
	116	#define MIIDELAY udelay(1)
	117
	118	#endif /* CONFIG_ETHER_ON_FCC */
	119
	120	#ifndef CONFIG_8260_CLKIN
	121	#define CONFIG_8260_CLKIN 100000000 /* in Hz */
	122	#endif
	123
	124	#define CONFIG_BAUDRATE 38400
	125
8b0bfc68	126
a1aa0bb5 JL	127	/*
	128	* BOOTP options
	129	*/
	130	#define CONFIG_BOOTP_BOOTFILESIZE
	131	#define CONFIG_BOOTP_BOOTPATH
	132	#define CONFIG_BOOTP_GATEWAY
	133	#define CONFIG_BOOTP_HOSTNAME
	134
	135
e9a0f8f1 JL	136	/*
	137	* Command line configuration.
	138	*/
	139	#include <config_cmd_default.h>
	140
	141	#define CONFIG_CMD_DHCP
	142	#define CONFIG_CMD_IMMAP
	143	#define CONFIG_CMD_JFFS2
	144	#define CONFIG_CMD_MII
	145	#define CONFIG_CMD_PING
	146
8b0bfc68 WD	147
	148	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	149	#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
	150	#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
	151
e9a0f8f1	152	#if defined(CONFIG_CMD_KGDB)
8b0bfc68 WD	153	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	154	#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	155	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	156	#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
	157	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
	158	#endif
	159
	160	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
	161	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
	162
	163	/*
	164	* Miscellaneous configurable options
	165	*/
	166	#define CFG_HUSH_PARSER
	167	#define CFG_PROMPT_HUSH_PS2 "> "
	168	#define CFG_LONGHELP /* undef to save memory */
	169	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
e9a0f8f1	170	#if defined(CONFIG_CMD_KGDB)
8b0bfc68 WD	171	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	172	#else
	173	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	174	#endif
	175	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	176	#define CFG_MAXARGS 16 /* max number of command args */
	177	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	178
	179	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	180	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	181
	182	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	183
	184	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	185
	186	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	187
	188	#define CFG_FLASH_BASE 0xFE000000
	189	#define CFG_FLASH_CFI
00b1883a	190	#define CONFIG_FLASH_CFI_DRIVER
8b0bfc68 WD	191	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
	192	#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
	193
	194	#define CFG_DIRECT_FLASH_TFTP
	195
e9a0f8f1	196	#if defined(CONFIG_CMD_JFFS2)
8b0bfc68	197	#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
8b0bfc68	198	#define CFG_JFFS2_SORT_FRAGMENTS
700a0c64 WD	199
	200	/*
	201	* JFFS2 partitions
	202	*
	203	*/
	204	/* No command line, one static partition */
	205	#undef CONFIG_JFFS2_CMDLINE
	206	#define CONFIG_JFFS2_DEV "nor0"
	207	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	208	#define CONFIG_JFFS2_PART_OFFSET 0x00100000
	209
	210	/* mtdparts command line support */
	211	/* Note: fake mtd_id used, no linux mtd map file */
	212	/*
	213	#define CONFIG_JFFS2_CMDLINE
	214	#define MTDIDS_DEFAULT "nor0=rattler-0"
	215	#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
	216	*/
a1aa0bb5	217	#endif /* CONFIG_CMD_JFFS2 */
8b0bfc68 WD	218
	219	#define CFG_MONITOR_BASE TEXT_BASE
	220	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	221	#define CFG_RAMBOOT
	222	#endif
	223
60fc6cbb	224	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
8b0bfc68	225
5a1aceb0	226	#define CONFIG_ENV_IS_IN_FLASH
8b0bfc68	227
5a1aceb0	228	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	229	#define CONFIG_ENV_SECT_SIZE 0x10000
0e8d1586 JCPV	230	#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
5a1aceb0	231	#endif /* CONFIG_ENV_IS_IN_FLASH */
8b0bfc68 WD	232
	233	#define CFG_DEFAULT_IMMR 0xFF010000
	234
	235	#define CFG_IMMR 0xF0000000
	236
	237	#define CFG_INIT_RAM_ADDR CFG_IMMR
	238	#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
	239	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	240	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	241	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	242
	243	#define CFG_SDRAM_BASE 0x00000000
	244	#define CFG_SDRAM_SIZE 32
	245	#define CFG_SDRAM_BR (CFG_SDRAM_BASE \| 0x00000041)
	246	#define CFG_SDRAM_OR 0xFE002EC0
	247
	248	#define CFG_BCSR 0xFC000000
	249
	250	/* Hard reset configuration word */
	251	#define CFG_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
	252	/* No slaves */
53677ef1 WD	253	#define CFG_HRCW_SLAVE1 0
	254	#define CFG_HRCW_SLAVE2 0
	255	#define CFG_HRCW_SLAVE3 0
	256	#define CFG_HRCW_SLAVE4 0
	257	#define CFG_HRCW_SLAVE5 0
	258	#define CFG_HRCW_SLAVE6 0
	259	#define CFG_HRCW_SLAVE7 0
8b0bfc68 WD	260
	261	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	262	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	263
	264	#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
	265	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	266
	267	#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
e9a0f8f1	268	#if defined(CONFIG_CMD_KGDB)
8b0bfc68 WD	269	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	270	#endif
	271
	272	#define CFG_HID0_INIT 0
	273	#define CFG_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE)
	274
	275	#define CFG_HID2 0
	276
	277	#define CFG_SIUMCR 0x0E04C000
	278	#define CFG_SYPCR 0xFFFFFFC3
	279	#define CFG_BCR 0x00000000
	280	#define CFG_SCCR SCCR_DFBRG01
	281
	282	#define CFG_RMR RMR_CSRE
	283	#define CFG_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
	284	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
	285	#define CFG_RCCR 0
	286
	287	#define CFG_PSDMR 0x8249A452
	288	#define CFG_PSRT 0x1F
	289	#define CFG_MPTPR 0x2000
	290
	291	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| 0x00001001)
	292	#define CFG_OR0_PRELIM 0xFF001ED6
	293	#define CFG_BR7_PRELIM (CFG_BCSR \| 0x00000801)
	294	#define CFG_OR7_PRELIM 0xFFFF87F6
	295
	296	#define CFG_RESET_ADDRESS 0xC0000000
	297
	298	#endif /* __CONFIG_H */