[people/ms/u-boot.git] / include / configs / SBC8540.h

/*
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
 * Added support for Wind River SBC8540 board
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * sbc8540 board configuration file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Top level Makefile configuration choices
 */
#ifdef CONFIG_MK_66
#define CONFIG_PCI_66
#endif

#define TSEC_DEBUG

/*
 * High Level Configuration Options
 */
#define CONFIG_BOOKE		1	/* BOOKE			*/
#define CONFIG_E500		1	/* BOOKE e500 family		*/
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560		*/
#define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip		*/


#define CONFIG_CPM2		1	/* has CPM2 */

#define CONFIG_SBC8540		1	/* configuration for SBC8560 board */
#define CONFIG_MPC8540		1

#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific (supplement)	*/

#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
#undef	CONFIG_PCI			/* pci ethernet support		*/
#undef  CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support	*/

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

#define CONFIG_ENV_OVERWRITE

/* Using Localbus SDRAM to emulate flash before we can program the flash,
 * normally you need a flash-boot image(u-boot.bin), if so undef this.
 */
#undef CONFIG_RAM_AS_FLASH

#if defined(CONFIG_PCI_66)			/* some PCI card is 33Mhz only	*/
  #define CONFIG_SYS_CLK_FREQ	66000000	/* sysclk for MPC85xx		*/
#else
  #define CONFIG_SYS_CLK_FREQ	33000000	/* most pci cards are 33Mhz	*/
#endif

/* below can be toggled for performance analysis. otherwise use default */
#define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
#undef	CONFIG_BTB			    /* toggle branch predition	*/

#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
#define CONFIG_RESET_PHY_R	1	    /* Call reset_phy() */

#undef	CONFIG_SYS_DRAM_TEST			    /* memory test, takes time	*/
#define CONFIG_SYS_MEMTEST_START	0x00200000  /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
     defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
     defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
#endif

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/

#if XXX
  #define CONFIG_SYS_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
#else
  #define CONFIG_SYS_CCSRBAR		0xff700000	/* default CCSRBAR	*/
#endif
#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR	*/

#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */

/* DDR Setup */
#define CONFIG_FSL_DDR1
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
#undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
#undef  CONFIG_DDR_SPD

#if defined(CONFIG_MPC85xx_REV1)
  #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
#endif

#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x55	/* CTLR 0 DIMM 0 */

#undef CONFIG_CLOCKS_IN_MHZ

#if defined(CONFIG_RAM_AS_FLASH)
  #define CONFIG_SYS_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
  #define CONFIG_SYS_FLASH_BASE	0xf8000000      /* start of FLASH 8M  */
  #define CONFIG_SYS_BR0_PRELIM	0xf8000801      /* port size 8bit */
  #define CONFIG_SYS_OR0_PRELIM	0xf8000ff7	/* 8MB Flash		*/
#else /* Boot from real Flash */
  #define CONFIG_SYS_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
  #define CONFIG_SYS_FLASH_BASE	0xff800000      /* start of FLASH 8M    */
  #define CONFIG_SYS_BR0_PRELIM	0xff800801      /* port size 8bit      */
  #define CONFIG_SYS_OR0_PRELIM	0xff800ff7	/* 8MB Flash		*/
#endif
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/

/* local bus definitions */
#define CONFIG_SYS_BR1_PRELIM		0xe4001801	/* 64M, 32-bit flash */
#define CONFIG_SYS_OR1_PRELIM		0xfc000ff7

#define CONFIG_SYS_BR2_PRELIM		0x00000000	/* CS2 not used */
#define CONFIG_SYS_OR2_PRELIM		0x00000000

#define CONFIG_SYS_BR3_PRELIM		0xf0001861	/* 64MB localbus SDRAM	*/
#define CONFIG_SYS_OR3_PRELIM		0xfc000cc1

#if defined(CONFIG_RAM_AS_FLASH)
  #define CONFIG_SYS_BR4_PRELIM	0xf4001861	/* 64M localbus SDRAM */
#else
  #define CONFIG_SYS_BR4_PRELIM	0xf8001861	/* 64M localbus SDRAM */
#endif
#define CONFIG_SYS_OR4_PRELIM		0xfc000cc1

#define CONFIG_SYS_BR5_PRELIM		0xfc000801	/* 16M CS5 misc devices */
#if 1
  #define CONFIG_SYS_OR5_PRELIM	0xff000ff7
#else
  #define CONFIG_SYS_OR5_PRELIM	0xff0000f0
#endif

#define CONFIG_SYS_BR6_PRELIM		0xe0001801	/* 64M, 32-bit flash */
#define CONFIG_SYS_OR6_PRELIM		0xfc000ff7
#define CONFIG_SYS_LBC_LCRR		0x00030002	/* local bus freq	*/
#define CONFIG_SYS_LBC_LBCR		0x00000000
#define CONFIG_SYS_LBC_LSRT		0x20000000
#define CONFIG_SYS_LBC_MRTPR		0x20000000
#define CONFIG_SYS_LBC_LSDMR_1		0x2861b723
#define CONFIG_SYS_LBC_LSDMR_2		0x0861b723
#define CONFIG_SYS_LBC_LSDMR_3		0x0861b723
#define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
#define CONFIG_SYS_LBC_LSDMR_5		0x4061b723

/* just hijack the MOT BCSR def for SBC8560 misc devices */
#define CONFIG_SYS_BCSR		((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
/* the size of CS5 needs to be >= 16M for TLB and LAW setups */

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */

/* Serial Port */
#undef  CONFIG_CONS_ON_SCC			/* define if console on SCC */
#undef	CONFIG_CONS_NONE			/* define if console on something else */

#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#if 0
#define CONFIG_SYS_NS16550_CLK		1843200 /* get_bus_freq(0) */
#else
#define CONFIG_SYS_NS16550_CLK		264000000 /* get_bus_freq(0) */
#endif

#define CONFIG_BAUDRATE		9600

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#if 0
#define CONFIG_SYS_NS16550_COM1	((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
#define CONFIG_SYS_NS16550_COM2	((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
#else
/* SBC8540 uses internal COMM controller */
#define CONFIG_SYS_NS16550_COM1	((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500)
#define CONFIG_SYS_NS16550_COM2	((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600)
#endif

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef	CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET		0x3000

#define CONFIG_SYS_PCI_MEM_BASE	0xC0000000
#define CONFIG_SYS_PCI_MEM_PHYS	0xC0000000
#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000

#if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */

#  define CONFIG_NET_MULTI	1
#  define CONFIG_MPC85xx_TSEC1
#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
#  define CONFIG_MII		1	/* MII PHY management		*/
#  define TSEC1_PHY_ADDR	25
#  define TSEC1_PHYIDX		0
/* Options are: TSEC0 */
#  define CONFIG_ETHPRIME		"TSEC0"


#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */

  #undef  CONFIG_ETHER_NONE		/* define if ether on something else */
  #define CONFIG_ETHER_ON_FCC2		/* cpm FCC ethernet support	*/
  #define CONFIG_ETHER_INDEX	2	/* which channel for ether  */

  #if (CONFIG_ETHER_INDEX == 2)
    /*
     * - Rx-CLK is CLK13
     * - Tx-CLK is CLK14
     * - Select bus for bd/buffers
     * - Full duplex
     */
    #define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
    #define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
    #define CONFIG_SYS_CPMFCR_RAMTYPE	0
    #define CONFIG_SYS_FCC_PSMR	(FCC_PSMR_FDE)

  #elif (CONFIG_ETHER_INDEX == 3)
    /* need more definitions here for FE3 */
  #endif				/* CONFIG_ETHER_INDEX */

  #define CONFIG_MII			/* MII PHY management */
  #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
  /*
   * GPIO pins used for bit-banged MII communications
   */
  #define MDIO_PORT	2		/* Port C */
  #define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
  #define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
  #define MDIO_READ	((iop->pdat &  0x00400000) != 0)

  #define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
			else	iop->pdat &= ~0x00400000

  #define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
			else	iop->pdat &= ~0x00200000

  #define MIIDELAY	udelay(1)

#endif

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
#if 0
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
#define CONFIG_SYS_FLASH_PROTECTION		/* use hardware protection		*/
#endif
#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/

#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	200000		/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	50000		/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/

#if 0
/* XXX This doesn't work and I don't want to fix it */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  #define CONFIG_SYS_RAMBOOT
#else
  #undef  CONFIG_SYS_RAMBOOT
#endif
#endif

/* Environment */
#if !defined(CONFIG_SYS_RAMBOOT)
  #if defined(CONFIG_RAM_AS_FLASH)
    #define CONFIG_ENV_IS_NOWHERE
    #define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + 0x100000)
    #define CONFIG_ENV_SIZE	0x2000
  #else
    #define CONFIG_ENV_IS_IN_FLASH	1
    #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
    #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
    #define CONFIG_ENV_SIZE	0x2000 /* CONFIG_ENV_SECT_SIZE */
  #endif
#else
  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now	*/
  #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
  #define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
/*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
#define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
    #define CONFIG_CMD_MII
#endif

#if defined(CONFIG_SYS_RAMBOOT)
    #undef CONFIG_CMD_SAVEENV
    #undef CONFIG_CMD_LOADS
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"SBC8540=> " /* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
  #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
  #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot		*/

#if defined(CONFIG_CMD_KGDB)
  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
  #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#  define CONFIG_ETHADDR	00:vv:ww:xx:yy:8a
#  define CONFIG_HAS_ETH1
#  define CONFIG_ETH1ADDR	00:vv:ww:xx:yy:8b
#  define CONFIG_HAS_ETH2
#  define CONFIG_ETH2ADDR	00:vv:ww:xx:yy:8c
#endif

#define CONFIG_SERVERIP		YourServerIP
#define CONFIG_IPADDR		YourTargetIP
#define CONFIG_GATEWAYIP	YourGatewayIP
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_HOSTNAME		SBC8560
#define CONFIG_ROOTPATH		YourRootPath
#define CONFIG_BOOTFILE		YourImageName

#endif	/* __CONFIG_H */
Commit	Line	Data
c15f3120 WD	1	/*
	2	* (C) Copyright 2002,2003 Motorola,Inc.
	3	* Xianghua Xiao <X.Xiao@motorola.com>
	4	*
	5	* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
	6	* Added support for Wind River SBC8540 board
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
928435d1 PG	27	/*
928435d1 PG	28	* sbc8540 board configuration file.
c15f3120	29	*/
8b74bf31	30
c15f3120 WD	31	#ifndef __CONFIG_H
	32	#define __CONFIG_H
	33
928435d1 PG	34	/*
	35	* Top level Makefile configuration choices
	36	*/
	37	#ifdef CONFIG_MK_66
	38	#define CONFIG_PCI_66
c15f3120	39	#endif
928435d1	40
c15f3120 WD	41	#define TSEC_DEBUG
c15f3120 WD	42
928435d1 PG	43	/*
	44	* High Level Configuration Options
	45	*/
c15f3120 WD	46	#define CONFIG_BOOKE 1 /* BOOKE */
	47	#define CONFIG_E500 1 /* BOOKE e500 family */
	48	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
	49	#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
	50
	51
9c4c5ae3	52	#define CONFIG_CPM2 1 /* has CPM2 */
c15f3120	53
53677ef1	54	#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
f060054d	55	#define CONFIG_MPC8540 1
c15f3120 WD	56
	57	#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
	58
	59	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	60	#undef CONFIG_PCI /* pci ethernet support */
	61	#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
	62
e2b159d0	63	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
c15f3120 WD	64
	65	#define CONFIG_ENV_OVERWRITE
	66
	67	/* Using Localbus SDRAM to emulate flash before we can program the flash,
	68	* normally you need a flash-boot image(u-boot.bin), if so undef this.
	69	*/
	70	#undef CONFIG_RAM_AS_FLASH
	71
	72	#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
	73	#define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
	74	#else
	75	#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
	76	#endif
	77
	78	/* below can be toggled for performance analysis. otherwise use default */
	79	#define CONFIG_L2_CACHE /* toggle L2 cache */
	80	#undef CONFIG_BTB /* toggle branch predition */
c15f3120 WD	81
c15f3120 WD	82	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
004eca0c	83	#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
c15f3120	84
6d0f6bcf JCPV	85	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	86	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
	87	#define CONFIG_SYS_MEMTEST_END 0x00400000
c15f3120 WD	88
	89	#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) \|\| \
	90	defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) \|\| \
	91	defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
	92	#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
	93	#endif
	94
	95	/*
	96	* Base addresses -- Note these are effective addresses where the
	97	* actual resources get mapped (not physical addresses)
	98	*/
6d0f6bcf	99	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
c15f3120 WD	100
c15f3120 WD	101	#if XXX
6d0f6bcf	102	#define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
c15f3120	103	#else
6d0f6bcf	104	#define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */
c15f3120	105	#endif
6d0f6bcf JCPV	106	#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
6d0f6bcf JCPV	107	#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
c15f3120	108
6d0f6bcf	109	#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
c15f3120	110
8e55313b KG	111	/* DDR Setup */
	112	#define CONFIG_FSL_DDR1
	113	#undef CONFIG_FSL_DDR_INTERACTIVE
c15f3120 WD	114	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
c15f3120 WD	115	#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
8e55313b	116	#undef CONFIG_DDR_SPD
c15f3120 WD	117
	118	#if defined(CONFIG_MPC85xx_REV1)
	119	#define CONFIG_DDR_DLL /* possible DLL fix needed */
	120	#endif
	121
8e55313b KG	122	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	123	#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
	124	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	127	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
8e55313b KG	128	#define CONFIG_VERY_BIG_RAM
	129
	130	#define CONFIG_NUM_DDR_CONTROLLERS 1
	131	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	132	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
	133
	134	/* I2C addresses of SPD EEPROMs */
	135	#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
	136
c15f3120 WD	137	#undef CONFIG_CLOCKS_IN_MHZ
	138
	139	#if defined(CONFIG_RAM_AS_FLASH)
6d0f6bcf JCPV	140	#define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
	141	#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
	142	#define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
	143	#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
c15f3120	144	#else /* Boot from real Flash */
6d0f6bcf JCPV	145	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
	146	#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
	147	#define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
	148	#define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
c15f3120	149	#endif
6d0f6bcf	150	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
c15f3120 WD	151
c15f3120 WD	152	/* local bus definitions */
6d0f6bcf JCPV	153	#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
6d0f6bcf JCPV	154	#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
c15f3120	155
6d0f6bcf JCPV	156	#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
6d0f6bcf JCPV	157	#define CONFIG_SYS_OR2_PRELIM 0x00000000
c15f3120	158
6d0f6bcf JCPV	159	#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
6d0f6bcf JCPV	160	#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
c15f3120 WD	161
c15f3120 WD	162	#if defined(CONFIG_RAM_AS_FLASH)
6d0f6bcf	163	#define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
c15f3120	164	#else
6d0f6bcf	165	#define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
c15f3120	166	#endif
6d0f6bcf	167	#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
c15f3120	168
6d0f6bcf	169	#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
c15f3120	170	#if 1
6d0f6bcf	171	#define CONFIG_SYS_OR5_PRELIM 0xff000ff7
c15f3120	172	#else
6d0f6bcf	173	#define CONFIG_SYS_OR5_PRELIM 0xff0000f0
c15f3120 WD	174	#endif
c15f3120 WD	175
6d0f6bcf JCPV	176	#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
	177	#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
	178	#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
	179	#define CONFIG_SYS_LBC_LBCR 0x00000000
	180	#define CONFIG_SYS_LBC_LSRT 0x20000000
	181	#define CONFIG_SYS_LBC_MRTPR 0x20000000
	182	#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
	183	#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
	184	#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
	185	#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
	186	#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
c15f3120 WD	187
c15f3120 WD	188	/* just hijack the MOT BCSR def for SBC8560 misc devices */
6d0f6bcf	189	#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)\|0x00400000)
c15f3120 WD	190	/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
c15f3120 WD	191
6d0f6bcf JCPV	192	#define CONFIG_SYS_INIT_RAM_LOCK 1
	193	#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
	194	#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
c15f3120	195
6d0f6bcf JCPV	196	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
	197	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	198	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c15f3120	199
6d0f6bcf JCPV	200	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	201	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
c15f3120 WD	202
	203	/* Serial Port */
	204	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	205	#undef CONFIG_CONS_NONE /* define if console on something else */
	206
	207	#define CONFIG_CONS_INDEX 1
	208	#undef CONFIG_SERIAL_SOFTWARE_FIFO
6d0f6bcf JCPV	209	#define CONFIG_SYS_NS16550
	210	#define CONFIG_SYS_NS16550_SERIAL
	211	#define CONFIG_SYS_NS16550_REG_SIZE 1
c15f3120	212	#if 0
6d0f6bcf	213	#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
c15f3120	214	#else
6d0f6bcf	215	#define CONFIG_SYS_NS16550_CLK 264000000 /* get_bus_freq(0) */
c15f3120 WD	216	#endif
	217
	218	#define CONFIG_BAUDRATE 9600
	219
6d0f6bcf	220	#define CONFIG_SYS_BAUDRATE_TABLE \
c15f3120 WD	221	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	222
	223	#if 0
6d0f6bcf JCPV	224	#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
6d0f6bcf JCPV	225	#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
c15f3120	226	#else
8b74bf31	227	/* SBC8540 uses internal COMM controller */
6d0f6bcf JCPV	228	#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500)
6d0f6bcf JCPV	229	#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600)
c15f3120 WD	230	#endif
	231
	232	/* Use the HUSH parser */
6d0f6bcf JCPV	233	#define CONFIG_SYS_HUSH_PARSER
	234	#ifdef CONFIG_SYS_HUSH_PARSER
	235	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
c15f3120 WD	236	#endif
c15f3120 WD	237
20476726 JL	238	/*
	239	* I2C
	240	*/
	241	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	242	#define CONFIG_HARD_I2C /* I2C with hardware support*/
c15f3120	243	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	244	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	245	#define CONFIG_SYS_I2C_SLAVE 0x7F
	246	#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
	247	#define CONFIG_SYS_I2C_OFFSET 0x3000
c15f3120	248
6d0f6bcf JCPV	249	#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
	250	#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
	251	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
c15f3120 WD	252
	253	#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
	254
d9b94f28 JL	255	# define CONFIG_NET_MULTI 1
	256	# define CONFIG_MPC85xx_TSEC1
	257	# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
	258	# define CONFIG_MII 1 /* MII PHY management */
	259	# define TSEC1_PHY_ADDR 25
	260	# define TSEC1_PHYIDX 0
	261	/* Options are: TSEC0 */
	262	# define CONFIG_ETHPRIME "TSEC0"
c15f3120	263
8b74bf31	264
c15f3120 WD	265	#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
	266
	267	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	268	#define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
	269	#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
8b74bf31	270
c15f3120 WD	271	#if (CONFIG_ETHER_INDEX == 2)
	272	/*
	273	* - Rx-CLK is CLK13
	274	* - Tx-CLK is CLK14
	275	* - Select bus for bd/buffers
	276	* - Full duplex
	277	*/
6d0f6bcf JCPV	278	#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	279	#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
	280	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
	281	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
8b74bf31	282
c15f3120 WD	283	#elif (CONFIG_ETHER_INDEX == 3)
	284	/* need more definitions here for FE3 */
	285	#endif /* CONFIG_ETHER_INDEX */
8b74bf31	286
c15f3120 WD	287	#define CONFIG_MII /* MII PHY management */
	288	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
	289	/*
	290	* GPIO pins used for bit-banged MII communications
	291	*/
	292	#define MDIO_PORT 2 /* Port C */
	293	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	294	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	295	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
	296
	297	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
	298	else iop->pdat &= ~0x00400000
	299
	300	#define MDC(bit) if(bit) iop->pdat \|= 0x00200000; \
	301	else iop->pdat &= ~0x00200000
	302
	303	#define MIIDELAY udelay(1)
8b74bf31	304
c15f3120 WD	305	#endif
	306
	307	/*-----------------------------------------------------------------------
	308	* FLASH and environment organization
	309	*/
	310
6d0f6bcf	311	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	312	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
c15f3120	313	#if 0
6d0f6bcf JCPV	314	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
6d0f6bcf JCPV	315	#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
c15f3120	316	#endif
6d0f6bcf JCPV	317	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
6d0f6bcf JCPV	318	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
c15f3120	319
6d0f6bcf JCPV	320	#undef CONFIG_SYS_FLASH_CHECKSUM
	321	#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
	322	#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
c15f3120	323
6d0f6bcf	324	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
c15f3120 WD	325
	326	#if 0
	327	/* XXX This doesn't work and I don't want to fix it */
6d0f6bcf JCPV	328	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	329	#define CONFIG_SYS_RAMBOOT
c15f3120	330	#else
6d0f6bcf	331	#undef CONFIG_SYS_RAMBOOT
c15f3120 WD	332	#endif
	333	#endif
	334
	335	/* Environment */
6d0f6bcf	336	#if !defined(CONFIG_SYS_RAMBOOT)
c15f3120	337	#if defined(CONFIG_RAM_AS_FLASH)
93f6d725	338	#define CONFIG_ENV_IS_NOWHERE
6d0f6bcf	339	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
0e8d1586	340	#define CONFIG_ENV_SIZE 0x2000
c15f3120	341	#else
5a1aceb0	342	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	343	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
6d0f6bcf	344	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
0e8d1586	345	#define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
c15f3120 WD	346	#endif
c15f3120 WD	347	#else
6d0f6bcf	348	#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
93f6d725	349	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
6d0f6bcf	350	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	351	#define CONFIG_ENV_SIZE 0x2000
c15f3120 WD	352	#endif
	353
	354	#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
	355	/#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"/
	356	#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
	357	#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
	358
	359	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	360	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c15f3120	361
2835e518	362
a1aa0bb5 JL	363	/*
	364	* BOOTP options
	365	*/
	366	#define CONFIG_BOOTP_BOOTFILESIZE
	367	#define CONFIG_BOOTP_BOOTPATH
	368	#define CONFIG_BOOTP_GATEWAY
	369	#define CONFIG_BOOTP_HOSTNAME
	370
	371
2835e518 JL	372	/*
	373	* Command line configuration.
	374	*/
	375	#include <config_cmd_default.h>
	376
	377	#define CONFIG_CMD_PING
	378	#define CONFIG_CMD_I2C
	379
	380	#if defined(CONFIG_PCI)
	381	#define CONFIG_CMD_PCI
	382	#endif
	383
	384	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
	385	#define CONFIG_CMD_MII
	386	#endif
	387
6d0f6bcf	388	#if defined(CONFIG_SYS_RAMBOOT)
bdab39d3	389	#undef CONFIG_CMD_SAVEENV
2835e518	390	#undef CONFIG_CMD_LOADS
c15f3120 WD	391	#endif
c15f3120 WD	392
c15f3120 WD	393
	394	#undef CONFIG_WATCHDOG /* watchdog disabled */
	395
	396	/*
	397	* Miscellaneous configurable options
	398	*/
6d0f6bcf JCPV	399	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	400	#define CONFIG_SYS_PROMPT "SBC8540=> " /* Monitor Command Prompt */
2835e518	401	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	402	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c15f3120	403	#else
6d0f6bcf	404	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c15f3120	405	#endif
6d0f6bcf JCPV	406	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	407	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	408	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	409	#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
	410	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c15f3120 WD	411
	412	/*
	413	* For booting Linux, the board info and command line data
	414	* have to be in the first 8 MB of memory, since this is
	415	* the maximum mapped by the Linux kernel during initialization.
	416	*/
6d0f6bcf	417	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c15f3120	418
c15f3120 WD	419	/*
	420	* Internal Definitions
	421	*
	422	* Boot Flags
	423	*/
	424	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	425	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	426
2835e518	427	#if defined(CONFIG_CMD_KGDB)
c15f3120 WD	428	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	429	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	430	#endif
	431
	432	/Note: change below for your network setting!!! /
	433	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
e2ffd59b WD	434	# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
	435	# define CONFIG_HAS_ETH1
	436	# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
	437	# define CONFIG_HAS_ETH2
	438	# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
c15f3120 WD	439	#endif
	440
	441	#define CONFIG_SERVERIP YourServerIP
	442	#define CONFIG_IPADDR YourTargetIP
	443	#define CONFIG_GATEWAYIP YourGatewayIP
	444	#define CONFIG_NETMASK 255.255.255.0
	445	#define CONFIG_HOSTNAME SBC8560
	446	#define CONFIG_ROOTPATH YourRootPath
	447	#define CONFIG_BOOTFILE YourImageName
	448
	449	#endif /* __CONFIG_H */