[people/ms/u-boot.git] / include / configs / SBC8540.h

/*
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
 * Added support for Wind River SBC8540 board
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* mpc8560ads board configuration file */
/* please refer to doc/README.mpc85xx for more info */
/* make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#if XXX
#define DEBUG		      /* General debug */
#define ET_DEBUG
#endif
#define TSEC_DEBUG

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE			*/
#define CONFIG_E500		1	/* BOOKE e500 family		*/
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560		*/
#define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip		*/


#define CONFIG_CPM2		1	/* has CPM2 */

#define CONFIG_SBC8540		1	/* configuration for SBC8560 board */

#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific (supplement)	*/

#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
#undef	CONFIG_PCI			/* pci ethernet support		*/
#undef  CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support	*/

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

#define CONFIG_ENV_OVERWRITE

/* Using Localbus SDRAM to emulate flash before we can program the flash,
 * normally you need a flash-boot image(u-boot.bin), if so undef this.
 */
#undef CONFIG_RAM_AS_FLASH

#if defined(CONFIG_PCI_66)			/* some PCI card is 33Mhz only	*/
  #define CONFIG_SYS_CLK_FREQ	66000000	/* sysclk for MPC85xx		*/
#else
  #define CONFIG_SYS_CLK_FREQ	33000000	/* most pci cards are 33Mhz	*/
#endif

/* below can be toggled for performance analysis. otherwise use default */
#define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
#undef	CONFIG_BTB			    /* toggle branch predition	*/
#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/

#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/

#undef	CFG_DRAM_TEST			    /* memory test, takes time	*/
#define CFG_MEMTEST_START	0x00200000  /* memtest region */
#define CFG_MEMTEST_END		0x00400000

#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
     defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
     defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
#endif

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/

#if XXX
  #define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
#else
  #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
#endif
#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/

#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
#define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */

#undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
#undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */

#if defined(CONFIG_MPC85xx_REV1)
  #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
#endif

#undef CONFIG_CLOCKS_IN_MHZ

#if defined(CONFIG_RAM_AS_FLASH)
  #define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
  #define CFG_FLASH_BASE	0xf8000000      /* start of FLASH 8M  */
  #define CFG_BR0_PRELIM	0xf8000801      /* port size 8bit */
  #define CFG_OR0_PRELIM	0xf8000ff7	/* 8MB Flash		*/
#else /* Boot from real Flash */
  #define CFG_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
  #define CFG_FLASH_BASE	0xff800000      /* start of FLASH 8M    */
  #define CFG_BR0_PRELIM	0xff800801      /* port size 8bit      */
  #define CFG_OR0_PRELIM	0xff800ff7	/* 8MB Flash		*/
#endif
#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/

/* local bus definitions */
#define CFG_BR1_PRELIM		0xe4001801	/* 64M, 32-bit flash */
#define CFG_OR1_PRELIM		0xfc000ff7

#define CFG_BR2_PRELIM		0x00000000	/* CS2 not used */
#define CFG_OR2_PRELIM		0x00000000

#define CFG_BR3_PRELIM		0xf0001861	/* 64MB localbus SDRAM	*/
#define CFG_OR3_PRELIM		0xfc000cc1

#if defined(CONFIG_RAM_AS_FLASH)
  #define CFG_BR4_PRELIM	0xf4001861	/* 64M localbus SDRAM */
#else
  #define CFG_BR4_PRELIM	0xf8001861	/* 64M localbus SDRAM */
#endif
#define CFG_OR4_PRELIM		0xfc000cc1

#define CFG_BR5_PRELIM		0xfc000801	/* 16M CS5 misc devices */
#if 1
  #define CFG_OR5_PRELIM	0xff000ff7
#else
  #define CFG_OR5_PRELIM	0xff0000f0
#endif

#define CFG_BR6_PRELIM		0xe0001801	/* 64M, 32-bit flash */
#define CFG_OR6_PRELIM		0xfc000ff7
#define CFG_LBC_LCRR		0x00030002	/* local bus freq	*/
#define CFG_LBC_LBCR		0x00000000
#define CFG_LBC_LSRT		0x20000000
#define CFG_LBC_MRTPR		0x20000000
#define CFG_LBC_LSDMR_1		0x2861b723
#define CFG_LBC_LSDMR_2		0x0861b723
#define CFG_LBC_LSDMR_3		0x0861b723
#define CFG_LBC_LSDMR_4		0x1861b723
#define CFG_LBC_LSDMR_5		0x4061b723

/* just hijack the MOT BCSR def for SBC8560 misc devices */
#define CFG_BCSR		((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
/* the size of CS5 needs to be >= 16M for TLB and LAW setups */

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */

#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */

/* Serial Port */
#undef  CONFIG_CONS_ON_SCC			/* define if console on SCC */
#undef	CONFIG_CONS_NONE			/* define if console on something else */

#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#if 0
#define CFG_NS16550_CLK		1843200 /* get_bus_freq(0) */
#else
#define CFG_NS16550_CLK		264000000 /* get_bus_freq(0) */
#endif

#define CONFIG_BAUDRATE		9600

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#if 0
#define CFG_NS16550_COM1	((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
#define CFG_NS16550_COM2	((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
#else
/* SBC8540 uses internal COMM controller */
#define CFG_NS16550_COM1	((CFG_CCSRBAR & 0xfff00000)+0x00004500)
#define CFG_NS16550_COM2	((CFG_CCSRBAR & 0xfff00000)+0x00004600)
#endif

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
#define CFG_I2C_OFFSET		0x3000

#define CFG_PCI_MEM_BASE	0xC0000000
#define CFG_PCI_MEM_PHYS	0xC0000000
#define CFG_PCI_MEM_SIZE	0x10000000

#if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */

#  define CONFIG_NET_MULTI	1
#  define CONFIG_MPC85xx_TSEC1
#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
#  define CONFIG_MII		1	/* MII PHY management		*/
#  define TSEC1_PHY_ADDR	25
#  define TSEC1_PHYIDX		0
/* Options are: TSEC0 */
#  define CONFIG_ETHPRIME		"TSEC0"


#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */

  #undef  CONFIG_ETHER_NONE		/* define if ether on something else */
  #define CONFIG_ETHER_ON_FCC2		/* cpm FCC ethernet support	*/
  #define CONFIG_ETHER_INDEX	2	/* which channel for ether  */

  #if (CONFIG_ETHER_INDEX == 2)
    /*
     * - Rx-CLK is CLK13
     * - Tx-CLK is CLK14
     * - Select bus for bd/buffers
     * - Full duplex
     */
    #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
    #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
    #define CFG_CPMFCR_RAMTYPE	0
    #define CFG_FCC_PSMR	(FCC_PSMR_FDE)

  #elif (CONFIG_ETHER_INDEX == 3)
    /* need more definitions here for FE3 */
  #endif				/* CONFIG_ETHER_INDEX */

  #define CONFIG_MII			/* MII PHY management */
  #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
  /*
   * GPIO pins used for bit-banged MII communications
   */
  #define MDIO_PORT	2		/* Port C */
  #define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
  #define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
  #define MDIO_READ	((iop->pdat &  0x00400000) != 0)

  #define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
			else	iop->pdat &= ~0x00400000

  #define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
			else	iop->pdat &= ~0x00200000

  #define MIIDELAY	udelay(1)

#endif

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
#if 0
#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
#define CFG_FLASH_PROTECTION		/* use hardware protection		*/
#endif
#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/

#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	200000		/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	50000		/* Timeout for Flash Write (in ms)	*/

#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/

#if 0
/* XXX This doesn't work and I don't want to fix it */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
  #define CFG_RAMBOOT
#else
  #undef  CFG_RAMBOOT
#endif
#endif

/* Environment */
#if !defined(CFG_RAMBOOT)
  #if defined(CONFIG_RAM_AS_FLASH)
    #define CFG_ENV_IS_NOWHERE
    #define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x100000)
    #define CFG_ENV_SIZE	0x2000
  #else
    #define CFG_ENV_IS_IN_FLASH	1
    #define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
    #define CFG_ENV_ADDR	(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
    #define CFG_ENV_SIZE	0x2000 /* CFG_ENV_SECT_SIZE */
  #endif
#else
  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
  #define CFG_ENV_SIZE		0x2000
#endif

#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
/*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
#define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
    #define CONFIG_CMD_MII
#endif

#if defined(CFG_RAMBOOT)
    #undef CONFIG_CMD_ENV
    #undef CONFIG_CMD_LOADS
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"SBC8540=> " /* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
  #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
  #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_LOAD_ADDR	0x1000000	/* default load address */
#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot		*/

#if defined(CONFIG_CMD_KGDB)
  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
  #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#  define CONFIG_ETHADDR	00:vv:ww:xx:yy:8a
#  define CONFIG_HAS_ETH1
#  define CONFIG_ETH1ADDR	00:vv:ww:xx:yy:8b
#  define CONFIG_HAS_ETH2
#  define CONFIG_ETH2ADDR	00:vv:ww:xx:yy:8c
#endif

#define CONFIG_SERVERIP		YourServerIP
#define CONFIG_IPADDR		YourTargetIP
#define CONFIG_GATEWAYIP	YourGatewayIP
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_HOSTNAME		SBC8560
#define CONFIG_ROOTPATH		YourRootPath
#define CONFIG_BOOTFILE		YourImageName

#endif	/* __CONFIG_H */
Commit	Line	Data
c15f3120 WD	1	/*
	2	* (C) Copyright 2002,2003 Motorola,Inc.
	3	* Xianghua Xiao <X.Xiao@motorola.com>
	4	*
	5	* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
	6	* Added support for Wind River SBC8540 board
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/* mpc8560ads board configuration file */
	28	/* please refer to doc/README.mpc85xx for more info */
	29	/* make sure you change the MAC address and other network params first,
	30	* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
	31	*/
8b74bf31	32
c15f3120 WD	33	#ifndef __CONFIG_H
	34	#define __CONFIG_H
	35
	36	#if XXX
	37	#define DEBUG /* General debug */
	38	#define ET_DEBUG
	39	#endif
	40	#define TSEC_DEBUG
	41
	42	/* High Level Configuration Options */
	43	#define CONFIG_BOOKE 1 /* BOOKE */
	44	#define CONFIG_E500 1 /* BOOKE e500 family */
	45	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
	46	#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
	47
	48
9c4c5ae3	49	#define CONFIG_CPM2 1 /* has CPM2 */
c15f3120	50
53677ef1	51	#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
c15f3120 WD	52
	53	#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
	54
	55	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	56	#undef CONFIG_PCI /* pci ethernet support */
	57	#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
	58
e2b159d0	59	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
c15f3120 WD	60
	61	#define CONFIG_ENV_OVERWRITE
	62
	63	/* Using Localbus SDRAM to emulate flash before we can program the flash,
	64	* normally you need a flash-boot image(u-boot.bin), if so undef this.
	65	*/
	66	#undef CONFIG_RAM_AS_FLASH
	67
	68	#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
	69	#define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
	70	#else
	71	#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
	72	#endif
	73
	74	/* below can be toggled for performance analysis. otherwise use default */
	75	#define CONFIG_L2_CACHE /* toggle L2 cache */
	76	#undef CONFIG_BTB /* toggle branch predition */
	77	#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
	78
	79	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	80
	81	#undef CFG_DRAM_TEST /* memory test, takes time */
	82	#define CFG_MEMTEST_START 0x00200000 /* memtest region */
	83	#define CFG_MEMTEST_END 0x00400000
	84
	85	#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) \|\| \
	86	defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) \|\| \
	87	defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
	88	#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
	89	#endif
	90
	91	/*
	92	* Base addresses -- Note these are effective addresses where the
	93	* actual resources get mapped (not physical addresses)
	94	*/
	95	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
	96
	97	#if XXX
	98	#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
	99	#else
	100	#define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
	101	#endif
f69766e4	102	#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
c15f3120 WD	103	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
	104
	105	#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
	106	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
	107	#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
	108	#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */
	109
	110	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	111	#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	112
	113	#if defined(CONFIG_MPC85xx_REV1)
	114	#define CONFIG_DDR_DLL /* possible DLL fix needed */
	115	#endif
	116
	117	#undef CONFIG_CLOCKS_IN_MHZ
	118
	119	#if defined(CONFIG_RAM_AS_FLASH)
	120	#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
	121	#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
	122	#define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */
	123	#define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
	124	#else /* Boot from real Flash */
	125	#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
	126	#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
	127	#define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */
	128	#define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
	129	#endif
	130	#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
	131
	132	/* local bus definitions */
	133	#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
	134	#define CFG_OR1_PRELIM 0xfc000ff7
	135
	136	#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */
	137	#define CFG_OR2_PRELIM 0x00000000
	138
	139	#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
	140	#define CFG_OR3_PRELIM 0xfc000cc1
	141
	142	#if defined(CONFIG_RAM_AS_FLASH)
	143	#define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
	144	#else
	145	#define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
	146	#endif
	147	#define CFG_OR4_PRELIM 0xfc000cc1
	148
	149	#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
	150	#if 1
	151	#define CFG_OR5_PRELIM 0xff000ff7
	152	#else
	153	#define CFG_OR5_PRELIM 0xff0000f0
	154	#endif
	155
	156	#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
	157	#define CFG_OR6_PRELIM 0xfc000ff7
	158	#define CFG_LBC_LCRR 0x00030002 /* local bus freq */
	159	#define CFG_LBC_LBCR 0x00000000
	160	#define CFG_LBC_LSRT 0x20000000
	161	#define CFG_LBC_MRTPR 0x20000000
	162	#define CFG_LBC_LSDMR_1 0x2861b723
	163	#define CFG_LBC_LSDMR_2 0x0861b723
	164	#define CFG_LBC_LSDMR_3 0x0861b723
	165	#define CFG_LBC_LSDMR_4 0x1861b723
	166	#define CFG_LBC_LSDMR_5 0x4061b723
167
168	/* just hijack the MOT BCSR def for SBC8560 misc devices */
169	#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)\|0x00400000)
170	/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
171
172	#define CONFIG_L1_INIT_RAM
173	#define CFG_INIT_RAM_LOCK 1
174	#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
175	#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
176
177	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
178	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
179	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
180
181	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
182	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
183
184	/* Serial Port */
185	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
186	#undef CONFIG_CONS_NONE /* define if console on something else */
187
188	#define CONFIG_CONS_INDEX 1
189	#undef CONFIG_SERIAL_SOFTWARE_FIFO
190	#define CFG_NS16550
191	#define CFG_NS16550_SERIAL
192	#define CFG_NS16550_REG_SIZE 1
193	#if 0
194	#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */
195	#else
196	#define CFG_NS16550_CLK 264000000 /* get_bus_freq(0) */
197	#endif
198
199	#define CONFIG_BAUDRATE 9600
200
201	#define CFG_BAUDRATE_TABLE \
202	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
203
204	#if 0
205	#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
206	#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
207	#else
8b74bf31	208	/* SBC8540 uses internal COMM controller */
c15f3120 WD	209	#define CFG_NS16550_COM1 ((CFG_CCSRBAR & 0xfff00000)+0x00004500)
	210	#define CFG_NS16550_COM2 ((CFG_CCSRBAR & 0xfff00000)+0x00004600)
	211	#endif
	212
	213	/* Use the HUSH parser */
	214	#define CFG_HUSH_PARSER
	215	#ifdef CFG_HUSH_PARSER
	216	#define CFG_PROMPT_HUSH_PS2 "> "
	217	#endif
	218
20476726 JL	219	/*
	220	* I2C
	221	*/
	222	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	223	#define CONFIG_HARD_I2C /* I2C with hardware support*/
c15f3120 WD	224	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	225	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	226	#define CFG_I2C_SLAVE 0x7F
	227	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
20476726	228	#define CFG_I2C_OFFSET 0x3000
c15f3120 WD	229
	230	#define CFG_PCI_MEM_BASE 0xC0000000
	231	#define CFG_PCI_MEM_PHYS 0xC0000000
	232	#define CFG_PCI_MEM_SIZE 0x10000000
	233
	234	#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
	235
d9b94f28 JL	236	# define CONFIG_NET_MULTI 1
	237	# define CONFIG_MPC85xx_TSEC1
	238	# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
	239	# define CONFIG_MII 1 /* MII PHY management */
	240	# define TSEC1_PHY_ADDR 25
	241	# define TSEC1_PHYIDX 0
	242	/* Options are: TSEC0 */
	243	# define CONFIG_ETHPRIME "TSEC0"
c15f3120	244
8b74bf31	245
c15f3120 WD	246	#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
	247
	248	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	249	#define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
	250	#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
8b74bf31	251
c15f3120 WD	252	#if (CONFIG_ETHER_INDEX == 2)
	253	/*
	254	* - Rx-CLK is CLK13
	255	* - Tx-CLK is CLK14
	256	* - Select bus for bd/buffers
	257	* - Full duplex
	258	*/
	259	#define CFG_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	260	#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
	261	#define CFG_CPMFCR_RAMTYPE 0
	262	#define CFG_FCC_PSMR (FCC_PSMR_FDE)
8b74bf31	263
c15f3120 WD	264	#elif (CONFIG_ETHER_INDEX == 3)
	265	/* need more definitions here for FE3 */
	266	#endif /* CONFIG_ETHER_INDEX */
8b74bf31	267
c15f3120 WD	268	#define CONFIG_MII /* MII PHY management */
	269	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
	270	/*
	271	* GPIO pins used for bit-banged MII communications
	272	*/
	273	#define MDIO_PORT 2 /* Port C */
	274	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	275	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	276	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
	277
	278	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
	279	else iop->pdat &= ~0x00400000
	280
	281	#define MDC(bit) if(bit) iop->pdat \|= 0x00200000; \
	282	else iop->pdat &= ~0x00200000
	283
	284	#define MIIDELAY udelay(1)
8b74bf31	285
c15f3120 WD	286	#endif
	287
	288	/*-----------------------------------------------------------------------
	289	* FLASH and environment organization
	290	*/
	291
	292	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
	293	#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
	294	#if 0
	295	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	296	#define CFG_FLASH_PROTECTION /* use hardware protection */
	297	#endif
	298	#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
	299	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	300
	301	#undef CFG_FLASH_CHECKSUM
	302	#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
	303	#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
	304
	305	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
	306
	307	#if 0
	308	/* XXX This doesn't work and I don't want to fix it */
	309	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	310	#define CFG_RAMBOOT
	311	#else
	312	#undef CFG_RAMBOOT
	313	#endif
	314	#endif
	315
	316	/* Environment */
	317	#if !defined(CFG_RAMBOOT)
	318	#if defined(CONFIG_RAM_AS_FLASH)
	319	#define CFG_ENV_IS_NOWHERE
	320	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
	321	#define CFG_ENV_SIZE 0x2000
	322	#else
	323	#define CFG_ENV_IS_IN_FLASH 1
	324	#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
	325	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
	326	#define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */
	327	#endif
	328	#else
	329	#define CFG_NO_FLASH 1 /* Flash is not usable now */
	330	#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	331	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	332	#define CFG_ENV_SIZE 0x2000
	333	#endif
	334
	335	#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
	336	/#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"/
	337	#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
	338	#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
	339
	340	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	341	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	342
2835e518	343
a1aa0bb5 JL	344	/*
	345	* BOOTP options
	346	*/
	347	#define CONFIG_BOOTP_BOOTFILESIZE
	348	#define CONFIG_BOOTP_BOOTPATH
	349	#define CONFIG_BOOTP_GATEWAY
	350	#define CONFIG_BOOTP_HOSTNAME
	351
	352
2835e518 JL	353	/*
	354	* Command line configuration.
	355	*/
	356	#include <config_cmd_default.h>
	357
	358	#define CONFIG_CMD_PING
	359	#define CONFIG_CMD_I2C
	360
	361	#if defined(CONFIG_PCI)
	362	#define CONFIG_CMD_PCI
	363	#endif
	364
	365	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
	366	#define CONFIG_CMD_MII
	367	#endif
	368
	369	#if defined(CFG_RAMBOOT)
	370	#undef CONFIG_CMD_ENV
	371	#undef CONFIG_CMD_LOADS
c15f3120 WD	372	#endif
c15f3120 WD	373
c15f3120 WD	374
	375	#undef CONFIG_WATCHDOG /* watchdog disabled */
	376
	377	/*
	378	* Miscellaneous configurable options
	379	*/
	380	#define CFG_LONGHELP /* undef to save memory */
	381	#define CFG_PROMPT "SBC8540=> " /* Monitor Command Prompt */
2835e518	382	#if defined(CONFIG_CMD_KGDB)
c15f3120 WD	383	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	384	#else
	385	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	386	#endif
	387	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	388	#define CFG_MAXARGS 16 /* max number of command args */
	389	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	390	#define CFG_LOAD_ADDR 0x1000000 /* default load address */
	391	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	392
	393	/*
	394	* For booting Linux, the board info and command line data
	395	* have to be in the first 8 MB of memory, since this is
	396	* the maximum mapped by the Linux kernel during initialization.
	397	*/
	398	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	399
c15f3120 WD	400	/*
	401	* Internal Definitions
	402	*
	403	* Boot Flags
	404	*/
	405	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	406	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	407
2835e518	408	#if defined(CONFIG_CMD_KGDB)
c15f3120 WD	409	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	410	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	411	#endif
	412
	413	/Note: change below for your network setting!!! /
	414	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
e2ffd59b WD	415	# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
	416	# define CONFIG_HAS_ETH1
	417	# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
	418	# define CONFIG_HAS_ETH2
	419	# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
c15f3120 WD	420	#endif
	421
	422	#define CONFIG_SERVERIP YourServerIP
	423	#define CONFIG_IPADDR YourTargetIP
	424	#define CONFIG_GATEWAYIP YourGatewayIP
	425	#define CONFIG_NETMASK 255.255.255.0
	426	#define CONFIG_HOSTNAME SBC8560
	427	#define CONFIG_ROOTPATH YourRootPath
	428	#define CONFIG_BOOTFILE YourImageName
	429
	430	#endif /* __CONFIG_H */