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c15f3120 WD |
1 | /* |
2 | * (C) Copyright 2002,2003 Motorola,Inc. | |
3 | * Xianghua Xiao <X.Xiao@motorola.com> | |
4 | * | |
5 | * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. | |
6 | * Added support for Wind River SBC8540 board | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* mpc8560ads board configuration file */ | |
28 | /* please refer to doc/README.mpc85xx for more info */ | |
29 | /* make sure you change the MAC address and other network params first, | |
30 | * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file | |
31 | */ | |
8b74bf31 | 32 | |
c15f3120 WD |
33 | #ifndef __CONFIG_H |
34 | #define __CONFIG_H | |
35 | ||
36 | #if XXX | |
37 | #define DEBUG /* General debug */ | |
38 | #define ET_DEBUG | |
39 | #endif | |
40 | #define TSEC_DEBUG | |
41 | ||
42 | /* High Level Configuration Options */ | |
43 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
44 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
45 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ | |
46 | #define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ | |
47 | ||
48 | ||
9c4c5ae3 | 49 | #define CONFIG_CPM2 1 /* has CPM2 */ |
c15f3120 | 50 | |
53677ef1 | 51 | #define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ |
f060054d | 52 | #define CONFIG_MPC8540 1 |
c15f3120 WD |
53 | |
54 | #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ | |
55 | ||
56 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
57 | #undef CONFIG_PCI /* pci ethernet support */ | |
58 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ | |
59 | ||
e2b159d0 | 60 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
c15f3120 WD |
61 | |
62 | #define CONFIG_ENV_OVERWRITE | |
63 | ||
64 | /* Using Localbus SDRAM to emulate flash before we can program the flash, | |
65 | * normally you need a flash-boot image(u-boot.bin), if so undef this. | |
66 | */ | |
67 | #undef CONFIG_RAM_AS_FLASH | |
68 | ||
69 | #if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ | |
70 | #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */ | |
71 | #else | |
72 | #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ | |
73 | #endif | |
74 | ||
75 | /* below can be toggled for performance analysis. otherwise use default */ | |
76 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
77 | #undef CONFIG_BTB /* toggle branch predition */ | |
c15f3120 WD |
78 | |
79 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
80 | ||
6d0f6bcf JCPV |
81 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
82 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
83 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
c15f3120 WD |
84 | |
85 | #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ | |
86 | defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ | |
87 | defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) | |
88 | #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." | |
89 | #endif | |
90 | ||
91 | /* | |
92 | * Base addresses -- Note these are effective addresses where the | |
93 | * actual resources get mapped (not physical addresses) | |
94 | */ | |
6d0f6bcf | 95 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
c15f3120 WD |
96 | |
97 | #if XXX | |
6d0f6bcf | 98 | #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ |
c15f3120 | 99 | #else |
6d0f6bcf | 100 | #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */ |
c15f3120 | 101 | #endif |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ |
103 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
c15f3120 | 104 | |
6d0f6bcf | 105 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
c15f3120 | 106 | |
8e55313b KG |
107 | /* DDR Setup */ |
108 | #define CONFIG_FSL_DDR1 | |
109 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
c15f3120 WD |
110 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
111 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
8e55313b | 112 | #undef CONFIG_DDR_SPD |
c15f3120 WD |
113 | |
114 | #if defined(CONFIG_MPC85xx_REV1) | |
115 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ | |
116 | #endif | |
117 | ||
8e55313b KG |
118 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
119 | #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
120 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
121 | ||
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
123 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
8e55313b KG |
124 | #define CONFIG_VERY_BIG_RAM |
125 | ||
126 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
127 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
128 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
129 | ||
130 | /* I2C addresses of SPD EEPROMs */ | |
131 | #define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */ | |
132 | ||
c15f3120 WD |
133 | #undef CONFIG_CLOCKS_IN_MHZ |
134 | ||
135 | #if defined(CONFIG_RAM_AS_FLASH) | |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ |
137 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ | |
138 | #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */ | |
139 | #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ | |
c15f3120 | 140 | #else /* Boot from real Flash */ |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ |
142 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ | |
143 | #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */ | |
144 | #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ | |
c15f3120 | 145 | #endif |
6d0f6bcf | 146 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
c15f3120 WD |
147 | |
148 | /* local bus definitions */ | |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ |
150 | #define CONFIG_SYS_OR1_PRELIM 0xfc000ff7 | |
c15f3120 | 151 | |
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */ |
153 | #define CONFIG_SYS_OR2_PRELIM 0x00000000 | |
c15f3120 | 154 | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ |
156 | #define CONFIG_SYS_OR3_PRELIM 0xfc000cc1 | |
c15f3120 WD |
157 | |
158 | #if defined(CONFIG_RAM_AS_FLASH) | |
6d0f6bcf | 159 | #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ |
c15f3120 | 160 | #else |
6d0f6bcf | 161 | #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ |
c15f3120 | 162 | #endif |
6d0f6bcf | 163 | #define CONFIG_SYS_OR4_PRELIM 0xfc000cc1 |
c15f3120 | 164 | |
6d0f6bcf | 165 | #define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ |
c15f3120 | 166 | #if 1 |
6d0f6bcf | 167 | #define CONFIG_SYS_OR5_PRELIM 0xff000ff7 |
c15f3120 | 168 | #else |
6d0f6bcf | 169 | #define CONFIG_SYS_OR5_PRELIM 0xff0000f0 |
c15f3120 WD |
170 | #endif |
171 | ||
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ |
173 | #define CONFIG_SYS_OR6_PRELIM 0xfc000ff7 | |
174 | #define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */ | |
175 | #define CONFIG_SYS_LBC_LBCR 0x00000000 | |
176 | #define CONFIG_SYS_LBC_LSRT 0x20000000 | |
177 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
178 | #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 | |
179 | #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 | |
180 | #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 | |
181 | #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 | |
182 | #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 | |
c15f3120 WD |
183 | |
184 | /* just hijack the MOT BCSR def for SBC8560 misc devices */ | |
6d0f6bcf | 185 | #define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000) |
c15f3120 WD |
186 | /* the size of CS5 needs to be >= 16M for TLB and LAW setups */ |
187 | ||
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
189 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ | |
190 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
c15f3120 | 191 | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
193 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
194 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
c15f3120 | 195 | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
197 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
c15f3120 WD |
198 | |
199 | /* Serial Port */ | |
200 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
201 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
202 | ||
203 | #define CONFIG_CONS_INDEX 1 | |
204 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_NS16550 |
206 | #define CONFIG_SYS_NS16550_SERIAL | |
207 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
c15f3120 | 208 | #if 0 |
6d0f6bcf | 209 | #define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */ |
c15f3120 | 210 | #else |
6d0f6bcf | 211 | #define CONFIG_SYS_NS16550_CLK 264000000 /* get_bus_freq(0) */ |
c15f3120 WD |
212 | #endif |
213 | ||
214 | #define CONFIG_BAUDRATE 9600 | |
215 | ||
6d0f6bcf | 216 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
c15f3120 WD |
217 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
218 | ||
219 | #if 0 | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000) |
221 | #define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000) | |
c15f3120 | 222 | #else |
8b74bf31 | 223 | /* SBC8540 uses internal COMM controller */ |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500) |
225 | #define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600) | |
c15f3120 WD |
226 | #endif |
227 | ||
228 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_HUSH_PARSER |
230 | #ifdef CONFIG_SYS_HUSH_PARSER | |
231 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
c15f3120 WD |
232 | #endif |
233 | ||
20476726 JL |
234 | /* |
235 | * I2C | |
236 | */ | |
237 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
238 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
c15f3120 | 239 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
240 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
241 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
242 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
243 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
c15f3120 | 244 | |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000 |
246 | #define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000 | |
247 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 | |
c15f3120 WD |
248 | |
249 | #if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ | |
250 | ||
d9b94f28 JL |
251 | # define CONFIG_NET_MULTI 1 |
252 | # define CONFIG_MPC85xx_TSEC1 | |
253 | # define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" | |
254 | # define CONFIG_MII 1 /* MII PHY management */ | |
255 | # define TSEC1_PHY_ADDR 25 | |
256 | # define TSEC1_PHYIDX 0 | |
257 | /* Options are: TSEC0 */ | |
258 | # define CONFIG_ETHPRIME "TSEC0" | |
c15f3120 | 259 | |
8b74bf31 | 260 | |
c15f3120 WD |
261 | #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ |
262 | ||
263 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
264 | #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ | |
265 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ | |
8b74bf31 | 266 | |
c15f3120 WD |
267 | #if (CONFIG_ETHER_INDEX == 2) |
268 | /* | |
269 | * - Rx-CLK is CLK13 | |
270 | * - Tx-CLK is CLK14 | |
271 | * - Select bus for bd/buffers | |
272 | * - Full duplex | |
273 | */ | |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
275 | #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
276 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
277 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) | |
8b74bf31 | 278 | |
c15f3120 WD |
279 | #elif (CONFIG_ETHER_INDEX == 3) |
280 | /* need more definitions here for FE3 */ | |
281 | #endif /* CONFIG_ETHER_INDEX */ | |
8b74bf31 | 282 | |
c15f3120 WD |
283 | #define CONFIG_MII /* MII PHY management */ |
284 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
285 | /* | |
286 | * GPIO pins used for bit-banged MII communications | |
287 | */ | |
288 | #define MDIO_PORT 2 /* Port C */ | |
289 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) | |
290 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
291 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
292 | ||
293 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
294 | else iop->pdat &= ~0x00400000 | |
295 | ||
296 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
297 | else iop->pdat &= ~0x00200000 | |
298 | ||
299 | #define MIIDELAY udelay(1) | |
8b74bf31 | 300 | |
c15f3120 WD |
301 | #endif |
302 | ||
303 | /*----------------------------------------------------------------------- | |
304 | * FLASH and environment organization | |
305 | */ | |
306 | ||
6d0f6bcf | 307 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 308 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
c15f3120 | 309 | #if 0 |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
311 | #define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */ | |
c15f3120 | 312 | #endif |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
314 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
c15f3120 | 315 | |
6d0f6bcf JCPV |
316 | #undef CONFIG_SYS_FLASH_CHECKSUM |
317 | #define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ | |
318 | #define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ | |
c15f3120 | 319 | |
6d0f6bcf | 320 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
c15f3120 WD |
321 | |
322 | #if 0 | |
323 | /* XXX This doesn't work and I don't want to fix it */ | |
6d0f6bcf JCPV |
324 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
325 | #define CONFIG_SYS_RAMBOOT | |
c15f3120 | 326 | #else |
6d0f6bcf | 327 | #undef CONFIG_SYS_RAMBOOT |
c15f3120 WD |
328 | #endif |
329 | #endif | |
330 | ||
331 | /* Environment */ | |
6d0f6bcf | 332 | #if !defined(CONFIG_SYS_RAMBOOT) |
c15f3120 | 333 | #if defined(CONFIG_RAM_AS_FLASH) |
93f6d725 | 334 | #define CONFIG_ENV_IS_NOWHERE |
6d0f6bcf | 335 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000) |
0e8d1586 | 336 | #define CONFIG_ENV_SIZE 0x2000 |
c15f3120 | 337 | #else |
5a1aceb0 | 338 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 339 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
6d0f6bcf | 340 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 341 | #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */ |
c15f3120 WD |
342 | #endif |
343 | #else | |
6d0f6bcf | 344 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 345 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 346 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 347 | #define CONFIG_ENV_SIZE 0x2000 |
c15f3120 WD |
348 | #endif |
349 | ||
350 | #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" | |
351 | /*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ | |
352 | #define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" | |
353 | #define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ | |
354 | ||
355 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 356 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
c15f3120 | 357 | |
2835e518 | 358 | |
a1aa0bb5 JL |
359 | /* |
360 | * BOOTP options | |
361 | */ | |
362 | #define CONFIG_BOOTP_BOOTFILESIZE | |
363 | #define CONFIG_BOOTP_BOOTPATH | |
364 | #define CONFIG_BOOTP_GATEWAY | |
365 | #define CONFIG_BOOTP_HOSTNAME | |
366 | ||
367 | ||
2835e518 JL |
368 | /* |
369 | * Command line configuration. | |
370 | */ | |
371 | #include <config_cmd_default.h> | |
372 | ||
373 | #define CONFIG_CMD_PING | |
374 | #define CONFIG_CMD_I2C | |
375 | ||
376 | #if defined(CONFIG_PCI) | |
377 | #define CONFIG_CMD_PCI | |
378 | #endif | |
379 | ||
380 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
381 | #define CONFIG_CMD_MII | |
382 | #endif | |
383 | ||
6d0f6bcf | 384 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 385 | #undef CONFIG_CMD_SAVEENV |
2835e518 | 386 | #undef CONFIG_CMD_LOADS |
c15f3120 WD |
387 | #endif |
388 | ||
c15f3120 WD |
389 | |
390 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
391 | ||
392 | /* | |
393 | * Miscellaneous configurable options | |
394 | */ | |
6d0f6bcf JCPV |
395 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
396 | #define CONFIG_SYS_PROMPT "SBC8540=> " /* Monitor Command Prompt */ | |
2835e518 | 397 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 398 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
c15f3120 | 399 | #else |
6d0f6bcf | 400 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c15f3120 | 401 | #endif |
6d0f6bcf JCPV |
402 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
403 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
404 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
405 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ | |
406 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
c15f3120 WD |
407 | |
408 | /* | |
409 | * For booting Linux, the board info and command line data | |
410 | * have to be in the first 8 MB of memory, since this is | |
411 | * the maximum mapped by the Linux kernel during initialization. | |
412 | */ | |
6d0f6bcf | 413 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c15f3120 | 414 | |
c15f3120 WD |
415 | /* |
416 | * Internal Definitions | |
417 | * | |
418 | * Boot Flags | |
419 | */ | |
420 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
421 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
422 | ||
2835e518 | 423 | #if defined(CONFIG_CMD_KGDB) |
c15f3120 WD |
424 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
425 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
426 | #endif | |
427 | ||
428 | /*Note: change below for your network setting!!! */ | |
429 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
e2ffd59b WD |
430 | # define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a |
431 | # define CONFIG_HAS_ETH1 | |
432 | # define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b | |
433 | # define CONFIG_HAS_ETH2 | |
434 | # define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c | |
c15f3120 WD |
435 | #endif |
436 | ||
437 | #define CONFIG_SERVERIP YourServerIP | |
438 | #define CONFIG_IPADDR YourTargetIP | |
439 | #define CONFIG_GATEWAYIP YourGatewayIP | |
440 | #define CONFIG_NETMASK 255.255.255.0 | |
441 | #define CONFIG_HOSTNAME SBC8560 | |
442 | #define CONFIG_ROOTPATH YourRootPath | |
443 | #define CONFIG_BOOTFILE YourImageName | |
444 | ||
445 | #endif /* __CONFIG_H */ |