projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0f8c9768 WD |
1 | /* |
| 2 | * (C) Copyright 2001 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | /* | |
| 32 | * High Level Configuration Options | |
| 33 | * (easy to change) | |
| 34 | */ | |
| 35 | ||
| 36 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ | |
| 37 | #define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ | |
| 38 | #define CONFIG_SCM 1 /* ...on a System Controller Module */ | |
| 9c4c5ae3 | 39 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
| 0f8c9768 WD |
40 | |
| 41 | #if (CONFIG_TQM8260 <= 100) | |
| 42 | # error "TQM8260 module revison not supported" | |
| 43 | #endif | |
| 44 | ||
| 45 | /* We use a TQM8260 module with a 300MHz CPU */ | |
| 46 | #define CONFIG_300MHz | |
| 47 | ||
| 48 | /* Define 60x busmode only if your TQM8260 has L2 cache! */ | |
| 49 | #ifdef CONFIG_L2_CACHE | |
| 50 | # define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */ | |
| 51 | #else | |
| 52 | # undef CONFIG_BUSMODE_60x /* bus mode: 8260 */ | |
| 53 | #endif | |
| 54 | ||
| 55 | /* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */ | |
| 56 | #ifdef CONFIG_300MHz | |
| 57 | # define CONFIG_BUSMODE_60x | |
| 58 | #endif | |
| 59 | ||
| 60 | #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ | |
| 61 | ||
| 62 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 63 | ||
| 64 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
| 65 | ||
| 32bf3d14 | 66 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
| 0f8c9768 WD |
67 | |
| 68 | #undef CONFIG_BOOTARGS | |
| 69 | #define CONFIG_BOOTCOMMAND \ | |
| 53677ef1 WD |
70 | "bootp; " \ |
| 71 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
| 72 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
| 0f8c9768 WD |
73 | "bootm" |
| 74 | ||
| 75 | /* enable I2C and select the hardware/software driver */ | |
| 76 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 77 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
| 78 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 79 | #define CFG_I2C_SLAVE 0x7F | |
| 80 | ||
| 81 | /* | |
| 82 | * Software (bit-bang) I2C driver configuration | |
| 83 | */ | |
| 84 | ||
| 85 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
| 86 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
| 87 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
| 88 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
| 89 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
| 90 | else iop->pdat &= ~0x00010000 | |
| 91 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
| 92 | else iop->pdat &= ~0x00020000 | |
| 93 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
| 94 | ||
| 95 | #define CFG_I2C_EEPROM_ADDR 0x50 | |
| 96 | #define CFG_I2C_EEPROM_ADDR_LEN 2 | |
| 97 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 | |
| 98 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
| 99 | ||
| 100 | #define CONFIG_I2C_X | |
| 101 | ||
| 102 | /* | |
| 103 | * select serial console configuration | |
| 104 | * | |
| 105 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
| 106 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
| 107 | * for SCC). | |
| 108 | * | |
| 109 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
| 110 | * defined elsewhere (for example, on the cogent platform, there are serial | |
| 111 | * ports on the motherboard which are used for the serial console - see | |
| 112 | * cogent/cma101/serial.[ch]). | |
| 113 | */ | |
| 114 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
| 115 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
| 116 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
| 117 | #ifdef CONFIG_82xx_CONS_SMC1 | |
| 118 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
| 119 | #endif | |
| 120 | #ifdef CONFIG_82xx_CONS_SMC2 | |
| 121 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
| 122 | #endif | |
| 123 | ||
| 124 | #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ | |
| 125 | #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ | |
| 126 | #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ | |
| 127 | ||
| 128 | /* | |
| 129 | * select ethernet configuration | |
| 130 | * | |
| 131 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
| 132 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
| 133 | * for FCC) | |
| 134 | * | |
| 135 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
| 639221c7 | 136 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
| 0f8c9768 WD |
137 | * |
| 138 | * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the | |
| 139 | * X.29 connector, and FCC2 is hardwired to the X.1 connector) | |
| 140 | */ | |
| 141 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
| 142 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
| 143 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
| 144 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ | |
| 145 | ||
| 146 | #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) | |
| 147 | ||
| 148 | /* | |
| 149 | * - Rx-CLK is CLK12 | |
| 150 | * - Tx-CLK is CLK11 | |
| 151 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
| 152 | * - Enable Full Duplex in FSMR | |
| 153 | */ | |
| 154 | # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) | |
| 155 | # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11) | |
| 156 | # define CFG_CPMFCR_RAMTYPE 0 | |
| 157 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
| 158 | ||
| 159 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) | |
| 160 | ||
| 161 | /* | |
| 162 | * - Rx-CLK is CLK15 | |
| 163 | * - Tx-CLK is CLK16 | |
| 164 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
| 165 | * - Enable Full Duplex in FSMR | |
| 166 | */ | |
| 167 | # define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) | |
| 53677ef1 | 168 | # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) |
| 0f8c9768 WD |
169 | # define CFG_CPMFCR_RAMTYPE 0 |
| 170 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
| 171 | ||
| 172 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
| 173 | ||
| 174 | ||
| 175 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
| 176 | #ifndef CONFIG_300MHz | |
| 177 | #define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
| 178 | #else | |
| 179 | #define CONFIG_8260_CLKIN 83333000 /* in Hz */ | |
| 180 | #endif | |
| 181 | ||
| 182 | #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) | |
| 183 | #define CONFIG_BAUDRATE 230400 | |
| 184 | #else | |
| 185 | #define CONFIG_BAUDRATE 115200 | |
| 186 | #endif | |
| 187 | ||
| 188 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 189 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
| 190 | ||
| 191 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 192 | ||
| 18225e8d JL |
193 | /* |
| 194 | * BOOTP options | |
| 195 | */ | |
| 196 | #define CONFIG_BOOTP_SUBNETMASK | |
| 197 | #define CONFIG_BOOTP_GATEWAY | |
| 198 | #define CONFIG_BOOTP_HOSTNAME | |
| 199 | #define CONFIG_BOOTP_BOOTPATH | |
| 200 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 0f8c9768 | 201 | |
| 0f8c9768 | 202 | |
| fe7f782d JL |
203 | /* |
| 204 | * Command line configuration. | |
| 205 | */ | |
| 206 | #include <config_cmd_default.h> | |
| 207 | ||
| 208 | #define CONFIG_CMD_DHCP | |
| 209 | #define CONFIG_CMD_I2C | |
| 210 | #define CONFIG_CMD_EEPROM | |
| 211 | #define CONFIG_CMD_BSP | |
| 212 | ||
| 0f8c9768 WD |
213 | |
| 214 | /* | |
| 215 | * Miscellaneous configurable options | |
| 216 | */ | |
| 217 | #define CFG_LONGHELP /* undef to save memory */ | |
| 218 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| fe7f782d | 219 | #if defined(CONFIG_CMD_KGDB) |
| 0f8c9768 WD |
220 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 221 | #else | |
| 222 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 223 | #endif | |
| 224 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 225 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 226 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 227 | ||
| 228 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
| 229 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 230 | ||
| 231 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
| 232 | ||
| 233 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| 234 | ||
| 235 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
| 236 | ||
| 237 | #define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ | |
| 238 | ||
| 239 | #define CONFIG_MISC_INIT_R /* have misc_init_r() function */ | |
| 240 | ||
| 241 | /* | |
| 242 | * For booting Linux, the board info and command line data | |
| 243 | * have to be in the first 8 MB of memory, since this is | |
| 244 | * the maximum mapped by the Linux kernel during initialization. | |
| 245 | */ | |
| 246 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 247 | ||
| 248 | ||
| 249 | /* What should the base address of the main FLASH be and how big is | |
| 250 | * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk | |
| 251 | * The main FLASH is whichever is connected to *CS0. | |
| 252 | */ | |
| 253 | #define CFG_FLASH0_BASE 0x40000000 | |
| 254 | #define CFG_FLASH1_BASE 0x60000000 | |
| 255 | #define CFG_FLASH0_SIZE 32 | |
| 256 | #define CFG_FLASH1_SIZE 32 | |
| 257 | ||
| 258 | /* Flash bank size (for preliminary settings) | |
| 259 | */ | |
| 260 | #define CFG_FLASH_SIZE CFG_FLASH0_SIZE | |
| 261 | ||
| 262 | /*----------------------------------------------------------------------- | |
| 263 | * FLASH organization | |
| 264 | */ | |
| 265 | #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
| 266 | #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
| 267 | ||
| 268 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
| 269 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
| 270 | ||
| 271 | #if 0 | |
| 272 | /* Start port with environment in flash; switch to EEPROM later */ | |
| 5a1aceb0 | 273 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 0e8d1586 JCPV |
274 | #define CONFIG_ENV_ADDR (CFG_FLASH_BASE+0x40000) |
| 275 | #define CONFIG_ENV_SIZE 0x40000 | |
| 276 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
| 0f8c9768 WD |
277 | #else |
| 278 | /* Final version: environment in EEPROM */ | |
| bb1f8b4f | 279 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
| 0e8d1586 JCPV |
280 | #define CONFIG_ENV_OFFSET 0 |
| 281 | #define CONFIG_ENV_SIZE 2048 | |
| 0f8c9768 WD |
282 | #endif |
| 283 | ||
| 284 | /*----------------------------------------------------------------------- | |
| 285 | * Hardware Information Block | |
| 286 | */ | |
| 287 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
| 288 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
| 289 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
| 290 | ||
| 291 | /*----------------------------------------------------------------------- | |
| 292 | * Hard Reset Configuration Words | |
| 293 | * | |
| 294 | * if you change bits in the HRCW, you must also change the CFG_* | |
| 295 | * defines for the various registers affected by the HRCW e.g. changing | |
| 296 | * HRCW_DPPCxx requires you to also change CFG_SIUMCR. | |
| 297 | */ | |
| 298 | #if defined(CONFIG_266MHz) | |
| 299 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ | |
| 8bde7f77 | 300 | HRCW_MODCK_H0111) |
| 0f8c9768 WD |
301 | #elif defined(CONFIG_300MHz) |
| 302 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ | |
| 8bde7f77 | 303 | HRCW_MODCK_H0110) |
| 0f8c9768 WD |
304 | #else |
| 305 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) | |
| 306 | #endif | |
| 307 | ||
| 308 | /* no slaves so just fill with zeros */ | |
| 309 | #define CFG_HRCW_SLAVE1 0 | |
| 310 | #define CFG_HRCW_SLAVE2 0 | |
| 311 | #define CFG_HRCW_SLAVE3 0 | |
| 312 | #define CFG_HRCW_SLAVE4 0 | |
| 313 | #define CFG_HRCW_SLAVE5 0 | |
| 314 | #define CFG_HRCW_SLAVE6 0 | |
| 315 | #define CFG_HRCW_SLAVE7 0 | |
| 316 | ||
| 317 | /*----------------------------------------------------------------------- | |
| 318 | * Internal Memory Mapped Register | |
| 319 | */ | |
| 320 | #define CFG_IMMR 0xFFF00000 | |
| 321 | ||
| 322 | /*----------------------------------------------------------------------- | |
| 323 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 324 | */ | |
| 325 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
| 326 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
| 327 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ | |
| 328 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 329 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 330 | ||
| 331 | /*----------------------------------------------------------------------- | |
| 332 | * Start addresses for the final memory configuration | |
| 333 | * (Set up by the startup code) | |
| 334 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 335 | * | |
| 336 | * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM | |
| 337 | * is mapped at SDRAM_BASE2_PRELIM. | |
| 338 | */ | |
| 339 | #define CFG_SDRAM_BASE 0x00000000 | |
| 340 | #define CFG_FLASH_BASE CFG_FLASH0_BASE | |
| 341 | #define CFG_MONITOR_BASE TEXT_BASE | |
| 342 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 343 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
| 344 | ||
| 345 | /* | |
| 346 | * Internal Definitions | |
| 347 | * | |
| 348 | * Boot Flags | |
| 349 | */ | |
| 350 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
| 351 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 352 | ||
| 353 | ||
| 354 | /*----------------------------------------------------------------------- | |
| 355 | * Hardware Information Block | |
| 356 | */ | |
| 357 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
| 358 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
| 359 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
| 360 | ||
| 361 | /*----------------------------------------------------------------------- | |
| 362 | * Cache Configuration | |
| 363 | */ | |
| 364 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ | |
| fe7f782d | 365 | #if defined(CONFIG_CMD_KGDB) |
| 0f8c9768 WD |
366 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 367 | #endif | |
| 368 | ||
| 369 | /*----------------------------------------------------------------------- | |
| 370 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
| 371 | *----------------------------------------------------------------------- | |
| 372 | * HID0 also contains cache control - initially enable both caches and | |
| 373 | * invalidate contents, then the final state leaves only the instruction | |
| 374 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
| 375 | * but Soft reset does not. | |
| 376 | * | |
| 377 | * HID1 has only read-only information - nothing to set. | |
| 378 | */ | |
| 379 | #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ | |
| 8bde7f77 | 380 | HID0_IFEM|HID0_ABE) |
| 0f8c9768 WD |
381 | #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) |
| 382 | #define CFG_HID2 0 | |
| 383 | ||
| 384 | /*----------------------------------------------------------------------- | |
| 385 | * RMR - Reset Mode Register 5-5 | |
| 386 | *----------------------------------------------------------------------- | |
| 387 | * turn on Checkstop Reset Enable | |
| 388 | */ | |
| 389 | #define CFG_RMR RMR_CSRE | |
| 390 | ||
| 391 | /*----------------------------------------------------------------------- | |
| 392 | * BCR - Bus Configuration 4-25 | |
| 393 | *----------------------------------------------------------------------- | |
| 394 | */ | |
| 395 | #ifdef CONFIG_BUSMODE_60x | |
| 396 | #define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ | |
| 397 | BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ | |
| 398 | #else | |
| 399 | #define BCR_APD01 0x10000000 | |
| 400 | #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ | |
| 401 | #endif | |
| 402 | ||
| 403 | /*----------------------------------------------------------------------- | |
| 404 | * SIUMCR - SIU Module Configuration 4-31 | |
| 405 | *----------------------------------------------------------------------- | |
| 406 | */ | |
| 407 | #if 0 | |
| 408 | #define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) | |
| 409 | #else | |
| 410 | #define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) | |
| 411 | #endif | |
| 412 | ||
| 413 | ||
| 414 | /*----------------------------------------------------------------------- | |
| 415 | * SYPCR - System Protection Control 4-35 | |
| 416 | * SYPCR can only be written once after reset! | |
| 417 | *----------------------------------------------------------------------- | |
| 418 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
| 419 | */ | |
| 420 | #if defined(CONFIG_WATCHDOG) | |
| 421 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
| 8bde7f77 | 422 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
| 0f8c9768 WD |
423 | #else |
| 424 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
| 8bde7f77 | 425 | SYPCR_SWRI|SYPCR_SWP) |
| 0f8c9768 WD |
426 | #endif /* CONFIG_WATCHDOG */ |
| 427 | ||
| 428 | /*----------------------------------------------------------------------- | |
| 429 | * TMCNTSC - Time Counter Status and Control 4-40 | |
| 430 | *----------------------------------------------------------------------- | |
| 431 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
| 432 | * and enable Time Counter | |
| 433 | */ | |
| 434 | #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
| 435 | ||
| 436 | /*----------------------------------------------------------------------- | |
| 437 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
| 438 | *----------------------------------------------------------------------- | |
| 439 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
| 440 | * Periodic timer | |
| 441 | */ | |
| 442 | #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
| 443 | ||
| 444 | /*----------------------------------------------------------------------- | |
| 445 | * SCCR - System Clock Control 9-8 | |
| 446 | *----------------------------------------------------------------------- | |
| 447 | * Ensure DFBRG is Divide by 16 | |
| 448 | */ | |
| 449 | #define CFG_SCCR 0 | |
| 450 | ||
| 451 | /*----------------------------------------------------------------------- | |
| 452 | * RCCR - RISC Controller Configuration 13-7 | |
| 453 | *----------------------------------------------------------------------- | |
| 454 | */ | |
| 455 | #define CFG_RCCR 0 | |
| 456 | ||
| 457 | /* | |
| 458 | * Init Memory Controller: | |
| 459 | * | |
| 460 | * Bank Bus Machine PortSz Device | |
| 461 | * ---- --- ------- ------ ------ | |
| 462 | * 0 60x GPCM 64 bit FLASH | |
| 463 | * 1 60x SDRAM 64 bit SDRAM | |
| 464 | * 2 Local SDRAM 32 bit SDRAM | |
| 465 | * | |
| 466 | */ | |
| 467 | ||
| 468 | /* Initialize SDRAM on local bus | |
| 469 | */ | |
| 470 | #define CFG_INIT_LOCAL_SDRAM | |
| 471 | ||
| 472 | #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
| 473 | ||
| 474 | /* Minimum mask to separate preliminary | |
| 475 | * address ranges for CS[0:2] | |
| 476 | */ | |
| 477 | #define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ | |
| 478 | #define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ | |
| 479 | ||
| 480 | #define CFG_MPTPR 0x4000 | |
| 481 | ||
| 482 | /*----------------------------------------------------------------------------- | |
| 483 | * Address for Mode Register Set (MRS) command | |
| 484 | *----------------------------------------------------------------------------- | |
| 485 | * In fact, the address is rather configuration data presented to the SDRAM on | |
| 486 | * its address lines. Because the address lines may be mux'ed externally either | |
| 487 | * for 8 column or 9 column devices, some bits appear twice in the 8260's | |
| 488 | * address: | |
| 489 | * | |
| 490 | * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | | |
| 491 | * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | | |
| 492 | * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | | |
| 493 | * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | | |
| 494 | * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | | |
| 495 | *----------------------------------------------------------------------------- | |
| 496 | */ | |
| 497 | #define CFG_MRS_OFFS 0x00000110 | |
| 498 | ||
| 499 | ||
| 500 | /* Bank 0 - FLASH | |
| 501 | */ | |
| 502 | #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ | |
| 8bde7f77 WD |
503 | BRx_PS_64 |\ |
| 504 | BRx_MS_GPCM_P |\ | |
| 505 | BRx_V) | |
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506 | |
| 507 | #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ | |
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508 | ORxG_CSNT |\ |
| 509 | ORxG_ACS_DIV1 |\ | |
| 510 | ORxG_SCY_3_CLK |\ | |
| 511 | ORxG_EHTR |\ | |
| 512 | ORxG_TRLX) | |
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513 | |
| 514 | /* SDRAM on TQM8260 can have either 8 or 9 columns. | |
| 515 | * The number affects configuration values. | |
| 516 | */ | |
| 517 | ||
| 518 | /* Bank 1 - 60x bus SDRAM | |
| 519 | */ | |
| 520 | #define CFG_PSRT 0x20 | |
| 521 | #define CFG_LSRT 0x20 | |
| 522 | #ifndef CFG_RAMBOOT | |
| 523 | #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ | |
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524 | BRx_PS_64 |\ |
| 525 | BRx_MS_SDRAM_P |\ | |
| 526 | BRx_V) | |
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527 | |
| 528 | #define CFG_OR1_PRELIM CFG_OR1_8COL | |
| 529 | ||
| 530 | ||
| 531 | /* SDRAM initialization values for 8-column chips | |
| 532 | */ | |
| 533 | #define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ | |
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534 | ORxS_BPD_4 |\ |
| 535 | ORxS_ROWST_PBI1_A7 |\ | |
| 536 | ORxS_NUMR_12) | |
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537 | |
| 538 | #define CFG_PSDMR_8COL (PSDMR_PBI |\ | |
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539 | PSDMR_SDAM_A15_IS_A5 |\ |
| 540 | PSDMR_BSMA_A12_A14 |\ | |
| 541 | PSDMR_SDA10_PBI1_A8 |\ | |
| 542 | PSDMR_RFRC_7_CLK |\ | |
| 543 | PSDMR_PRETOACT_2W |\ | |
| 544 | PSDMR_ACTTORW_2W |\ | |
| 545 | PSDMR_LDOTOPRE_1C |\ | |
| 546 | PSDMR_WRC_2C |\ | |
| 547 | PSDMR_EAMUX |\ | |
| 548 | PSDMR_CL_2) | |
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549 | |
| 550 | /* SDRAM initialization values for 9-column chips | |
| 551 | */ | |
| 552 | #define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ | |
| 8bde7f77 WD |
553 | ORxS_BPD_4 |\ |
| 554 | ORxS_ROWST_PBI1_A5 |\ | |
| 555 | ORxS_NUMR_13) | |
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556 | |
| 557 | #define CFG_PSDMR_9COL (PSDMR_PBI |\ | |
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558 | PSDMR_SDAM_A16_IS_A5 |\ |
| 559 | PSDMR_BSMA_A12_A14 |\ | |
| 560 | PSDMR_SDA10_PBI1_A7 |\ | |
| 561 | PSDMR_RFRC_7_CLK |\ | |
| 562 | PSDMR_PRETOACT_2W |\ | |
| 563 | PSDMR_ACTTORW_2W |\ | |
| 564 | PSDMR_LDOTOPRE_1C |\ | |
| 565 | PSDMR_WRC_2C |\ | |
| 566 | PSDMR_EAMUX |\ | |
| 567 | PSDMR_CL_2) | |
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568 | |
| 569 | /* Bank 2 - Local bus SDRAM | |
| 570 | */ | |
| 571 | #ifdef CFG_INIT_LOCAL_SDRAM | |
| 572 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ | |
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573 | BRx_PS_32 |\ |
| 574 | BRx_MS_SDRAM_L |\ | |
| 575 | BRx_V) | |
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576 | |
| 577 | #define CFG_OR2_PRELIM CFG_OR2_8COL | |
| 578 | ||
| 579 | #define SDRAM_BASE2_PRELIM 0x80000000 | |
| 580 | ||
| 581 | /* SDRAM initialization values for 8-column chips | |
| 582 | */ | |
| 583 | #define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ | |
| 8bde7f77 WD |
584 | ORxS_BPD_4 |\ |
| 585 | ORxS_ROWST_PBI1_A8 |\ | |
| 586 | ORxS_NUMR_12) | |
| 0f8c9768 WD |
587 | |
| 588 | #define CFG_LSDMR_8COL (PSDMR_PBI |\ | |
| 8bde7f77 WD |
589 | PSDMR_SDAM_A15_IS_A5 |\ |
| 590 | PSDMR_BSMA_A13_A15 |\ | |
| 591 | PSDMR_SDA10_PBI1_A9 |\ | |
| 592 | PSDMR_RFRC_7_CLK |\ | |
| 593 | PSDMR_PRETOACT_2W |\ | |
| 594 | PSDMR_ACTTORW_2W |\ | |
| 595 | PSDMR_BL |\ | |
| 596 | PSDMR_LDOTOPRE_1C |\ | |
| 597 | PSDMR_WRC_2C |\ | |
| 598 | PSDMR_CL_2) | |
| 0f8c9768 WD |
599 | |
| 600 | /* SDRAM initialization values for 9-column chips | |
| 601 | */ | |
| 602 | #define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ | |
| 8bde7f77 WD |
603 | ORxS_BPD_4 |\ |
| 604 | ORxS_ROWST_PBI1_A6 |\ | |
| 605 | ORxS_NUMR_13) | |
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606 | |
| 607 | #define CFG_LSDMR_9COL (PSDMR_PBI |\ | |
| 8bde7f77 WD |
608 | PSDMR_SDAM_A16_IS_A5 |\ |
| 609 | PSDMR_BSMA_A13_A15 |\ | |
| 610 | PSDMR_SDA10_PBI1_A8 |\ | |
| 611 | PSDMR_RFRC_7_CLK |\ | |
| 612 | PSDMR_PRETOACT_2W |\ | |
| 613 | PSDMR_ACTTORW_2W |\ | |
| 614 | PSDMR_BL |\ | |
| 615 | PSDMR_LDOTOPRE_1C |\ | |
| 616 | PSDMR_WRC_2C |\ | |
| 617 | PSDMR_CL_2) | |
| 0f8c9768 WD |
618 | |
| 619 | #endif /* CFG_INIT_LOCAL_SDRAM */ | |
| 620 | ||
| 621 | #endif /* CFG_RAMBOOT */ | |
| 622 | ||
| 623 | #define CFG_CAN0_BASE 0xc0000000 | |
| 624 | #define CFG_CAN1_BASE 0xc0008000 | |
| 625 | #define CFG_FIOX_BASE 0xc0010000 | |
| 626 | #define CFG_FDOHM_BASE 0xc0018000 | |
| 627 | #define CFG_EXTPROM_BASE 0xc2000000 | |
| 628 | ||
| 629 | #define CFG_CAN_SIZE 0x00000100 | |
| 630 | #define CFG_FIOX_SIZE 0x00000020 | |
| 631 | #define CFG_FDOHM_SIZE 0x00002000 | |
| 632 | #define CFG_EXTPROM_BANK_SIZE 0x01000000 | |
| 633 | ||
| 634 | #define EXT_EEPROM_MAX_FLASH_BANKS 0x02 | |
| 635 | ||
| 636 | /* CS3 - CAN 0 | |
| 637 | */ | |
| 638 | #define CFG_CAN0_BR3 ((CFG_CAN0_BASE & BRx_BA_MSK) |\ | |
| 639 | BRx_PS_8 |\ | |
| 640 | BRx_MS_UPMA |\ | |
| 641 | BRx_V) | |
| 642 | ||
| 643 | #define CFG_CAN0_OR3 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ | |
| 644 | ORxU_BI |\ | |
| 645 | ORxU_EHTR_4IDLE) | |
| 646 | ||
| 647 | /* CS4 - CAN 1 | |
| 648 | */ | |
| 649 | #define CFG_CAN1_BR4 ((CFG_CAN1_BASE & BRx_BA_MSK) |\ | |
| 650 | BRx_PS_8 |\ | |
| 651 | BRx_MS_UPMA |\ | |
| 652 | BRx_V) | |
| 653 | ||
| 654 | #define CFG_CAN1_OR4 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ | |
| 655 | ORxU_BI |\ | |
| 656 | ORxU_EHTR_4IDLE) | |
| 657 | ||
| 658 | /* CS5 - Extended PROM (16MB optional) | |
| 659 | */ | |
| 660 | #define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\ | |
| 661 | BRx_PS_32 |\ | |
| 662 | BRx_MS_GPCM_P |\ | |
| 663 | BRx_V) | |
| 664 | ||
| 665 | #define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ | |
| 666 | ORxG_CSNT |\ | |
| 667 | ORxG_ACS_DIV4 |\ | |
| 668 | ORxG_SCY_5_CLK |\ | |
| 669 | ORxG_TRLX) | |
| 670 | ||
| 671 | /* CS6 - Extended PROM (16MB optional) | |
| 672 | */ | |
| 673 | #define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \ | |
| 674 | CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\ | |
| 675 | BRx_PS_32 |\ | |
| 676 | BRx_MS_GPCM_P |\ | |
| 677 | BRx_V) | |
| 678 | ||
| 679 | #define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ | |
| 680 | ORxG_CSNT |\ | |
| 681 | ORxG_ACS_DIV4 |\ | |
| 682 | ORxG_SCY_5_CLK |\ | |
| 683 | ORxG_TRLX) | |
| 684 | ||
| 685 | /* CS7 - FPGA FIOX: Glue Logic | |
| 686 | */ | |
| 687 | #define CFG_FIOX_BR7 ((CFG_FIOX_BASE & BRx_BA_MSK) |\ | |
| 688 | BRx_PS_32 |\ | |
| 689 | BRx_MS_GPCM_P |\ | |
| 690 | BRx_V) | |
| 691 | ||
| 692 | #define CFG_FIOX_OR7 (P2SZ_TO_AM(CFG_FIOX_SIZE) |\ | |
| 693 | ORxG_ACS_DIV4 |\ | |
| 694 | ORxG_SCY_5_CLK |\ | |
| 695 | ORxG_TRLX) | |
| 696 | ||
| 697 | /* CS8 - FPGA DOH Master | |
| 698 | */ | |
| 699 | #define CFG_FDOHM_BR8 ((CFG_FDOHM_BASE & BRx_BA_MSK) |\ | |
| 700 | BRx_PS_16 |\ | |
| 701 | BRx_MS_GPCM_P |\ | |
| 702 | BRx_V) | |
| 703 | ||
| 704 | #define CFG_FDOHM_OR8 (P2SZ_TO_AM(CFG_FDOHM_SIZE) |\ | |
| 705 | ORxG_ACS_DIV4 |\ | |
| 706 | ORxG_SCY_5_CLK |\ | |
| 707 | ORxG_TRLX) | |
| 708 | ||
| 709 | ||
| 710 | /* FPGA configuration */ | |
| 711 | #define CFG_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */ | |
| 712 | #define CFG_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */ | |
| 713 | #define CFG_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */ | |
| 714 | ||
| 715 | #define CFG_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */ | |
| 716 | #define CFG_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */ | |
| 717 | #define CFG_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */ | |
| 718 | ||
| 719 | ||
| 720 | #endif /* __CONFIG_H */ |