[people/ms/u-boot.git] / include / configs / SIMPC8313.h

/*
 * Copyright (C) Sheldon Instruments, Inc. 2008
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
/*
 * simpc8313 board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_NAND_U_BOOT

#define CONFIG_E300			1
#define CONFIG_MPC83xx			1
#define CONFIG_MPC831x			1
#define CONFIG_MPC8313			1

#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START	0x00100100
#define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)

#define CONFIG_SYS_TEXT_BASE	0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000

#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_ELBC			1

#define CONFIG_MISC_INIT_R

/*
 * On-board devices
 *
 * TSEC1 is Marvell PHY 88E1118
 */

#define CONFIG_SYS_33MHZ

#define CONFIG_83XX_CLKIN		33333333	/* in Hz */

#define CONFIG_SYS_CLK_FREQ		CONFIG_83XX_CLKIN

#define CONFIG_SYS_IMMR			0xE0000000

#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DEFAULT_IMMR		CONFIG_SYS_IMMR
#endif

#define CONFIG_SYS_MEMTEST_START	0x00001000
#define CONFIG_SYS_MEMTEST_END		0x07f00000

#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */

/*
 * Device configurations
 */
#define CONFIG_TSEC1

/*
 * DDR Setup
 */
					/* DDR is system memory*/
#define CONFIG_SYS_DDR_BASE		0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE

#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED		(512 << 20)

#define CONFIG_SYS_DDRCDR		(DDRCDR_EN \
					| DDRCDR_PZ_NOMZ \
					| DDRCDR_NZ_NOMZ \
					| DDRCDR_M_ODR)
					/* 0x73000002 TODO ODR & DRN ? */

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_NO_FLASH

#if !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */

/*
 * Local Bus LCRR and LBCR regs
 */
#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
				| (0xFF << LBCR_BMT_SHIFT) \
				| 0xF)	/* 0x0004ff0f */

				/* LB refresh timer prescal, 266MHz/32 */
#define CONFIG_SYS_LBC_MRTPR	0x20000000

/* drivers/mtd/nand/nand.c */
#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE		0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE		0xE2800000
#endif
#define CONFIG_SYS_FPGA_BASE		0xFF000000

#define CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_NAND_FSL_ELBC		1

#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
				| BR_PS_8		/* 8 bit Port */ \
				| BR_MS_FCM		/* MSEL = FCM */ \
				| BR_V)			/* valid */

#ifdef CONFIG_NAND_SP
#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
					| OR_FCM_CSCT \
					| OR_FCM_CST \
					| OR_FCM_CHT \
					| OR_FCM_SCY_1 \
					| OR_FCM_TRLX \
					| OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
#define CONFIG_SYS_NAND_PAGE_SIZE	512	/* NAND chip page size */
					/* NAND chip block size */
#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)
#define NAND_CACHE_PAGES		32
#elif defined(CONFIG_NAND_LP)
#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_256KB \
					| OR_FCM_PGS \
					| OR_FCM_CSCT \
					| OR_FCM_CST \
					| OR_FCM_CHT \
					| OR_FCM_SCY_1 \
					| OR_FCM_TRLX \
					| OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_256KB)
#define CONFIG_SYS_NAND_PAGE_SIZE	2048	/* NAND chip page size */
					/* NAND chip block size */
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
#define NAND_CACHE_PAGES		64
#else
#error Page size of NAND not defined.
#endif /* CONFIG_NAND_SP */

#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SYS_NAND_BLOCK_SIZE

#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_NAND_OR_PRELIM

#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM	CONFIG_SYS_LBLAWBAR0_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM	CONFIG_SYS_LBLAWAR0_PRELIM

#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_FPGA_BASE \
					| BR_PS_16 \
					| BR_MS_UPMA \
					| BR_V)
#define CONFIG_SYS_OR1_PRELIM		(OR_AM_2MB \
					| OR_UPM_BCTLD)

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_FPGA_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_2MB)

/*
 * JFFS2 configuration
 */
#define CONFIG_JFFS2_NAND
#define CONFIG_JFFS2_DEV	"nand0"

/* mtdparts command line support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define MTDIDS_DEFAULT		"nand0=nand0"
#define MTDPARTS_DEFAULT	"mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#ifdef CONFIG_NAND_SPL
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif

#define CONFIG_SYS_BAUDRATE_TABLE	\
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */

#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1057	/* Motorola */

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET		/* TSEC ethernet support */

#define CONFIG_GMII			/* MII PHY management */

#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME		"TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET		0x24000
#define TSEC1_PHY_ADDR			0x0
#define TSEC1_FLAGS			TSEC_GIGABIT
#define TSEC1_PHYIDX			0
#endif

#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME		"TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET		0x25000
#define TSEC2_PHY_ADDR			4
#define TSEC2_FLAGS			TSEC_GIGABIT
#define TSEC2_PHYIDX			0
#endif


/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME			"TSEC1"

/*
 * Configure on-board RTC
 */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR		0x68

/*
 * Environment
 */
#if defined(CONFIG_NAND_U_BOOT)
	#define CONFIG_ENV_IS_IN_NAND	1
	#define CONFIG_ENV_OFFSET	(768 * 1024)
	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
	#define CONFIG_ENV_RANGE	(CONFIG_ENV_SECT_SIZE * 4)
	#define CONFIG_ENV_OFFSET_REDUND	\
					(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#elif !defined(CONFIG_SYS_RAMBOOT)
	#define CONFIG_ENV_IS_IN_FLASH	1
	#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
	#define CONFIG_ENV_SIZE		0x2000

/* Address and size of Redundant Environment Sector */
#else
	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO		1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1 /* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FLASH

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_JFFS2

#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
	#undef CONFIG_CMD_SAVEENV
	#undef CONFIG_CMD_LOADS
#endif

#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */

#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE		\
				+ sizeof(CONFIG_SYS_PROMPT)	\
				+ 16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
				/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)

#define CONFIG_SYS_RCWH_PCIHOST	0x80000000	/* PCIHOST */

#define CONFIG_SYS_HRCW_LOW	(HRCWL_LCL_BUS_TO_SCB_CLK_1X1	\
				| 0x20000000 /* reserved */	\
				| HRCWL_DDR_TO_SCB_CLK_2X1	\
				| HRCWL_CSB_TO_CLKIN_4X1	\
				| HRCWL_CORE_TO_CSB_2_5X1)

#define CONFIG_SYS_NS16550_CLK	(CONFIG_83XX_CLKIN * 4)

#define CONFIG_SYS_HRCW_HIGH_BASE	(HRCWH_PCI_HOST	\
				| HRCWH_PCI1_ARBITER_ENABLE	\
				| HRCWH_CORE_ENABLE		\
				| HRCWH_BOOTSEQ_DISABLE		\
				| HRCWH_SW_WATCHDOG_DISABLE	\
				| HRCWH_TSEC1M_IN_RGMII		\
				| HRCWH_TSEC2M_IN_RGMII		\
				| HRCWH_BIG_ENDIAN		\
				| HRCWH_LALE_NORMAL)

#ifdef CONFIG_NAND_LP
#define CONFIG_SYS_HRCW_HIGH	(CONFIG_SYS_HRCW_HIGH_BASE	\
				| HRCWH_FROM_0XFFF00100		\
				| HRCWH_ROM_LOC_NAND_LP_8BIT	\
				| HRCWH_RL_EXT_NAND)
#else
#define CONFIG_SYS_HRCW_HIGH	(CONFIG_SYS_HRCW_HIGH_BASE	\
				| HRCWH_FROM_0XFFF00100		\
				| HRCWH_ROM_LOC_NAND_SP_8BIT	\
				| HRCWH_RL_EXT_NAND)
#endif

/* System IO Config */
#define CONFIG_SYS_SICRH	(SICRH_ETSEC2_B	\
				| SICRH_ETSEC2_C	\
				| SICRH_ETSEC2_D	\
				| SICRH_ETSEC2_E	\
				| SICRH_ETSEC2_F	\
				| SICRH_ETSEC2_G	\
				| SICRH_TSOBI1		\
				| SICRH_TSOBI2)
#define CONFIG_SYS_SICRL	(SICRL_LBC		\
				| SICRL_USBDR_10	\
				| SICRL_ETSEC2_A)

#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
				| HID0_ENABLE_INSTRUCTION_CACHE \
				| HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)

#define CONFIG_SYS_HID2		HID2_HBE

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT1L	((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
				| BATL_PP_RW)
#define CONFIG_SYS_IBAT1U	((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* PCI @ 0x80000000 */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* PCI2 not supported on 8313 */
#define CONFIG_SYS_IBAT4L	(0)
#define CONFIG_SYS_IBAT4U	(0)

/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L	(0xF0000000 \
				| BATL_PP_RW \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(0xF0000000 \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_NETDEV		"eth1"

#define CONFIG_HOSTNAME		simpc8313
#define CONFIG_ROOTPATH		"/tftpboot/"
#define CONFIG_BOOTFILE		"/tftpboot/uImage"
				/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH	"u-boot-nand.bin"
#define CONFIG_FDTFILE		"simpc8313.dtb"

				/* default location for tftp and bootm */
#define CONFIG_LOADADDR		500000
#define CONFIG_BOOTDELAY	5	/* 5 second delay */
#define CONFIG_BAUDRATE		115200

#define CONFIG_BOOTCOMMAND	"nand read $loadaddr kernel 600000;" \
					"bootm $loadaddr - $fdtaddr"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" CONFIG_NETDEV "\0"					\
	"ethprime=TSEC1\0"						\
	"uboot=" CONFIG_UBOOTPATH "\0"					\
	"tftpflash=tftpboot $loadaddr $uboot; "				\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" +$filesize; "	\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize; "	\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize\0"	\
	"fdtaddr=ae0000\0"						\
	"fdtfile=" CONFIG_FDTFILE "\0"					\
	"console=ttyS0\0"						\
	"setbootargs=setenv bootargs "					\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
	"load_uboot=tftp 100000 u-boot-nand.bin\0"			\
	"burn_uboot=nand erase u-boot 80000; "				\
		"nand write 100000 u-boot $filesize\0"			\
	"update_uboot=run load_uboot;run burn_uboot\0"			\
	"mtdids=nand0=nand0\0"						\
	"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "		\
		"console=ttyS0,115200\0"				\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv rootdev /dev/nfs;"					\
	"run setbootargs;"						\
	"run setipargs;"						\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv rootdev /dev/ram;"					\
	"run setbootargs;"						\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#endif	/* __CONFIG_H */
Commit	Line	Data
5bb907a4 RM	1	/*
	2	* Copyright (C) Sheldon Instruments, Inc. 2008
	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
5bb907a4 RM	5	*/
	6	/*
	7	* simpc8313 board configuration file
	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/*
	14	* High Level Configuration Options
	15	*/
	16	#define CONFIG_NAND_U_BOOT
	17
	18	#define CONFIG_E300 1
0f898604	19	#define CONFIG_MPC83xx 1
2c7920af	20	#define CONFIG_MPC831x 1
5bb907a4 RM	21	#define CONFIG_MPC8313 1
5bb907a4 RM	22
f1c574d4 SW	23	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
	24	#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
	25	#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
	26	#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
	27	#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
	28
	29	#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
	30	#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
	31
	32	#ifdef CONFIG_NAND_SPL
	33	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
	34	#else
	35	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
2ae18241 WD	36	#endif
2ae18241 WD	37
5bb907a4	38	#define CONFIG_PCI
842033e6	39	#define CONFIG_PCI_INDIRECT_BRIDGE
0914f483	40	#define CONFIG_FSL_ELBC 1
5bb907a4 RM	41
	42	#define CONFIG_MISC_INIT_R
	43
	44	/*
	45	* On-board devices
	46	*
	47	* TSEC1 is Marvell PHY 88E1118
	48	*/
	49
	50	#define CONFIG_SYS_33MHZ
	51
	52	#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
	53
	54	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	55
	56	#define CONFIG_SYS_IMMR 0xE0000000
	57
	58	#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
	59	#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
	60	#endif
	61
	62	#define CONFIG_SYS_MEMTEST_START 0x00001000
	63	#define CONFIG_SYS_MEMTEST_END 0x07f00000
	64
bb0f5bc9 JH	65	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
bb0f5bc9 JH	66	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
5bb907a4 RM	67
	68	/*
	69	* Device configurations
	70	*/
	71	#define CONFIG_TSEC1
	72
	73	/*
	74	* DDR Setup
	75	*/
bb0f5bc9 JH	76	/* DDR is system memory*/
bb0f5bc9 JH	77	#define CONFIG_SYS_DDR_BASE 0x00000000
5bb907a4 RM	78	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	79	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	80
	81	#define CONFIG_VERY_BIG_RAM
	82	#define CONFIG_MAX_MEM_MAPPED (512 << 20)
	83
bb0f5bc9	84	#define CONFIG_SYS_DDRCDR (DDRCDR_EN \
5bb907a4 RM	85	\| DDRCDR_PZ_NOMZ \
5bb907a4 RM	86	\| DDRCDR_NZ_NOMZ \
bb0f5bc9	87	\| DDRCDR_M_ODR)
5bb907a4 RM	88	/* 0x73000002 TODO ODR & DRN ? */
	89
	90	/*
	91	* FLASH on the Local Bus
	92	*/
	93	#define CONFIG_SYS_NO_FLASH
	94
5bb907a4 RM	95	#if !defined(CONFIG_NAND_SPL)
	96	#define CONFIG_SYS_RAMBOOT
	97	#endif
	98
	99	#define CONFIG_SYS_INIT_RAM_LOCK 1
bb0f5bc9 JH	100	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
bb0f5bc9 JH	101	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
5bb907a4	102
bb0f5bc9 JH	103	#define CONFIG_SYS_GBL_DATA_OFFSET \
bb0f5bc9 JH	104	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
5bb907a4 RM	105	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	106
	107	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
bb0f5bc9 JH	108	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
bb0f5bc9 JH	109	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
5bb907a4 RM	110
	111	/*
	112	* Local Bus LCRR and LBCR regs
	113	*/
c7190f02 KP	114	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
	115	#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
	116	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
5bb907a4 RM	117	#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
5bb907a4 RM	118	\| (0xFF << LBCR_BMT_SHIFT) \
bb0f5bc9	119	\| 0xF) /* 0x0004ff0f */
5bb907a4	120
bb0f5bc9 JH	121	/* LB refresh timer prescal, 266MHz/32 */
bb0f5bc9 JH	122	#define CONFIG_SYS_LBC_MRTPR 0x20000000
5bb907a4 RM	123
	124	/* drivers/mtd/nand/nand.c */
	125	#ifdef CONFIG_NAND_SPL
	126	#define CONFIG_SYS_NAND_BASE 0xFFF00000
	127	#else
	128	#define CONFIG_SYS_NAND_BASE 0xE2800000
	129	#endif
3b439792	130	#define CONFIG_SYS_FPGA_BASE 0xFF000000
5bb907a4	131
6bbb3e93	132	#define CONFIG_CMD_NAND
5bb907a4	133	#define CONFIG_SYS_MAX_NAND_DEVICE 1
5bb907a4	134	#define CONFIG_MTD_NAND_VERIFY_WRITE
5bb907a4 RM	135	#define CONFIG_NAND_FSL_ELBC 1
5bb907a4 RM	136
bb0f5bc9	137	#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
7d6a0982	138	\| BR_DECC_CHK_GEN /* Use HW ECC */ \
bb0f5bc9 JH	139	\| BR_PS_8 /* 8 bit Port */ \
	140	\| BR_MS_FCM /* MSEL = FCM */ \
	141	\| BR_V) /* valid */
5bb907a4 RM	142
5bb907a4 RM	143	#ifdef CONFIG_NAND_SP
7d6a0982	144	#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
5bb907a4 RM	145	\| OR_FCM_CSCT \
	146	\| OR_FCM_CST \
	147	\| OR_FCM_CHT \
	148	\| OR_FCM_SCY_1 \
	149	\| OR_FCM_TRLX \
bb0f5bc9	150	\| OR_FCM_EHTR)
7d6a0982 JH	151	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
7d6a0982 JH	152	#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
bb0f5bc9 JH	153	/* NAND chip block size */
bb0f5bc9 JH	154	#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10)
5bb907a4 RM	155	#define NAND_CACHE_PAGES 32
5bb907a4 RM	156	#elif defined(CONFIG_NAND_LP)
7d6a0982	157	#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
5bb907a4 RM	158	\| OR_FCM_PGS \
	159	\| OR_FCM_CSCT \
	160	\| OR_FCM_CST \
	161	\| OR_FCM_CHT \
	162	\| OR_FCM_SCY_1 \
	163	\| OR_FCM_TRLX \
bb0f5bc9	164	\| OR_FCM_EHTR)
7d6a0982 JH	165	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_256KB)
7d6a0982 JH	166	#define CONFIG_SYS_NAND_PAGE_SIZE 2048 /* NAND chip page size */
bb0f5bc9 JH	167	/* NAND chip block size */
bb0f5bc9 JH	168	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
5bb907a4 RM	169	#define NAND_CACHE_PAGES 64
	170	#else
	171	#error Page size of NAND not defined.
	172	#endif /* CONFIG_NAND_SP */
	173
	174	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
	175
	176	#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
	177	#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
	178
	179	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
	180
	181	#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
	182	#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
	183
bb0f5bc9	184	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA_BASE \
3b439792 RM	185	\| BR_PS_16 \
3b439792 RM	186	\| BR_MS_UPMA \
bb0f5bc9 JH	187	\| BR_V)
bb0f5bc9 JH	188	#define CONFIG_SYS_OR1_PRELIM (OR_AM_2MB \
3b439792 RM	189	\| OR_UPM_BCTLD)
	190
	191	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
	192	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_2MB)
	193
5bb907a4 RM	194	/*
	195	* JFFS2 configuration
	196	*/
	197	#define CONFIG_JFFS2_NAND
	198	#define CONFIG_JFFS2_DEV "nand0"
	199
	200	/* mtdparts command line support */
68d7d651	201	#define CONFIG_CMD_MTDPARTS
bb0f5bc9	202	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
5bb907a4 RM	203	#define MTDIDS_DEFAULT "nand0=nand0"
	204	#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
	205
	206	/* pass open firmware flat tree */
	207	#define CONFIG_OF_LIBFDT 1
	208	#define CONFIG_OF_BOARD_SETUP 1
	209	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	210
	211	/*
	212	* Serial Port
	213	*/
	214	#define CONFIG_CONS_INDEX 1
	215	#define CONFIG_SYS_NS16550
	216	#define CONFIG_SYS_NS16550_SERIAL
	217	#define CONFIG_SYS_NS16550_REG_SIZE 1
f5675aa5 RM	218	#ifdef CONFIG_NAND_SPL
	219	#define CONFIG_NS16550_MIN_FUNCTIONS
	220	#endif
5bb907a4 RM	221
5bb907a4 RM	222	#define CONFIG_SYS_BAUDRATE_TABLE \
bb0f5bc9	223	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
5bb907a4 RM	224
	225	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
	226	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
	227
	228	/* Use the HUSH parser */
	229	#define CONFIG_SYS_HUSH_PARSER
5bb907a4 RM	230
5bb907a4 RM	231	/* I2C */
00f792e0 HS	232	#define CONFIG_SYS_I2C
	233	#define CONFIG_SYS_I2C_FSL
	234	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	235	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	236	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	237	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	238	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	239	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	240	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
5bb907a4 RM	241
	242	/*
	243	* General PCI
	244	* Addresses are mapped 1-1.
	245	*/
	246	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	247	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	248	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	249	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	250	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	251	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	252	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	253	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	254	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
	255
	256	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	257	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
	258
	259	/*
	260	* TSEC
	261	*/
	262	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
	263
5bb907a4 RM	264	#define CONFIG_GMII /* MII PHY management */
	265
	266	#ifdef CONFIG_TSEC1
	267	#define CONFIG_HAS_ETH0
	268	#define CONFIG_TSEC1_NAME "TSEC0"
	269	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	270	#define TSEC1_PHY_ADDR 0x0
	271	#define TSEC1_FLAGS TSEC_GIGABIT
	272	#define TSEC1_PHYIDX 0
	273	#endif
	274
	275	#ifdef CONFIG_TSEC2
	276	#define CONFIG_HAS_ETH1
	277	#define CONFIG_TSEC2_NAME "TSEC1"
	278	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	279	#define TSEC2_PHY_ADDR 4
	280	#define TSEC2_FLAGS TSEC_GIGABIT
	281	#define TSEC2_PHYIDX 0
	282	#endif
	283
	284
	285	/* Options are: TSEC[0-1] */
	286	#define CONFIG_ETHPRIME "TSEC1"
	287
	288	/*
	289	* Configure on-board RTC
	290	*/
	291	#define CONFIG_RTC_DS1337
	292	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	293
	294	/*
	295	* Environment
	296	*/
	297	#if defined(CONFIG_NAND_U_BOOT)
bb0f5bc9 JH	298	#define CONFIG_ENV_IS_IN_NAND 1
	299	#define CONFIG_ENV_OFFSET (768 * 1024)
	300	#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
	301	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	302	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	303	#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
	304	#define CONFIG_ENV_OFFSET_REDUND \
	305	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
5bb907a4	306	#elif !defined(CONFIG_SYS_RAMBOOT)
bb0f5bc9 JH	307	#define CONFIG_ENV_IS_IN_FLASH 1
	308	#define CONFIG_ENV_ADDR \
	309	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	310	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
	311	#define CONFIG_ENV_SIZE 0x2000
5bb907a4 RM	312
	313	/* Address and size of Redundant Environment Sector */
	314	#else
bb0f5bc9 JH	315	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	316	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
	317	#define CONFIG_ENV_SIZE 0x2000
5bb907a4 RM	318	#endif
5bb907a4 RM	319
bb0f5bc9 JH	320	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
bb0f5bc9 JH	321	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
5bb907a4 RM	322
	323	/*
	324	* BOOTP options
	325	*/
	326	#define CONFIG_BOOTP_BOOTFILESIZE
	327	#define CONFIG_BOOTP_BOOTPATH
	328	#define CONFIG_BOOTP_GATEWAY
	329	#define CONFIG_BOOTP_HOSTNAME
	330
	331
	332	/*
	333	* Command line configuration.
	334	*/
	335	#include <config_cmd_default.h>
	336	#undef CONFIG_CMD_IMLS
	337	#undef CONFIG_CMD_FLASH
	338
	339	#define CONFIG_CMD_PING
	340	#define CONFIG_CMD_DHCP
	341	#define CONFIG_CMD_I2C
	342	#define CONFIG_CMD_MII
	343	#define CONFIG_CMD_DATE
	344	#define CONFIG_CMD_PCI
	345	#define CONFIG_CMD_JFFS2
	346
	347	#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
bdab39d3	348	#undef CONFIG_CMD_SAVEENV
5bb907a4 RM	349	#undef CONFIG_CMD_LOADS
	350	#endif
	351
bb0f5bc9 JH	352	#define CONFIG_CMDLINE_EDITING 1
bb0f5bc9 JH	353	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
5bb907a4 RM	354
	355	/*
	356	* Miscellaneous configurable options
	357	*/
bb0f5bc9 JH	358	#define CONFIG_SYS_LONGHELP /* undef to save memory */
bb0f5bc9 JH	359	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
bb0f5bc9 JH	360	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	361
	362	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
	363	+ sizeof(CONFIG_SYS_PROMPT) \
	364	+ 16) /* Print Buffer Size */
	365	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	366	/* Boot Argument Buffer Size */
	367	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
5bb907a4 RM	368
	369	/*
	370	* For booting Linux, the board info and command line data
9f530d59	371	* have to be in the first 256 MB of memory, since this is
5bb907a4 RM	372	* the maximum mapped by the Linux kernel during initialization.
5bb907a4 RM	373	*/
bb0f5bc9 JH	374	/* Initial Memory map for Linux*/
bb0f5bc9 JH	375	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
5bb907a4	376
bb0f5bc9	377	#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
5bb907a4	378
bb0f5bc9 JH	379	#define CONFIG_SYS_HRCW_LOW (HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
	380	\| 0x20000000 /* reserved */ \
	381	\| HRCWL_DDR_TO_SCB_CLK_2X1 \
	382	\| HRCWL_CSB_TO_CLKIN_4X1 \
	383	\| HRCWL_CORE_TO_CSB_2_5X1)
5bb907a4	384
bb0f5bc9	385	#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
5bb907a4	386
bb0f5bc9 JH	387	#define CONFIG_SYS_HRCW_HIGH_BASE (HRCWH_PCI_HOST \
	388	\| HRCWH_PCI1_ARBITER_ENABLE \
	389	\| HRCWH_CORE_ENABLE \
	390	\| HRCWH_BOOTSEQ_DISABLE \
	391	\| HRCWH_SW_WATCHDOG_DISABLE \
	392	\| HRCWH_TSEC1M_IN_RGMII \
	393	\| HRCWH_TSEC2M_IN_RGMII \
	394	\| HRCWH_BIG_ENDIAN \
	395	\| HRCWH_LALE_NORMAL)
5bb907a4 RM	396
5bb907a4 RM	397	#ifdef CONFIG_NAND_LP
bb0f5bc9 JH	398	#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
	399	\| HRCWH_FROM_0XFFF00100 \
	400	\| HRCWH_ROM_LOC_NAND_LP_8BIT \
5bb907a4 RM	401	\| HRCWH_RL_EXT_NAND)
5bb907a4 RM	402	#else
bb0f5bc9 JH	403	#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
	404	\| HRCWH_FROM_0XFFF00100 \
	405	\| HRCWH_ROM_LOC_NAND_SP_8BIT \
	406	\| HRCWH_RL_EXT_NAND)
5bb907a4 RM	407	#endif
	408
	409	/* System IO Config */
bb0f5bc9	410	#define CONFIG_SYS_SICRH (SICRH_ETSEC2_B \
5bb907a4 RM	411	\| SICRH_ETSEC2_C \
	412	\| SICRH_ETSEC2_D \
	413	\| SICRH_ETSEC2_E \
	414	\| SICRH_ETSEC2_F \
	415	\| SICRH_ETSEC2_G \
	416	\| SICRH_TSOBI1 \
bb0f5bc9 JH	417	\| SICRH_TSOBI2)
bb0f5bc9 JH	418	#define CONFIG_SYS_SICRL (SICRL_LBC \
f986325d	419	\| SICRL_USBDR_10 \
bb0f5bc9	420	\| SICRL_ETSEC2_A)
5bb907a4 RM	421
5bb907a4 RM	422	#define CONFIG_SYS_HID0_INIT 0x000000000
bb0f5bc9 JH	423	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
	424	\| HID0_ENABLE_INSTRUCTION_CACHE \
	425	\| HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
5bb907a4 RM	426
	427	#define CONFIG_SYS_HID2 HID2_HBE
	428
	429	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
	430
	431	/* DDR @ 0x00000000 */
72cd4087	432	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW)
bb0f5bc9 JH	433	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	434	\| BATU_BL_256M \
	435	\| BATU_VS \
	436	\| BATU_VP)
	437	#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
72cd4087	438	\| BATL_PP_RW)
bb0f5bc9 JH	439	#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
	440	\| BATU_BL_256M \
	441	\| BATU_VS \
	442	\| BATU_VP)
5bb907a4 RM	443
5bb907a4 RM	444	/* PCI @ 0x80000000 */
72cd4087	445	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE \| BATL_PP_RW)
bb0f5bc9 JH	446	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \
	447	\| BATU_BL_256M \
	448	\| BATU_VS \
	449	\| BATU_VP)
	450	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \
72cd4087	451	\| BATL_PP_RW \
bb0f5bc9 JH	452	\| BATL_CACHEINHIBIT \
	453	\| BATL_GUARDEDSTORAGE)
	454	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \
	455	\| BATU_BL_256M \
	456	\| BATU_VS \
	457	\| BATU_VP)
5bb907a4 RM	458
	459	/* PCI2 not supported on 8313 */
	460	#define CONFIG_SYS_IBAT4L (0)
	461	#define CONFIG_SYS_IBAT4U (0)
	462
	463	/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
bb0f5bc9	464	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
72cd4087	465	\| BATL_PP_RW \
bb0f5bc9 JH	466	\| BATL_CACHEINHIBIT \
	467	\| BATL_GUARDEDSTORAGE)
	468	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
	469	\| BATU_BL_256M \
	470	\| BATU_VS \
	471	\| BATU_VP)
5bb907a4 RM	472
5bb907a4 RM	473	/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
bb0f5bc9	474	#define CONFIG_SYS_IBAT6L (0xF0000000 \
72cd4087	475	\| BATL_PP_RW \
bb0f5bc9 JH	476	\| BATL_GUARDEDSTORAGE)
	477	#define CONFIG_SYS_IBAT6U (0xF0000000 \
	478	\| BATU_BL_256M \
	479	\| BATU_VS \
	480	\| BATU_VP)
5bb907a4 RM	481
	482	#define CONFIG_SYS_IBAT7L (0)
	483	#define CONFIG_SYS_IBAT7U (0)
	484
	485	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	486	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	487	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	488	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	489	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	490	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	491	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	492	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	493	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	494	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	495	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	496	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	497	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	498	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	499	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	500	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
	501
5bb907a4 RM	502	/*
	503	* Environment Configuration
	504	*/
	505	#define CONFIG_ENV_OVERWRITE
	506
bb0f5bc9	507	#define CONFIG_NETDEV "eth1"
5bb907a4 RM	508
5bb907a4 RM	509	#define CONFIG_HOSTNAME simpc8313
8b3637c6	510	#define CONFIG_ROOTPATH "/tftpboot/"
b3f44c21	511	#define CONFIG_BOOTFILE "/tftpboot/uImage"
bb0f5bc9 JH	512	/* U-Boot image on TFTP server */
	513	#define CONFIG_UBOOTPATH "u-boot-nand.bin"
	514	#define CONFIG_FDTFILE "simpc8313.dtb"
5bb907a4	515
bb0f5bc9 JH	516	/* default location for tftp and bootm */
bb0f5bc9 JH	517	#define CONFIG_LOADADDR 500000
5bb907a4 RM	518	#define CONFIG_BOOTDELAY 5 /* 5 second delay */
	519	#define CONFIG_BAUDRATE 115200
	520
bb0f5bc9 JH	521	#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;" \
bb0f5bc9 JH	522	"bootm $loadaddr - $fdtaddr"
5bb907a4	523
5bb907a4	524	#define CONFIG_EXTRA_ENV_SETTINGS \
bb0f5bc9	525	"netdev=" CONFIG_NETDEV "\0" \
5bb907a4	526	"ethprime=TSEC1\0" \
bb0f5bc9	527	"uboot=" CONFIG_UBOOTPATH "\0" \
5bb907a4	528	"tftpflash=tftpboot $loadaddr $uboot; " \
5368c55d MV	529	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	530	" +$filesize; " \
	531	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	532	" +$filesize; " \
	533	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	534	" $filesize; " \
	535	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	536	" +$filesize; " \
	537	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	538	" $filesize\0" \
5bb907a4	539	"fdtaddr=ae0000\0" \
bb0f5bc9	540	"fdtfile=" CONFIG_FDTFILE "\0" \
5bb907a4 RM	541	"console=ttyS0\0" \
	542	"setbootargs=setenv bootargs " \
	543	"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
bb0f5bc9 JH	544	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
	545	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	546	"$netdev:off " \
	547	"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
5bb907a4 RM	548	"load_uboot=tftp 100000 u-boot-nand.bin\0" \
	549	"burn_uboot=nand erase u-boot 80000; " \
	550	"nand write 100000 u-boot $filesize\0" \
	551	"update_uboot=run load_uboot;run burn_uboot\0" \
	552	"mtdids=nand0=nand0\0" \
	553	"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
	554	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	555	"nfsroot=${serverip}:${rootpath}\0" \
	556	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	557	"addip=setenv bootargs ${bootargs} " \
	558	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	559	":${hostname}:${netdev}:off panic=1\0" \
bb0f5bc9	560	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
5bb907a4 RM	561	"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
	562	"console=ttyS0,115200\0" \
	563	""
	564
	565	#define CONFIG_NFSBOOTCOMMAND \
	566	"setenv rootdev /dev/nfs;" \
	567	"run setbootargs;" \
	568	"run setipargs;" \
	569	"tftp $loadaddr $bootfile;" \
	570	"tftp $fdtaddr $fdtfile;" \
	571	"bootm $loadaddr - $fdtaddr"
	572
	573	#define CONFIG_RAMBOOTCOMMAND \
	574	"setenv rootdev /dev/ram;" \
	575	"run setbootargs;" \
	576	"tftp $ramdiskaddr $ramdiskfile;" \
	577	"tftp $loadaddr $bootfile;" \
	578	"tftp $fdtaddr $fdtfile;" \
	579	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	580
5bb907a4	581	#endif /* __CONFIG_H */