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5bb907a4 RM |
1 | /* |
2 | * Copyright (C) Sheldon Instruments, Inc. 2008 | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | /* | |
23 | * simpc8313 board configuration file | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | */ | |
32 | #define CONFIG_NAND_U_BOOT | |
33 | ||
34 | #define CONFIG_E300 1 | |
0f898604 | 35 | #define CONFIG_MPC83xx 1 |
2c7920af | 36 | #define CONFIG_MPC831x 1 |
5bb907a4 RM |
37 | #define CONFIG_MPC8313 1 |
38 | ||
39 | #define CONFIG_PCI | |
5bb907a4 RM |
40 | |
41 | #define CONFIG_MISC_INIT_R | |
42 | ||
43 | /* | |
44 | * On-board devices | |
45 | * | |
46 | * TSEC1 is Marvell PHY 88E1118 | |
47 | */ | |
48 | ||
49 | #define CONFIG_SYS_33MHZ | |
50 | ||
51 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
52 | ||
53 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
54 | ||
55 | #define CONFIG_SYS_IMMR 0xE0000000 | |
56 | ||
57 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
58 | #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR | |
59 | #endif | |
60 | ||
61 | #define CONFIG_SYS_MEMTEST_START 0x00001000 | |
62 | #define CONFIG_SYS_MEMTEST_END 0x07f00000 | |
63 | ||
64 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ | |
65 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
66 | ||
67 | /* | |
68 | * Device configurations | |
69 | */ | |
70 | #define CONFIG_TSEC1 | |
71 | ||
72 | /* | |
73 | * DDR Setup | |
74 | */ | |
75 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ | |
76 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
77 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
78 | ||
79 | #define CONFIG_VERY_BIG_RAM | |
80 | #define CONFIG_MAX_MEM_MAPPED (512 << 20) | |
81 | ||
82 | #define CONFIG_SYS_DDRCDR ( DDRCDR_EN \ | |
83 | | DDRCDR_PZ_NOMZ \ | |
84 | | DDRCDR_NZ_NOMZ \ | |
85 | | DDRCDR_M_ODR ) | |
86 | /* 0x73000002 TODO ODR & DRN ? */ | |
87 | ||
88 | /* | |
89 | * FLASH on the Local Bus | |
90 | */ | |
91 | #define CONFIG_SYS_NO_FLASH | |
92 | ||
93 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
94 | ||
95 | #if !defined(CONFIG_NAND_SPL) | |
96 | #define CONFIG_SYS_RAMBOOT | |
97 | #endif | |
98 | ||
99 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
100 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
101 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ | |
102 | ||
103 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
104 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
105 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
106 | ||
107 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ | |
108 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
109 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
110 | ||
111 | /* | |
112 | * Local Bus LCRR and LBCR regs | |
113 | */ | |
c7190f02 KP |
114 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
115 | #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 | |
116 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
5bb907a4 RM |
117 | #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ |
118 | | (0xFF << LBCR_BMT_SHIFT) \ | |
119 | | 0xF ) /* 0x0004ff0f */ | |
120 | ||
121 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ | |
122 | ||
123 | /* drivers/mtd/nand/nand.c */ | |
124 | #ifdef CONFIG_NAND_SPL | |
125 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 | |
126 | #else | |
127 | #define CONFIG_SYS_NAND_BASE 0xE2800000 | |
128 | #endif | |
3b439792 | 129 | #define CONFIG_SYS_FPGA_BASE 0xFF000000 |
5bb907a4 RM |
130 | |
131 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
132 | #define NAND_MAX_CHIPS 1 | |
133 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
134 | #define CONFIG_CMD_NAND 1 | |
135 | #define CONFIG_NAND_FSL_ELBC 1 | |
136 | ||
137 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) | |
138 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 | |
139 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 | |
140 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
6e1385d5 | 141 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) |
5bb907a4 RM |
142 | |
143 | #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ | |
144 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
145 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
146 | | BR_MS_FCM /* MSEL = FCM */ \ | |
147 | | BR_V ) /* valid */ | |
148 | ||
149 | #ifdef CONFIG_NAND_SP | |
150 | #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ | |
151 | | OR_FCM_CSCT \ | |
152 | | OR_FCM_CST \ | |
153 | | OR_FCM_CHT \ | |
154 | | OR_FCM_SCY_1 \ | |
155 | | OR_FCM_TRLX \ | |
156 | | OR_FCM_EHTR ) | |
157 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */ | |
158 | #define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */ | |
159 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
160 | #define NAND_CACHE_PAGES 32 | |
161 | #elif defined(CONFIG_NAND_LP) | |
162 | #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \ | |
163 | | OR_FCM_PGS \ | |
164 | | OR_FCM_CSCT \ | |
165 | | OR_FCM_CST \ | |
166 | | OR_FCM_CHT \ | |
167 | | OR_FCM_SCY_1 \ | |
168 | | OR_FCM_TRLX \ | |
169 | | OR_FCM_EHTR ) | |
170 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */ | |
171 | #define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */ | |
172 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ | |
173 | #define NAND_CACHE_PAGES 64 | |
174 | #else | |
175 | #error Page size of NAND not defined. | |
176 | #endif /* CONFIG_NAND_SP */ | |
177 | ||
178 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE | |
179 | ||
180 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM | |
181 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
182 | ||
183 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE | |
184 | ||
185 | #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM | |
186 | #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM | |
187 | ||
3b439792 RM |
188 | #define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_FPGA_BASE \ |
189 | | BR_PS_16 \ | |
190 | | BR_MS_UPMA \ | |
191 | | BR_V ) | |
192 | #define CONFIG_SYS_OR1_PRELIM ( OR_AM_2MB \ | |
193 | | OR_UPM_BCTLD) | |
194 | ||
195 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE | |
196 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB) | |
197 | ||
5bb907a4 RM |
198 | /* |
199 | * JFFS2 configuration | |
200 | */ | |
201 | #define CONFIG_JFFS2_NAND | |
202 | #define CONFIG_JFFS2_DEV "nand0" | |
203 | ||
204 | /* mtdparts command line support */ | |
68d7d651 | 205 | #define CONFIG_CMD_MTDPARTS |
942556a9 | 206 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
5bb907a4 RM |
207 | #define MTDIDS_DEFAULT "nand0=nand0" |
208 | #define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)" | |
209 | ||
210 | /* pass open firmware flat tree */ | |
211 | #define CONFIG_OF_LIBFDT 1 | |
212 | #define CONFIG_OF_BOARD_SETUP 1 | |
213 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
214 | ||
215 | /* | |
216 | * Serial Port | |
217 | */ | |
218 | #define CONFIG_CONS_INDEX 1 | |
219 | #define CONFIG_SYS_NS16550 | |
220 | #define CONFIG_SYS_NS16550_SERIAL | |
221 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
f5675aa5 RM |
222 | #ifdef CONFIG_NAND_SPL |
223 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
224 | #endif | |
5bb907a4 RM |
225 | |
226 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
227 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
228 | ||
229 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) | |
230 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
231 | ||
232 | /* Use the HUSH parser */ | |
233 | #define CONFIG_SYS_HUSH_PARSER | |
234 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
235 | ||
236 | /* I2C */ | |
237 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
238 | #define CONFIG_FSL_I2C | |
239 | #define CONFIG_I2C_MULTI_BUS | |
5bb907a4 RM |
240 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
241 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
242 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ | |
243 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
244 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
245 | ||
246 | /* | |
247 | * General PCI | |
248 | * Addresses are mapped 1-1. | |
249 | */ | |
250 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 | |
251 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
252 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
253 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
254 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
255 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
256 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
257 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
258 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
259 | ||
260 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
261 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
262 | ||
263 | /* | |
264 | * TSEC | |
265 | */ | |
266 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
267 | ||
268 | #define CONFIG_NET_MULTI | |
269 | #define CONFIG_GMII /* MII PHY management */ | |
270 | ||
271 | #ifdef CONFIG_TSEC1 | |
272 | #define CONFIG_HAS_ETH0 | |
273 | #define CONFIG_TSEC1_NAME "TSEC0" | |
274 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 | |
275 | #define TSEC1_PHY_ADDR 0x0 | |
276 | #define TSEC1_FLAGS TSEC_GIGABIT | |
277 | #define TSEC1_PHYIDX 0 | |
278 | #endif | |
279 | ||
280 | #ifdef CONFIG_TSEC2 | |
281 | #define CONFIG_HAS_ETH1 | |
282 | #define CONFIG_TSEC2_NAME "TSEC1" | |
283 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
284 | #define TSEC2_PHY_ADDR 4 | |
285 | #define TSEC2_FLAGS TSEC_GIGABIT | |
286 | #define TSEC2_PHYIDX 0 | |
287 | #endif | |
288 | ||
289 | ||
290 | /* Options are: TSEC[0-1] */ | |
291 | #define CONFIG_ETHPRIME "TSEC1" | |
292 | ||
293 | /* | |
294 | * Configure on-board RTC | |
295 | */ | |
296 | #define CONFIG_RTC_DS1337 | |
297 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
298 | ||
299 | /* | |
300 | * Environment | |
301 | */ | |
302 | #if defined(CONFIG_NAND_U_BOOT) | |
303 | #define CONFIG_ENV_IS_IN_NAND 1 | |
304 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
305 | #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
306 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
307 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
308 | #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) | |
309 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) | |
310 | #elif !defined(CONFIG_SYS_RAMBOOT) | |
311 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
312 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
313 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ | |
314 | #define CONFIG_ENV_SIZE 0x2000 | |
315 | ||
316 | /* Address and size of Redundant Environment Sector */ | |
317 | #else | |
318 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
319 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
320 | #define CONFIG_ENV_SIZE 0x2000 | |
321 | #endif | |
322 | ||
323 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
324 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
325 | ||
326 | /* | |
327 | * BOOTP options | |
328 | */ | |
329 | #define CONFIG_BOOTP_BOOTFILESIZE | |
330 | #define CONFIG_BOOTP_BOOTPATH | |
331 | #define CONFIG_BOOTP_GATEWAY | |
332 | #define CONFIG_BOOTP_HOSTNAME | |
333 | ||
334 | ||
335 | /* | |
336 | * Command line configuration. | |
337 | */ | |
338 | #include <config_cmd_default.h> | |
339 | #undef CONFIG_CMD_IMLS | |
340 | #undef CONFIG_CMD_FLASH | |
341 | ||
342 | #define CONFIG_CMD_PING | |
343 | #define CONFIG_CMD_DHCP | |
344 | #define CONFIG_CMD_I2C | |
345 | #define CONFIG_CMD_MII | |
346 | #define CONFIG_CMD_DATE | |
347 | #define CONFIG_CMD_PCI | |
348 | #define CONFIG_CMD_JFFS2 | |
349 | ||
350 | #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) | |
bdab39d3 | 351 | #undef CONFIG_CMD_SAVEENV |
5bb907a4 RM |
352 | #undef CONFIG_CMD_LOADS |
353 | #endif | |
354 | ||
355 | #define CONFIG_CMDLINE_EDITING 1 | |
a059e90e | 356 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
5bb907a4 RM |
357 | |
358 | /* | |
359 | * Miscellaneous configurable options | |
360 | */ | |
361 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
362 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
363 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
364 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
365 | ||
366 | #define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \ | |
367 | + sizeof(CONFIG_SYS_PROMPT) \ | |
368 | + 16 ) /* Print Buffer Size */ | |
369 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
370 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
371 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
372 | ||
373 | /* | |
374 | * For booting Linux, the board info and command line data | |
375 | * have to be in the first 8 MB of memory, since this is | |
376 | * the maximum mapped by the Linux kernel during initialization. | |
377 | */ | |
378 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
379 | ||
380 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ | |
381 | ||
382 | #define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \ | |
383 | | 0x20000000 /* reserved */ \ | |
384 | | HRCWL_DDR_TO_SCB_CLK_2X1 \ | |
385 | | HRCWL_CSB_TO_CLKIN_4X1 \ | |
386 | | HRCWL_CORE_TO_CSB_2_5X1 ) | |
387 | ||
388 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4) | |
389 | ||
390 | #define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \ | |
391 | | HRCWH_PCI1_ARBITER_ENABLE \ | |
392 | | HRCWH_CORE_ENABLE \ | |
393 | | HRCWH_BOOTSEQ_DISABLE \ | |
394 | | HRCWH_SW_WATCHDOG_DISABLE \ | |
395 | | HRCWH_TSEC1M_IN_RGMII \ | |
396 | | HRCWH_TSEC2M_IN_RGMII \ | |
397 | | HRCWH_BIG_ENDIAN \ | |
398 | | HRCWH_LALE_NORMAL ) | |
399 | ||
400 | #ifdef CONFIG_NAND_LP | |
401 | #define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ | |
402 | | HRCWH_FROM_0XFFF00100 \ | |
403 | | HRCWH_ROM_LOC_NAND_LP_8BIT \ | |
404 | | HRCWH_RL_EXT_NAND) | |
405 | #else | |
406 | #define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ | |
407 | | HRCWH_FROM_0XFFF00100 \ | |
408 | | HRCWH_ROM_LOC_NAND_SP_8BIT \ | |
409 | | HRCWH_RL_EXT_NAND ) | |
410 | #endif | |
411 | ||
412 | /* System IO Config */ | |
413 | #define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \ | |
414 | | SICRH_ETSEC2_C \ | |
415 | | SICRH_ETSEC2_D \ | |
416 | | SICRH_ETSEC2_E \ | |
417 | | SICRH_ETSEC2_F \ | |
418 | | SICRH_ETSEC2_G \ | |
419 | | SICRH_TSOBI1 \ | |
420 | | SICRH_TSOBI2 ) | |
421 | #define CONFIG_SYS_SICRL (SICRL_USBDR \ | |
422 | | SICRL_ETSEC2_A ) | |
423 | ||
424 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
1a2e203b KP |
425 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
426 | HID0_ENABLE_INSTRUCTION_CACHE | \ | |
427 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT ) | |
5bb907a4 RM |
428 | |
429 | #define CONFIG_SYS_HID2 HID2_HBE | |
430 | ||
431 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ | |
432 | ||
433 | /* DDR @ 0x00000000 */ | |
434 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) | |
435 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
436 | #define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10) | |
437 | #define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP) | |
438 | ||
439 | /* PCI @ 0x80000000 */ | |
440 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) | |
441 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
442 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
443 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
444 | ||
445 | /* PCI2 not supported on 8313 */ | |
446 | #define CONFIG_SYS_IBAT4L (0) | |
447 | #define CONFIG_SYS_IBAT4U (0) | |
448 | ||
449 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ | |
450 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
451 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
452 | ||
453 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
c1230980 | 454 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) |
5bb907a4 RM |
455 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
456 | ||
457 | #define CONFIG_SYS_IBAT7L (0) | |
458 | #define CONFIG_SYS_IBAT7U (0) | |
459 | ||
460 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
461 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
462 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
463 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
464 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
465 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
466 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
467 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
468 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
469 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
470 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
471 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
472 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
473 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
474 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
475 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
476 | ||
477 | /* | |
478 | * Internal Definitions | |
479 | * | |
480 | * Boot Flags | |
481 | */ | |
482 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
483 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
484 | ||
485 | /* | |
486 | * Environment Configuration | |
487 | */ | |
488 | #define CONFIG_ENV_OVERWRITE | |
489 | ||
490 | #define CONFIG_NETDEV eth1 | |
491 | ||
492 | #define CONFIG_HOSTNAME simpc8313 | |
493 | #define CONFIG_ROOTPATH /tftpboot/ | |
494 | #define CONFIG_BOOTFILE /tftpboot/uImage | |
495 | #define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */ | |
496 | #define CONFIG_FDTFILE simpc8313.dtb | |
497 | ||
498 | #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ | |
499 | #define CONFIG_BOOTDELAY 5 /* 5 second delay */ | |
500 | #define CONFIG_BAUDRATE 115200 | |
501 | ||
502 | #define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr" | |
503 | ||
504 | #define XMK_STR(x) #x | |
505 | #define MK_STR(x) XMK_STR(x) | |
506 | ||
507 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
508 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ | |
509 | "ethprime=TSEC1\0" \ | |
510 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
511 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
512 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
513 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
514 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
515 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
516 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
517 | "fdtaddr=ae0000\0" \ | |
518 | "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ | |
519 | "console=ttyS0\0" \ | |
520 | "setbootargs=setenv bootargs " \ | |
521 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
522 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
523 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
524 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
525 | "load_uboot=tftp 100000 u-boot-nand.bin\0" \ | |
526 | "burn_uboot=nand erase u-boot 80000; " \ | |
527 | "nand write 100000 u-boot $filesize\0" \ | |
528 | "update_uboot=run load_uboot;run burn_uboot\0" \ | |
529 | "mtdids=nand0=nand0\0" \ | |
530 | "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \ | |
531 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
532 | "nfsroot=${serverip}:${rootpath}\0" \ | |
533 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
534 | "addip=setenv bootargs ${bootargs} " \ | |
535 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
536 | ":${hostname}:${netdev}:off panic=1\0" \ | |
537 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ | |
538 | "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \ | |
539 | "console=ttyS0,115200\0" \ | |
540 | "" | |
541 | ||
542 | #define CONFIG_NFSBOOTCOMMAND \ | |
543 | "setenv rootdev /dev/nfs;" \ | |
544 | "run setbootargs;" \ | |
545 | "run setipargs;" \ | |
546 | "tftp $loadaddr $bootfile;" \ | |
547 | "tftp $fdtaddr $fdtfile;" \ | |
548 | "bootm $loadaddr - $fdtaddr" | |
549 | ||
550 | #define CONFIG_RAMBOOTCOMMAND \ | |
551 | "setenv rootdev /dev/ram;" \ | |
552 | "run setbootargs;" \ | |
553 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
554 | "tftp $loadaddr $bootfile;" \ | |
555 | "tftp $fdtaddr $fdtfile;" \ | |
556 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
557 | ||
558 | #undef MK_STR | |
559 | #undef XMK_STR | |
560 | ||
561 | #endif /* __CONFIG_H */ |