projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5bb907a4 RM |
1 | /* |
| 2 | * Copyright (C) Sheldon Instruments, Inc. 2008 | |
| 3 | * | |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | /* | |
| 23 | * simpc8313 board configuration file | |
| 24 | */ | |
| 25 | ||
| 26 | #ifndef __CONFIG_H | |
| 27 | #define __CONFIG_H | |
| 28 | ||
| 29 | /* | |
| 30 | * High Level Configuration Options | |
| 31 | */ | |
| 32 | #define CONFIG_NAND_U_BOOT | |
| 33 | ||
| 34 | #define CONFIG_E300 1 | |
| 35 | #define CONFIG_MPC83XX 1 | |
| 36 | #define CONFIG_MPC831X 1 | |
| 37 | #define CONFIG_MPC8313 1 | |
| 38 | ||
| 39 | #define CONFIG_PCI | |
| 40 | #define CONFIG_83XX_GENERIC_PCI | |
| 41 | ||
| 42 | #define CONFIG_MISC_INIT_R | |
| 43 | ||
| 44 | /* | |
| 45 | * On-board devices | |
| 46 | * | |
| 47 | * TSEC1 is Marvell PHY 88E1118 | |
| 48 | */ | |
| 49 | ||
| 50 | #define CONFIG_SYS_33MHZ | |
| 51 | ||
| 52 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
| 53 | ||
| 54 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
| 55 | ||
| 56 | #define CONFIG_SYS_IMMR 0xE0000000 | |
| 57 | ||
| 58 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
| 59 | #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR | |
| 60 | #endif | |
| 61 | ||
| 62 | #define CONFIG_SYS_MEMTEST_START 0x00001000 | |
| 63 | #define CONFIG_SYS_MEMTEST_END 0x07f00000 | |
| 64 | ||
| 65 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ | |
| 66 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
| 67 | ||
| 68 | /* | |
| 69 | * Device configurations | |
| 70 | */ | |
| 71 | #define CONFIG_TSEC1 | |
| 72 | ||
| 73 | /* | |
| 74 | * DDR Setup | |
| 75 | */ | |
| 76 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ | |
| 77 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 78 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 79 | ||
| 80 | #define CONFIG_VERY_BIG_RAM | |
| 81 | #define CONFIG_MAX_MEM_MAPPED (512 << 20) | |
| 82 | ||
| 83 | #define CONFIG_SYS_DDRCDR ( DDRCDR_EN \ | |
| 84 | | DDRCDR_PZ_NOMZ \ | |
| 85 | | DDRCDR_NZ_NOMZ \ | |
| 86 | | DDRCDR_M_ODR ) | |
| 87 | /* 0x73000002 TODO ODR & DRN ? */ | |
| 88 | ||
| 89 | /* | |
| 90 | * FLASH on the Local Bus | |
| 91 | */ | |
| 92 | #define CONFIG_SYS_NO_FLASH | |
| 93 | ||
| 94 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| 95 | ||
| 96 | #if !defined(CONFIG_NAND_SPL) | |
| 97 | #define CONFIG_SYS_RAMBOOT | |
| 98 | #endif | |
| 99 | ||
| 100 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
| 101 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
| 102 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ | |
| 103 | ||
| 104 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
| 105 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 106 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 107 | ||
| 108 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ | |
| 109 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
| 110 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
| 111 | ||
| 112 | /* | |
| 113 | * Local Bus LCRR and LBCR regs | |
| 114 | */ | |
| 115 | #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) | |
| 116 | #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ | |
| 117 | | (0xFF << LBCR_BMT_SHIFT) \ | |
| 118 | | 0xF ) /* 0x0004ff0f */ | |
| 119 | ||
| 120 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ | |
| 121 | ||
| 122 | /* drivers/mtd/nand/nand.c */ | |
| 123 | #ifdef CONFIG_NAND_SPL | |
| 124 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 | |
| 125 | #else | |
| 126 | #define CONFIG_SYS_NAND_BASE 0xE2800000 | |
| 127 | #endif | |
| 128 | ||
| 129 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 130 | #define NAND_MAX_CHIPS 1 | |
| 131 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
| 132 | #define CONFIG_CMD_NAND 1 | |
| 133 | #define CONFIG_NAND_FSL_ELBC 1 | |
| 134 | ||
| 135 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) | |
| 136 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 | |
| 137 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 | |
| 138 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
| 139 | ||
| 140 | #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ | |
| 141 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 142 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 143 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 144 | | BR_V ) /* valid */ | |
| 145 | ||
| 146 | #ifdef CONFIG_NAND_SP | |
| 147 | #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ | |
| 148 | | OR_FCM_CSCT \ | |
| 149 | | OR_FCM_CST \ | |
| 150 | | OR_FCM_CHT \ | |
| 151 | | OR_FCM_SCY_1 \ | |
| 152 | | OR_FCM_TRLX \ | |
| 153 | | OR_FCM_EHTR ) | |
| 154 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */ | |
| 155 | #define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */ | |
| 156 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
| 157 | #define NAND_CACHE_PAGES 32 | |
| 158 | #elif defined(CONFIG_NAND_LP) | |
| 159 | #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \ | |
| 160 | | OR_FCM_PGS \ | |
| 161 | | OR_FCM_CSCT \ | |
| 162 | | OR_FCM_CST \ | |
| 163 | | OR_FCM_CHT \ | |
| 164 | | OR_FCM_SCY_1 \ | |
| 165 | | OR_FCM_TRLX \ | |
| 166 | | OR_FCM_EHTR ) | |
| 167 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */ | |
| 168 | #define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */ | |
| 169 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ | |
| 170 | #define NAND_CACHE_PAGES 64 | |
| 171 | #else | |
| 172 | #error Page size of NAND not defined. | |
| 173 | #endif /* CONFIG_NAND_SP */ | |
| 174 | ||
| 175 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE | |
| 176 | ||
| 177 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM | |
| 178 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
| 179 | ||
| 180 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE | |
| 181 | ||
| 182 | #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM | |
| 183 | #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM | |
| 184 | ||
| 185 | /* | |
| 186 | * JFFS2 configuration | |
| 187 | */ | |
| 188 | #define CONFIG_JFFS2_NAND | |
| 189 | #define CONFIG_JFFS2_DEV "nand0" | |
| 190 | ||
| 191 | /* mtdparts command line support */ | |
| 68d7d651 | 192 | #define CONFIG_CMD_MTDPARTS |
| 942556a9 | 193 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
| 5bb907a4 RM |
194 | #define MTDIDS_DEFAULT "nand0=nand0" |
| 195 | #define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)" | |
| 196 | ||
| 197 | /* pass open firmware flat tree */ | |
| 198 | #define CONFIG_OF_LIBFDT 1 | |
| 199 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 200 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| 201 | ||
| 202 | /* | |
| 203 | * Serial Port | |
| 204 | */ | |
| 205 | #define CONFIG_CONS_INDEX 1 | |
| 206 | #define CONFIG_SYS_NS16550 | |
| 207 | #define CONFIG_SYS_NS16550_SERIAL | |
| 208 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| f5675aa5 RM |
209 | #ifdef CONFIG_NAND_SPL |
| 210 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
| 211 | #endif | |
| 5bb907a4 RM |
212 | |
| 213 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 214 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
| 215 | ||
| 216 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) | |
| 217 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
| 218 | ||
| 219 | /* Use the HUSH parser */ | |
| 220 | #define CONFIG_SYS_HUSH_PARSER | |
| 221 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 222 | ||
| 223 | /* I2C */ | |
| 224 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
| 225 | #define CONFIG_FSL_I2C | |
| 226 | #define CONFIG_I2C_MULTI_BUS | |
| 5bb907a4 RM |
227 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 228 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 229 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ | |
| 230 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 231 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 232 | ||
| 233 | /* | |
| 234 | * General PCI | |
| 235 | * Addresses are mapped 1-1. | |
| 236 | */ | |
| 237 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 | |
| 238 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
| 239 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 240 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
| 241 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
| 242 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
| 243 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
| 244 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
| 245 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
| 246 | ||
| 247 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 248 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
| 249 | ||
| 250 | /* | |
| 251 | * TSEC | |
| 252 | */ | |
| 253 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
| 254 | ||
| 255 | #define CONFIG_NET_MULTI | |
| 256 | #define CONFIG_GMII /* MII PHY management */ | |
| 257 | ||
| 258 | #ifdef CONFIG_TSEC1 | |
| 259 | #define CONFIG_HAS_ETH0 | |
| 260 | #define CONFIG_TSEC1_NAME "TSEC0" | |
| 261 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 | |
| 262 | #define TSEC1_PHY_ADDR 0x0 | |
| 263 | #define TSEC1_FLAGS TSEC_GIGABIT | |
| 264 | #define TSEC1_PHYIDX 0 | |
| 265 | #endif | |
| 266 | ||
| 267 | #ifdef CONFIG_TSEC2 | |
| 268 | #define CONFIG_HAS_ETH1 | |
| 269 | #define CONFIG_TSEC2_NAME "TSEC1" | |
| 270 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
| 271 | #define TSEC2_PHY_ADDR 4 | |
| 272 | #define TSEC2_FLAGS TSEC_GIGABIT | |
| 273 | #define TSEC2_PHYIDX 0 | |
| 274 | #endif | |
| 275 | ||
| 276 | ||
| 277 | /* Options are: TSEC[0-1] */ | |
| 278 | #define CONFIG_ETHPRIME "TSEC1" | |
| 279 | ||
| 280 | /* | |
| 281 | * Configure on-board RTC | |
| 282 | */ | |
| 283 | #define CONFIG_RTC_DS1337 | |
| 284 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 285 | ||
| 286 | /* | |
| 287 | * Environment | |
| 288 | */ | |
| 289 | #if defined(CONFIG_NAND_U_BOOT) | |
| 290 | #define CONFIG_ENV_IS_IN_NAND 1 | |
| 291 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
| 292 | #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
| 293 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
| 294 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
| 295 | #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) | |
| 296 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) | |
| 297 | #elif !defined(CONFIG_SYS_RAMBOOT) | |
| 298 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
| 299 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
| 300 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ | |
| 301 | #define CONFIG_ENV_SIZE 0x2000 | |
| 302 | ||
| 303 | /* Address and size of Redundant Environment Sector */ | |
| 304 | #else | |
| 305 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
| 306 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
| 307 | #define CONFIG_ENV_SIZE 0x2000 | |
| 308 | #endif | |
| 309 | ||
| 310 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 311 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 312 | ||
| 313 | /* | |
| 314 | * BOOTP options | |
| 315 | */ | |
| 316 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 317 | #define CONFIG_BOOTP_BOOTPATH | |
| 318 | #define CONFIG_BOOTP_GATEWAY | |
| 319 | #define CONFIG_BOOTP_HOSTNAME | |
| 320 | ||
| 321 | ||
| 322 | /* | |
| 323 | * Command line configuration. | |
| 324 | */ | |
| 325 | #include <config_cmd_default.h> | |
| 326 | #undef CONFIG_CMD_IMLS | |
| 327 | #undef CONFIG_CMD_FLASH | |
| 328 | ||
| 329 | #define CONFIG_CMD_PING | |
| 330 | #define CONFIG_CMD_DHCP | |
| 331 | #define CONFIG_CMD_I2C | |
| 332 | #define CONFIG_CMD_MII | |
| 333 | #define CONFIG_CMD_DATE | |
| 334 | #define CONFIG_CMD_PCI | |
| 335 | #define CONFIG_CMD_JFFS2 | |
| 336 | ||
| 337 | #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) | |
| bdab39d3 | 338 | #undef CONFIG_CMD_SAVEENV |
| 5bb907a4 RM |
339 | #undef CONFIG_CMD_LOADS |
| 340 | #endif | |
| 341 | ||
| 342 | #define CONFIG_CMDLINE_EDITING 1 | |
| 343 | ||
| 344 | ||
| 345 | /* | |
| 346 | * Miscellaneous configurable options | |
| 347 | */ | |
| 348 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 349 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 350 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 351 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 352 | ||
| 353 | #define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \ | |
| 354 | + sizeof(CONFIG_SYS_PROMPT) \ | |
| 355 | + 16 ) /* Print Buffer Size */ | |
| 356 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 357 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 358 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 359 | ||
| 360 | /* | |
| 361 | * For booting Linux, the board info and command line data | |
| 362 | * have to be in the first 8 MB of memory, since this is | |
| 363 | * the maximum mapped by the Linux kernel during initialization. | |
| 364 | */ | |
| 365 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
| 366 | ||
| 367 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ | |
| 368 | ||
| 369 | #define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \ | |
| 370 | | 0x20000000 /* reserved */ \ | |
| 371 | | HRCWL_DDR_TO_SCB_CLK_2X1 \ | |
| 372 | | HRCWL_CSB_TO_CLKIN_4X1 \ | |
| 373 | | HRCWL_CORE_TO_CSB_2_5X1 ) | |
| 374 | ||
| 375 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4) | |
| 376 | ||
| 377 | #define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \ | |
| 378 | | HRCWH_PCI1_ARBITER_ENABLE \ | |
| 379 | | HRCWH_CORE_ENABLE \ | |
| 380 | | HRCWH_BOOTSEQ_DISABLE \ | |
| 381 | | HRCWH_SW_WATCHDOG_DISABLE \ | |
| 382 | | HRCWH_TSEC1M_IN_RGMII \ | |
| 383 | | HRCWH_TSEC2M_IN_RGMII \ | |
| 384 | | HRCWH_BIG_ENDIAN \ | |
| 385 | | HRCWH_LALE_NORMAL ) | |
| 386 | ||
| 387 | #ifdef CONFIG_NAND_LP | |
| 388 | #define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ | |
| 389 | | HRCWH_FROM_0XFFF00100 \ | |
| 390 | | HRCWH_ROM_LOC_NAND_LP_8BIT \ | |
| 391 | | HRCWH_RL_EXT_NAND) | |
| 392 | #else | |
| 393 | #define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ | |
| 394 | | HRCWH_FROM_0XFFF00100 \ | |
| 395 | | HRCWH_ROM_LOC_NAND_SP_8BIT \ | |
| 396 | | HRCWH_RL_EXT_NAND ) | |
| 397 | #endif | |
| 398 | ||
| 399 | /* System IO Config */ | |
| 400 | #define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \ | |
| 401 | | SICRH_ETSEC2_C \ | |
| 402 | | SICRH_ETSEC2_D \ | |
| 403 | | SICRH_ETSEC2_E \ | |
| 404 | | SICRH_ETSEC2_F \ | |
| 405 | | SICRH_ETSEC2_G \ | |
| 406 | | SICRH_TSOBI1 \ | |
| 407 | | SICRH_TSOBI2 ) | |
| 408 | #define CONFIG_SYS_SICRL (SICRL_USBDR \ | |
| 409 | | SICRL_ETSEC2_A ) | |
| 410 | ||
| 411 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
| 412 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ | |
| 413 | | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT ) | |
| 414 | ||
| 415 | #define CONFIG_SYS_HID2 HID2_HBE | |
| 416 | ||
| 417 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ | |
| 418 | ||
| 419 | /* DDR @ 0x00000000 */ | |
| 420 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) | |
| 421 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 422 | #define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10) | |
| 423 | #define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 424 | ||
| 425 | /* PCI @ 0x80000000 */ | |
| 426 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) | |
| 427 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 428 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 429 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 430 | ||
| 431 | /* PCI2 not supported on 8313 */ | |
| 432 | #define CONFIG_SYS_IBAT4L (0) | |
| 433 | #define CONFIG_SYS_IBAT4U (0) | |
| 434 | ||
| 435 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ | |
| 436 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 437 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 438 | ||
| 439 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
| c1230980 | 440 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) |
| 5bb907a4 RM |
441 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
| 442 | ||
| 443 | #define CONFIG_SYS_IBAT7L (0) | |
| 444 | #define CONFIG_SYS_IBAT7U (0) | |
| 445 | ||
| 446 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
| 447 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 448 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 449 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 450 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
| 451 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
| 452 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
| 453 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| 454 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
| 455 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| 456 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
| 457 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| 458 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
| 459 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| 460 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
| 461 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
| 462 | ||
| 463 | /* | |
| 464 | * Internal Definitions | |
| 465 | * | |
| 466 | * Boot Flags | |
| 467 | */ | |
| 468 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 469 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 470 | ||
| 471 | /* | |
| 472 | * Environment Configuration | |
| 473 | */ | |
| 474 | #define CONFIG_ENV_OVERWRITE | |
| 475 | ||
| 476 | #define CONFIG_NETDEV eth1 | |
| 477 | ||
| 478 | #define CONFIG_HOSTNAME simpc8313 | |
| 479 | #define CONFIG_ROOTPATH /tftpboot/ | |
| 480 | #define CONFIG_BOOTFILE /tftpboot/uImage | |
| 481 | #define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */ | |
| 482 | #define CONFIG_FDTFILE simpc8313.dtb | |
| 483 | ||
| 484 | #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ | |
| 485 | #define CONFIG_BOOTDELAY 5 /* 5 second delay */ | |
| 486 | #define CONFIG_BAUDRATE 115200 | |
| 487 | ||
| 488 | #define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr" | |
| 489 | ||
| 490 | #define XMK_STR(x) #x | |
| 491 | #define MK_STR(x) XMK_STR(x) | |
| 492 | ||
| 493 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 494 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ | |
| 495 | "ethprime=TSEC1\0" \ | |
| 496 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 497 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 498 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 499 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 500 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
| 501 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 502 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
| 503 | "fdtaddr=ae0000\0" \ | |
| 504 | "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ | |
| 505 | "console=ttyS0\0" \ | |
| 506 | "setbootargs=setenv bootargs " \ | |
| 507 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
| 508 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
| 509 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 510 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
| 511 | "load_uboot=tftp 100000 u-boot-nand.bin\0" \ | |
| 512 | "burn_uboot=nand erase u-boot 80000; " \ | |
| 513 | "nand write 100000 u-boot $filesize\0" \ | |
| 514 | "update_uboot=run load_uboot;run burn_uboot\0" \ | |
| 515 | "mtdids=nand0=nand0\0" \ | |
| 516 | "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \ | |
| 517 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 518 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 519 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 520 | "addip=setenv bootargs ${bootargs} " \ | |
| 521 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 522 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 523 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ | |
| 524 | "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \ | |
| 525 | "console=ttyS0,115200\0" \ | |
| 526 | "" | |
| 527 | ||
| 528 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 529 | "setenv rootdev /dev/nfs;" \ | |
| 530 | "run setbootargs;" \ | |
| 531 | "run setipargs;" \ | |
| 532 | "tftp $loadaddr $bootfile;" \ | |
| 533 | "tftp $fdtaddr $fdtfile;" \ | |
| 534 | "bootm $loadaddr - $fdtaddr" | |
| 535 | ||
| 536 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 537 | "setenv rootdev /dev/ram;" \ | |
| 538 | "run setbootargs;" \ | |
| 539 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 540 | "tftp $loadaddr $bootfile;" \ | |
| 541 | "tftp $fdtaddr $fdtfile;" \ | |
| 542 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 543 | ||
| 544 | #undef MK_STR | |
| 545 | #undef XMK_STR | |
| 546 | ||
| 547 | #endif /* __CONFIG_H */ |