[people/ms/u-boot.git] / include / configs / SIMPC8313.h

/*
 * Copyright (C) Sheldon Instruments, Inc. 2008
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
/*
 * simpc8313 board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_NAND_U_BOOT

#define CONFIG_E300			1
#define CONFIG_MPC83xx			1
#define CONFIG_MPC831x			1
#define CONFIG_MPC8313			1

#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START	0x00100100
#define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)

#define CONFIG_SYS_TEXT_BASE	0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000

#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#define CONFIG_PCI
#define CONFIG_FSL_ELBC			1

#define CONFIG_MISC_INIT_R

/*
 * On-board devices
 *
 * TSEC1 is Marvell PHY 88E1118
 */

#define CONFIG_SYS_33MHZ

#define CONFIG_83XX_CLKIN		33333333	/* in Hz */

#define CONFIG_SYS_CLK_FREQ		CONFIG_83XX_CLKIN

#define CONFIG_SYS_IMMR			0xE0000000

#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DEFAULT_IMMR		CONFIG_SYS_IMMR
#endif

#define CONFIG_SYS_MEMTEST_START	0x00001000
#define CONFIG_SYS_MEMTEST_END		0x07f00000

#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */

/*
 * Device configurations
 */
#define CONFIG_TSEC1

/*
 * DDR Setup
 */
					/* DDR is system memory*/
#define CONFIG_SYS_DDR_BASE		0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE

#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED		(512 << 20)

#define CONFIG_SYS_DDRCDR		(DDRCDR_EN \
					| DDRCDR_PZ_NOMZ \
					| DDRCDR_NZ_NOMZ \
					| DDRCDR_M_ODR)
					/* 0x73000002 TODO ODR & DRN ? */

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_NO_FLASH

#if !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */

/*
 * Local Bus LCRR and LBCR regs
 */
#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
				| (0xFF << LBCR_BMT_SHIFT) \
				| 0xF)	/* 0x0004ff0f */

				/* LB refresh timer prescal, 266MHz/32 */
#define CONFIG_SYS_LBC_MRTPR	0x20000000

/* drivers/mtd/nand/nand.c */
#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE		0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE		0xE2800000
#endif
#define CONFIG_SYS_FPGA_BASE		0xFF000000

#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS			1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND			1
#define CONFIG_NAND_FSL_ELBC		1

#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
				| BR_PS_8		/* 8 bit Port */ \
				| BR_MS_FCM		/* MSEL = FCM */ \
				| BR_V)			/* valid */

#ifdef CONFIG_NAND_SP
#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFF8000	/* length 32K */ \
					| OR_FCM_CSCT \
					| OR_FCM_CST \
					| OR_FCM_CHT \
					| OR_FCM_SCY_1 \
					| OR_FCM_TRLX \
					| OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000000E	/* 32KB */
#define CONFIG_SYS_NAND_PAGE_SIZE	(512)	/* NAND chip page size */
					/* NAND chip block size */
#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)
#define NAND_CACHE_PAGES		32
#elif defined(CONFIG_NAND_LP)
#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFC0000	/* length 256K */ \
					| OR_FCM_PGS \
					| OR_FCM_CSCT \
					| OR_FCM_CST \
					| OR_FCM_CHT \
					| OR_FCM_SCY_1 \
					| OR_FCM_TRLX \
					| OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000011	/* 256KB */
#define CONFIG_SYS_NAND_PAGE_SIZE	(2048)	/* NAND chip page size */
					/* NAND chip block size */
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
#define NAND_CACHE_PAGES		64
#else
#error Page size of NAND not defined.
#endif /* CONFIG_NAND_SP */

#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SYS_NAND_BLOCK_SIZE

#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_NAND_OR_PRELIM

#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM	CONFIG_SYS_LBLAWBAR0_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM	CONFIG_SYS_LBLAWAR0_PRELIM

#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_FPGA_BASE \
					| BR_PS_16 \
					| BR_MS_UPMA \
					| BR_V)
#define CONFIG_SYS_OR1_PRELIM		(OR_AM_2MB \
					| OR_UPM_BCTLD)

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_FPGA_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_2MB)

/*
 * JFFS2 configuration
 */
#define CONFIG_JFFS2_NAND
#define CONFIG_JFFS2_DEV	"nand0"

/* mtdparts command line support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define MTDIDS_DEFAULT		"nand0=nand0"
#define MTDPARTS_DEFAULT	"mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#ifdef CONFIG_NAND_SPL
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif

#define CONFIG_SYS_BAUDRATE_TABLE	\
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

/* I2C */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE	0x7F
#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x69} } /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C2_OFFSET	0x3100

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */

#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1057	/* Motorola */

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET		/* TSEC ethernet support */

#define CONFIG_GMII			/* MII PHY management */

#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME		"TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET		0x24000
#define TSEC1_PHY_ADDR			0x0
#define TSEC1_FLAGS			TSEC_GIGABIT
#define TSEC1_PHYIDX			0
#endif

#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME		"TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET		0x25000
#define TSEC2_PHY_ADDR			4
#define TSEC2_FLAGS			TSEC_GIGABIT
#define TSEC2_PHYIDX			0
#endif


/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME			"TSEC1"

/*
 * Configure on-board RTC
 */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR		0x68

/*
 * Environment
 */
#if defined(CONFIG_NAND_U_BOOT)
	#define CONFIG_ENV_IS_IN_NAND	1
	#define CONFIG_ENV_OFFSET	(768 * 1024)
	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
	#define CONFIG_ENV_RANGE	(CONFIG_ENV_SECT_SIZE * 4)
	#define CONFIG_ENV_OFFSET_REDUND	\
					(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#elif !defined(CONFIG_SYS_RAMBOOT)
	#define CONFIG_ENV_IS_IN_FLASH	1
	#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
	#define CONFIG_ENV_SIZE		0x2000

/* Address and size of Redundant Environment Sector */
#else
	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO		1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1 /* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FLASH

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_JFFS2

#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
	#undef CONFIG_CMD_SAVEENV
	#undef CONFIG_CMD_LOADS
#endif

#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */

#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE		\
				+ sizeof(CONFIG_SYS_PROMPT)	\
				+ 16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
				/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)

#define CONFIG_SYS_RCWH_PCIHOST	0x80000000	/* PCIHOST */

#define CONFIG_SYS_HRCW_LOW	(HRCWL_LCL_BUS_TO_SCB_CLK_1X1	\
				| 0x20000000 /* reserved */	\
				| HRCWL_DDR_TO_SCB_CLK_2X1	\
				| HRCWL_CSB_TO_CLKIN_4X1	\
				| HRCWL_CORE_TO_CSB_2_5X1)

#define CONFIG_SYS_NS16550_CLK	(CONFIG_83XX_CLKIN * 4)

#define CONFIG_SYS_HRCW_HIGH_BASE	(HRCWH_PCI_HOST	\
				| HRCWH_PCI1_ARBITER_ENABLE	\
				| HRCWH_CORE_ENABLE		\
				| HRCWH_BOOTSEQ_DISABLE		\
				| HRCWH_SW_WATCHDOG_DISABLE	\
				| HRCWH_TSEC1M_IN_RGMII		\
				| HRCWH_TSEC2M_IN_RGMII		\
				| HRCWH_BIG_ENDIAN		\
				| HRCWH_LALE_NORMAL)

#ifdef CONFIG_NAND_LP
#define CONFIG_SYS_HRCW_HIGH	(CONFIG_SYS_HRCW_HIGH_BASE	\
				| HRCWH_FROM_0XFFF00100		\
				| HRCWH_ROM_LOC_NAND_LP_8BIT	\
				| HRCWH_RL_EXT_NAND)
#else
#define CONFIG_SYS_HRCW_HIGH	(CONFIG_SYS_HRCW_HIGH_BASE	\
				| HRCWH_FROM_0XFFF00100		\
				| HRCWH_ROM_LOC_NAND_SP_8BIT	\
				| HRCWH_RL_EXT_NAND)
#endif

/* System IO Config */
#define CONFIG_SYS_SICRH	(SICRH_ETSEC2_B	\
				| SICRH_ETSEC2_C	\
				| SICRH_ETSEC2_D	\
				| SICRH_ETSEC2_E	\
				| SICRH_ETSEC2_F	\
				| SICRH_ETSEC2_G	\
				| SICRH_TSOBI1		\
				| SICRH_TSOBI2)
#define CONFIG_SYS_SICRL	(SICRL_LBC		\
				| SICRL_USBDR_10	\
				| SICRL_ETSEC2_A)

#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
				| HID0_ENABLE_INSTRUCTION_CACHE \
				| HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)

#define CONFIG_SYS_HID2		HID2_HBE

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT1L	((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
				| BATL_PP_10)
#define CONFIG_SYS_IBAT1U	((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* PCI @ 0x80000000 */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATL_PP_10 \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* PCI2 not supported on 8313 */
#define CONFIG_SYS_IBAT4L	(0)
#define CONFIG_SYS_IBAT4U	(0)

/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
				| BATL_PP_10 \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L	(0xF0000000 \
				| BATL_PP_10 \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(0xF0000000 \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_NETDEV		"eth1"

#define CONFIG_HOSTNAME		simpc8313
#define CONFIG_ROOTPATH		"/tftpboot/"
#define CONFIG_BOOTFILE		"/tftpboot/uImage"
				/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH	"u-boot-nand.bin"
#define CONFIG_FDTFILE		"simpc8313.dtb"

				/* default location for tftp and bootm */
#define CONFIG_LOADADDR		500000
#define CONFIG_BOOTDELAY	5	/* 5 second delay */
#define CONFIG_BAUDRATE		115200

#define CONFIG_BOOTCOMMAND	"nand read $loadaddr kernel 600000;" \
					"bootm $loadaddr - $fdtaddr"

#define XMK_STR(x)	#x
#define MK_STR(x)	XMK_STR(x)

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" CONFIG_NETDEV "\0"					\
	"ethprime=TSEC1\0"						\
	"uboot=" CONFIG_UBOOTPATH "\0"					\
	"tftpflash=tftpboot $loadaddr $uboot; "				\
		"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
		"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
		"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
		"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
		"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
	"fdtaddr=ae0000\0"						\
	"fdtfile=" CONFIG_FDTFILE "\0"					\
	"console=ttyS0\0"						\
	"setbootargs=setenv bootargs "					\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
	"load_uboot=tftp 100000 u-boot-nand.bin\0"			\
	"burn_uboot=nand erase u-boot 80000; "				\
		"nand write 100000 u-boot $filesize\0"			\
	"update_uboot=run load_uboot;run burn_uboot\0"			\
	"mtdids=nand0=nand0\0"						\
	"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "		\
		"console=ttyS0,115200\0"				\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv rootdev /dev/nfs;"					\
	"run setbootargs;"						\
	"run setipargs;"						\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv rootdev /dev/ram;"					\
	"run setbootargs;"						\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#undef MK_STR
#undef XMK_STR

#endif	/* __CONFIG_H */
Commit	Line	Data
5bb907a4 RM	1	/*
	2	* Copyright (C) Sheldon Instruments, Inc. 2008
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22	/*
	23	* simpc8313 board configuration file
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	/*
	30	* High Level Configuration Options
	31	*/
	32	#define CONFIG_NAND_U_BOOT
	33
	34	#define CONFIG_E300 1
0f898604	35	#define CONFIG_MPC83xx 1
2c7920af	36	#define CONFIG_MPC831x 1
5bb907a4 RM	37	#define CONFIG_MPC8313 1
5bb907a4 RM	38
f1c574d4 SW	39	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
	40	#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
	41	#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
	42	#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
	43	#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
	44
	45	#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
	46	#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
	47
	48	#ifdef CONFIG_NAND_SPL
	49	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
	50	#else
	51	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
2ae18241 WD	52	#endif
2ae18241 WD	53
5bb907a4	54	#define CONFIG_PCI
0914f483	55	#define CONFIG_FSL_ELBC 1
5bb907a4 RM	56
	57	#define CONFIG_MISC_INIT_R
	58
	59	/*
	60	* On-board devices
	61	*
	62	* TSEC1 is Marvell PHY 88E1118
	63	*/
	64
	65	#define CONFIG_SYS_33MHZ
	66
	67	#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
	68
	69	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	70
	71	#define CONFIG_SYS_IMMR 0xE0000000
	72
	73	#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
	74	#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
	75	#endif
	76
	77	#define CONFIG_SYS_MEMTEST_START 0x00001000
	78	#define CONFIG_SYS_MEMTEST_END 0x07f00000
	79
bb0f5bc9 JH	80	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
bb0f5bc9 JH	81	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
5bb907a4 RM	82
	83	/*
	84	* Device configurations
	85	*/
	86	#define CONFIG_TSEC1
	87
	88	/*
	89	* DDR Setup
	90	*/
bb0f5bc9 JH	91	/* DDR is system memory*/
bb0f5bc9 JH	92	#define CONFIG_SYS_DDR_BASE 0x00000000
5bb907a4 RM	93	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	94	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	95
	96	#define CONFIG_VERY_BIG_RAM
	97	#define CONFIG_MAX_MEM_MAPPED (512 << 20)
	98
bb0f5bc9	99	#define CONFIG_SYS_DDRCDR (DDRCDR_EN \
5bb907a4 RM	100	\| DDRCDR_PZ_NOMZ \
5bb907a4 RM	101	\| DDRCDR_NZ_NOMZ \
bb0f5bc9	102	\| DDRCDR_M_ODR)
5bb907a4 RM	103	/* 0x73000002 TODO ODR & DRN ? */
	104
	105	/*
	106	* FLASH on the Local Bus
	107	*/
	108	#define CONFIG_SYS_NO_FLASH
	109
5bb907a4 RM	110	#if !defined(CONFIG_NAND_SPL)
	111	#define CONFIG_SYS_RAMBOOT
	112	#endif
	113
	114	#define CONFIG_SYS_INIT_RAM_LOCK 1
bb0f5bc9 JH	115	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
bb0f5bc9 JH	116	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
5bb907a4	117
bb0f5bc9 JH	118	#define CONFIG_SYS_GBL_DATA_OFFSET \
bb0f5bc9 JH	119	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
5bb907a4 RM	120	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	121
	122	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
bb0f5bc9 JH	123	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
bb0f5bc9 JH	124	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
5bb907a4 RM	125
	126	/*
	127	* Local Bus LCRR and LBCR regs
	128	*/
c7190f02 KP	129	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
	130	#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
	131	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
5bb907a4 RM	132	#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
5bb907a4 RM	133	\| (0xFF << LBCR_BMT_SHIFT) \
bb0f5bc9	134	\| 0xF) /* 0x0004ff0f */
5bb907a4	135
bb0f5bc9 JH	136	/* LB refresh timer prescal, 266MHz/32 */
bb0f5bc9 JH	137	#define CONFIG_SYS_LBC_MRTPR 0x20000000
5bb907a4 RM	138
	139	/* drivers/mtd/nand/nand.c */
	140	#ifdef CONFIG_NAND_SPL
	141	#define CONFIG_SYS_NAND_BASE 0xFFF00000
	142	#else
	143	#define CONFIG_SYS_NAND_BASE 0xE2800000
	144	#endif
3b439792	145	#define CONFIG_SYS_FPGA_BASE 0xFF000000
5bb907a4 RM	146
	147	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	148	#define NAND_MAX_CHIPS 1
	149	#define CONFIG_MTD_NAND_VERIFY_WRITE
bb0f5bc9	150	#define CONFIG_CMD_NAND 1
5bb907a4 RM	151	#define CONFIG_NAND_FSL_ELBC 1
5bb907a4 RM	152
bb0f5bc9 JH	153	#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
	154	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
	155	\| BR_PS_8 /* 8 bit Port */ \
	156	\| BR_MS_FCM /* MSEL = FCM */ \
	157	\| BR_V) /* valid */
5bb907a4 RM	158
5bb907a4 RM	159	#ifdef CONFIG_NAND_SP
bb0f5bc9	160	#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
5bb907a4 RM	161	\| OR_FCM_CSCT \
	162	\| OR_FCM_CST \
	163	\| OR_FCM_CHT \
	164	\| OR_FCM_SCY_1 \
	165	\| OR_FCM_TRLX \
bb0f5bc9	166	\| OR_FCM_EHTR)
5bb907a4	167	#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
bb0f5bc9 JH	168	#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
	169	/* NAND chip block size */
	170	#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10)
5bb907a4 RM	171	#define NAND_CACHE_PAGES 32
5bb907a4 RM	172	#elif defined(CONFIG_NAND_LP)
bb0f5bc9	173	#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
5bb907a4 RM	174	\| OR_FCM_PGS \
	175	\| OR_FCM_CSCT \
	176	\| OR_FCM_CST \
	177	\| OR_FCM_CHT \
	178	\| OR_FCM_SCY_1 \
	179	\| OR_FCM_TRLX \
bb0f5bc9	180	\| OR_FCM_EHTR)
5bb907a4	181	#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
bb0f5bc9 JH	182	#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
	183	/* NAND chip block size */
	184	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
5bb907a4 RM	185	#define NAND_CACHE_PAGES 64
	186	#else
	187	#error Page size of NAND not defined.
	188	#endif /* CONFIG_NAND_SP */
	189
	190	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
	191
	192	#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
	193	#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
	194
	195	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
	196
	197	#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
	198	#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
	199
bb0f5bc9	200	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA_BASE \
3b439792 RM	201	\| BR_PS_16 \
3b439792 RM	202	\| BR_MS_UPMA \
bb0f5bc9 JH	203	\| BR_V)
bb0f5bc9 JH	204	#define CONFIG_SYS_OR1_PRELIM (OR_AM_2MB \
3b439792 RM	205	\| OR_UPM_BCTLD)
	206
	207	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
	208	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_2MB)
	209
5bb907a4 RM	210	/*
	211	* JFFS2 configuration
	212	*/
	213	#define CONFIG_JFFS2_NAND
	214	#define CONFIG_JFFS2_DEV "nand0"
	215
	216	/* mtdparts command line support */
68d7d651	217	#define CONFIG_CMD_MTDPARTS
bb0f5bc9	218	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
5bb907a4 RM	219	#define MTDIDS_DEFAULT "nand0=nand0"
	220	#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
	221
	222	/* pass open firmware flat tree */
	223	#define CONFIG_OF_LIBFDT 1
	224	#define CONFIG_OF_BOARD_SETUP 1
	225	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	226
	227	/*
	228	* Serial Port
	229	*/
	230	#define CONFIG_CONS_INDEX 1
	231	#define CONFIG_SYS_NS16550
	232	#define CONFIG_SYS_NS16550_SERIAL
	233	#define CONFIG_SYS_NS16550_REG_SIZE 1
f5675aa5 RM	234	#ifdef CONFIG_NAND_SPL
	235	#define CONFIG_NS16550_MIN_FUNCTIONS
	236	#endif
5bb907a4 RM	237
5bb907a4 RM	238	#define CONFIG_SYS_BAUDRATE_TABLE \
bb0f5bc9	239	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
5bb907a4 RM	240
	241	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
	242	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
	243
	244	/* Use the HUSH parser */
	245	#define CONFIG_SYS_HUSH_PARSER
	246	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	247
	248	/* I2C */
bb0f5bc9	249	#define CONFIG_HARD_I2C /* I2C with hardware support*/
5bb907a4 RM	250	#define CONFIG_FSL_I2C
5bb907a4 RM	251	#define CONFIG_I2C_MULTI_BUS
bb0f5bc9 JH	252	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	253	#define CONFIG_SYS_I2C_SLAVE 0x7F
	254	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
	255	#define CONFIG_SYS_I2C_OFFSET 0x3000
	256	#define CONFIG_SYS_I2C2_OFFSET 0x3100
5bb907a4 RM	257
	258	/*
	259	* General PCI
	260	* Addresses are mapped 1-1.
	261	*/
	262	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	263	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	264	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	265	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	266	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	267	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	268	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	269	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	270	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
	271
	272	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	273	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
	274
	275	/*
	276	* TSEC
	277	*/
	278	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
	279
5bb907a4 RM	280	#define CONFIG_GMII /* MII PHY management */
	281
	282	#ifdef CONFIG_TSEC1
	283	#define CONFIG_HAS_ETH0
	284	#define CONFIG_TSEC1_NAME "TSEC0"
	285	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	286	#define TSEC1_PHY_ADDR 0x0
	287	#define TSEC1_FLAGS TSEC_GIGABIT
	288	#define TSEC1_PHYIDX 0
	289	#endif
	290
	291	#ifdef CONFIG_TSEC2
	292	#define CONFIG_HAS_ETH1
	293	#define CONFIG_TSEC2_NAME "TSEC1"
	294	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	295	#define TSEC2_PHY_ADDR 4
	296	#define TSEC2_FLAGS TSEC_GIGABIT
	297	#define TSEC2_PHYIDX 0
	298	#endif
	299
	300
	301	/* Options are: TSEC[0-1] */
	302	#define CONFIG_ETHPRIME "TSEC1"
	303
	304	/*
	305	* Configure on-board RTC
	306	*/
	307	#define CONFIG_RTC_DS1337
	308	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	309
	310	/*
	311	* Environment
	312	*/
	313	#if defined(CONFIG_NAND_U_BOOT)
bb0f5bc9 JH	314	#define CONFIG_ENV_IS_IN_NAND 1
	315	#define CONFIG_ENV_OFFSET (768 * 1024)
	316	#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
	317	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	318	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	319	#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
	320	#define CONFIG_ENV_OFFSET_REDUND \
	321	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
5bb907a4	322	#elif !defined(CONFIG_SYS_RAMBOOT)
bb0f5bc9 JH	323	#define CONFIG_ENV_IS_IN_FLASH 1
	324	#define CONFIG_ENV_ADDR \
	325	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	326	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
	327	#define CONFIG_ENV_SIZE 0x2000
5bb907a4 RM	328
	329	/* Address and size of Redundant Environment Sector */
	330	#else
bb0f5bc9 JH	331	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	332	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
	333	#define CONFIG_ENV_SIZE 0x2000
5bb907a4 RM	334	#endif
5bb907a4 RM	335
bb0f5bc9 JH	336	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
bb0f5bc9 JH	337	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
5bb907a4 RM	338
	339	/*
	340	* BOOTP options
	341	*/
	342	#define CONFIG_BOOTP_BOOTFILESIZE
	343	#define CONFIG_BOOTP_BOOTPATH
	344	#define CONFIG_BOOTP_GATEWAY
	345	#define CONFIG_BOOTP_HOSTNAME
	346
	347
	348	/*
	349	* Command line configuration.
	350	*/
	351	#include <config_cmd_default.h>
	352	#undef CONFIG_CMD_IMLS
	353	#undef CONFIG_CMD_FLASH
	354
	355	#define CONFIG_CMD_PING
	356	#define CONFIG_CMD_DHCP
	357	#define CONFIG_CMD_I2C
	358	#define CONFIG_CMD_MII
	359	#define CONFIG_CMD_DATE
	360	#define CONFIG_CMD_PCI
	361	#define CONFIG_CMD_JFFS2
	362
	363	#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
bdab39d3	364	#undef CONFIG_CMD_SAVEENV
5bb907a4 RM	365	#undef CONFIG_CMD_LOADS
	366	#endif
	367
bb0f5bc9 JH	368	#define CONFIG_CMDLINE_EDITING 1
bb0f5bc9 JH	369	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
5bb907a4 RM	370
	371	/*
	372	* Miscellaneous configurable options
	373	*/
bb0f5bc9 JH	374	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	375	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
	376	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	377	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	378
	379	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
	380	+ sizeof(CONFIG_SYS_PROMPT) \
	381	+ 16) /* Print Buffer Size */
	382	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	383	/* Boot Argument Buffer Size */
	384	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	385	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
5bb907a4 RM	386
	387	/*
	388	* For booting Linux, the board info and command line data
9f530d59	389	* have to be in the first 256 MB of memory, since this is
5bb907a4 RM	390	* the maximum mapped by the Linux kernel during initialization.
5bb907a4 RM	391	*/
bb0f5bc9 JH	392	/* Initial Memory map for Linux*/
bb0f5bc9 JH	393	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
5bb907a4	394
bb0f5bc9	395	#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
5bb907a4	396
bb0f5bc9 JH	397	#define CONFIG_SYS_HRCW_LOW (HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
	398	\| 0x20000000 /* reserved */ \
	399	\| HRCWL_DDR_TO_SCB_CLK_2X1 \
	400	\| HRCWL_CSB_TO_CLKIN_4X1 \
	401	\| HRCWL_CORE_TO_CSB_2_5X1)
5bb907a4	402
bb0f5bc9	403	#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
5bb907a4	404
bb0f5bc9 JH	405	#define CONFIG_SYS_HRCW_HIGH_BASE (HRCWH_PCI_HOST \
	406	\| HRCWH_PCI1_ARBITER_ENABLE \
	407	\| HRCWH_CORE_ENABLE \
	408	\| HRCWH_BOOTSEQ_DISABLE \
	409	\| HRCWH_SW_WATCHDOG_DISABLE \
	410	\| HRCWH_TSEC1M_IN_RGMII \
	411	\| HRCWH_TSEC2M_IN_RGMII \
	412	\| HRCWH_BIG_ENDIAN \
	413	\| HRCWH_LALE_NORMAL)
5bb907a4 RM	414
5bb907a4 RM	415	#ifdef CONFIG_NAND_LP
bb0f5bc9 JH	416	#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
	417	\| HRCWH_FROM_0XFFF00100 \
	418	\| HRCWH_ROM_LOC_NAND_LP_8BIT \
5bb907a4 RM	419	\| HRCWH_RL_EXT_NAND)
5bb907a4 RM	420	#else
bb0f5bc9 JH	421	#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
	422	\| HRCWH_FROM_0XFFF00100 \
	423	\| HRCWH_ROM_LOC_NAND_SP_8BIT \
	424	\| HRCWH_RL_EXT_NAND)
5bb907a4 RM	425	#endif
	426
	427	/* System IO Config */
bb0f5bc9	428	#define CONFIG_SYS_SICRH (SICRH_ETSEC2_B \
5bb907a4 RM	429	\| SICRH_ETSEC2_C \
	430	\| SICRH_ETSEC2_D \
	431	\| SICRH_ETSEC2_E \
	432	\| SICRH_ETSEC2_F \
	433	\| SICRH_ETSEC2_G \
	434	\| SICRH_TSOBI1 \
bb0f5bc9 JH	435	\| SICRH_TSOBI2)
bb0f5bc9 JH	436	#define CONFIG_SYS_SICRL (SICRL_LBC \
f986325d	437	\| SICRL_USBDR_10 \
bb0f5bc9	438	\| SICRL_ETSEC2_A)
5bb907a4 RM	439
5bb907a4 RM	440	#define CONFIG_SYS_HID0_INIT 0x000000000
bb0f5bc9 JH	441	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
	442	\| HID0_ENABLE_INSTRUCTION_CACHE \
	443	\| HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
5bb907a4 RM	444
	445	#define CONFIG_SYS_HID2 HID2_HBE
	446
	447	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
	448
	449	/* DDR @ 0x00000000 */
	450	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10)
bb0f5bc9 JH	451	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	452	\| BATU_BL_256M \
	453	\| BATU_VS \
	454	\| BATU_VP)
	455	#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
	456	\| BATL_PP_10)
	457	#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
	458	\| BATU_BL_256M \
	459	\| BATU_VS \
	460	\| BATU_VP)
5bb907a4 RM	461
	462	/* PCI @ 0x80000000 */
	463	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE \| BATL_PP_10)
bb0f5bc9 JH	464	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \
	465	\| BATU_BL_256M \
	466	\| BATU_VS \
	467	\| BATU_VP)
	468	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \
	469	\| BATL_PP_10 \
	470	\| BATL_CACHEINHIBIT \
	471	\| BATL_GUARDEDSTORAGE)
	472	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \
	473	\| BATU_BL_256M \
	474	\| BATU_VS \
	475	\| BATU_VP)
5bb907a4 RM	476
	477	/* PCI2 not supported on 8313 */
	478	#define CONFIG_SYS_IBAT4L (0)
	479	#define CONFIG_SYS_IBAT4U (0)
	480
	481	/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
bb0f5bc9 JH	482	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
	483	\| BATL_PP_10 \
	484	\| BATL_CACHEINHIBIT \
	485	\| BATL_GUARDEDSTORAGE)
	486	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
	487	\| BATU_BL_256M \
	488	\| BATU_VS \
	489	\| BATU_VP)
5bb907a4 RM	490
5bb907a4 RM	491	/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
bb0f5bc9 JH	492	#define CONFIG_SYS_IBAT6L (0xF0000000 \
	493	\| BATL_PP_10 \
	494	\| BATL_GUARDEDSTORAGE)
	495	#define CONFIG_SYS_IBAT6U (0xF0000000 \
	496	\| BATU_BL_256M \
	497	\| BATU_VS \
	498	\| BATU_VP)
5bb907a4 RM	499
	500	#define CONFIG_SYS_IBAT7L (0)
	501	#define CONFIG_SYS_IBAT7U (0)
	502
	503	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	504	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	505	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	506	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	507	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	508	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	509	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	510	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	511	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	512	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	513	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	514	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	515	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	516	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	517	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	518	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
	519
5bb907a4 RM	520	/*
	521	* Environment Configuration
	522	*/
	523	#define CONFIG_ENV_OVERWRITE
	524
bb0f5bc9	525	#define CONFIG_NETDEV "eth1"
5bb907a4 RM	526
5bb907a4 RM	527	#define CONFIG_HOSTNAME simpc8313
8b3637c6	528	#define CONFIG_ROOTPATH "/tftpboot/"
b3f44c21	529	#define CONFIG_BOOTFILE "/tftpboot/uImage"
bb0f5bc9 JH	530	/* U-Boot image on TFTP server */
	531	#define CONFIG_UBOOTPATH "u-boot-nand.bin"
	532	#define CONFIG_FDTFILE "simpc8313.dtb"
5bb907a4	533
bb0f5bc9 JH	534	/* default location for tftp and bootm */
bb0f5bc9 JH	535	#define CONFIG_LOADADDR 500000
5bb907a4 RM	536	#define CONFIG_BOOTDELAY 5 /* 5 second delay */
	537	#define CONFIG_BAUDRATE 115200
	538
bb0f5bc9 JH	539	#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;" \
bb0f5bc9 JH	540	"bootm $loadaddr - $fdtaddr"
5bb907a4 RM	541
	542	#define XMK_STR(x) #x
	543	#define MK_STR(x) XMK_STR(x)
	544
	545	#define CONFIG_EXTRA_ENV_SETTINGS \
bb0f5bc9	546	"netdev=" CONFIG_NETDEV "\0" \
5bb907a4	547	"ethprime=TSEC1\0" \
bb0f5bc9	548	"uboot=" CONFIG_UBOOTPATH "\0" \
5bb907a4	549	"tftpflash=tftpboot $loadaddr $uboot; " \
bb0f5bc9 JH	550	"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	551	"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	552	"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
	553	"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	554	"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
5bb907a4	555	"fdtaddr=ae0000\0" \
bb0f5bc9	556	"fdtfile=" CONFIG_FDTFILE "\0" \
5bb907a4 RM	557	"console=ttyS0\0" \
	558	"setbootargs=setenv bootargs " \
	559	"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
bb0f5bc9 JH	560	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
	561	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	562	"$netdev:off " \
	563	"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
5bb907a4 RM	564	"load_uboot=tftp 100000 u-boot-nand.bin\0" \
	565	"burn_uboot=nand erase u-boot 80000; " \
	566	"nand write 100000 u-boot $filesize\0" \
	567	"update_uboot=run load_uboot;run burn_uboot\0" \
	568	"mtdids=nand0=nand0\0" \
	569	"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
	570	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	571	"nfsroot=${serverip}:${rootpath}\0" \
	572	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	573	"addip=setenv bootargs ${bootargs} " \
	574	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	575	":${hostname}:${netdev}:off panic=1\0" \
bb0f5bc9	576	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
5bb907a4 RM	577	"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
	578	"console=ttyS0,115200\0" \
	579	""
	580
	581	#define CONFIG_NFSBOOTCOMMAND \
	582	"setenv rootdev /dev/nfs;" \
	583	"run setbootargs;" \
	584	"run setipargs;" \
	585	"tftp $loadaddr $bootfile;" \
	586	"tftp $fdtaddr $fdtfile;" \
	587	"bootm $loadaddr - $fdtaddr"
	588
	589	#define CONFIG_RAMBOOTCOMMAND \
	590	"setenv rootdev /dev/ram;" \
	591	"run setbootargs;" \
	592	"tftp $ramdiskaddr $ramdiskfile;" \
	593	"tftp $loadaddr $bootfile;" \
	594	"tftp $fdtaddr $fdtfile;" \
	595	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	596
	597	#undef MK_STR
	598	#undef XMK_STR
	599
	600	#endif /* __CONFIG_H */