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0f8c9768 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ | |
37 | #define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */ | |
38 | ||
39 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
40 | #undef CONFIG_8xx_CONS_SMC2 | |
41 | #undef CONFIG_8xx_CONS_NONE | |
42 | #define CONFIG_BAUDRATE 115200 | |
43 | #if 0 | |
44 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
45 | #else | |
46 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
47 | #endif | |
48 | ||
49 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
50 | ||
51 | #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ | |
52 | ||
53 | #define CONFIG_BOOTARGS "root=/dev/nfs rw " \ | |
54 | "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ | |
55 | "nfsaddrs=10.0.0.99:10.0.0.2" | |
56 | ||
57 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 58 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
0f8c9768 WD |
59 | |
60 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
61 | ||
fe7f782d JL |
62 | |
63 | /* | |
64 | * Command line configuration. | |
65 | */ | |
66 | #include <config_cmd_default.h> | |
67 | ||
68 | #define CONFIG_CMD_IDE | |
69 | ||
70 | #undef CONFIG_CMD_FLASH | |
71 | ||
72 | ||
0f8c9768 WD |
73 | #define CONFIG_MAC_PARTITION |
74 | #define CONFIG_DOS_PARTITION | |
75 | ||
18225e8d JL |
76 | /* |
77 | * BOOTP options | |
78 | */ | |
79 | #define CONFIG_BOOTP_SUBNETMASK | |
80 | #define CONFIG_BOOTP_GATEWAY | |
81 | #define CONFIG_BOOTP_HOSTNAME | |
82 | #define CONFIG_BOOTP_BOOTPATH | |
83 | #define CONFIG_BOOTP_BOOTFILESIZE | |
84 | ||
0f8c9768 | 85 | |
0f8c9768 WD |
86 | /*----------------------------------------------------------------------*/ |
87 | #define CONFIG_ETHADDR 00:D0:93:00:01:CB | |
88 | #define CONFIG_IPADDR 10.0.0.98 | |
89 | #define CONFIG_SERVERIP 10.0.0.1 | |
90 | #undef CONFIG_BOOTCOMMAND | |
3bac3513 | 91 | #define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000" |
0f8c9768 WD |
92 | /*----------------------------------------------------------------------*/ |
93 | ||
94 | /* | |
95 | * Miscellaneous configurable options | |
96 | */ | |
6d0f6bcf JCPV |
97 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
98 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
fe7f782d | 99 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 100 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0f8c9768 | 101 | #else |
6d0f6bcf | 102 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0f8c9768 | 103 | #endif |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
105 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
106 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0f8c9768 | 107 | |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
109 | #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ | |
0f8c9768 | 110 | |
6d0f6bcf | 111 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
0f8c9768 | 112 | |
6d0f6bcf | 113 | #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
0f8c9768 | 114 | |
6d0f6bcf | 115 | #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ |
0f8c9768 | 116 | |
6d0f6bcf | 117 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
0f8c9768 | 118 | |
6d0f6bcf | 119 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
0f8c9768 WD |
120 | |
121 | /* | |
122 | * Low Level Configuration Settings | |
123 | * (address mappings, register initial values, etc.) | |
124 | * You should know what you are doing if you make changes here. | |
125 | */ | |
126 | /*----------------------------------------------------------------------- | |
127 | * Internal Memory Mapped Register | |
128 | */ | |
6d0f6bcf | 129 | #define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */ |
0f8c9768 WD |
130 | |
131 | /*----------------------------------------------------------------------- | |
132 | * Definitions for initial stack pointer and data area (in DPRAM) | |
133 | */ | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
135 | #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
136 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
137 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
138 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
0f8c9768 WD |
139 | |
140 | /*----------------------------------------------------------------------- | |
141 | * Start addresses for the final memory configuration | |
142 | * (Set up by the startup code) | |
6d0f6bcf | 143 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
0f8c9768 | 144 | */ |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
146 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
0f8c9768 | 147 | #ifdef DEBUG |
6d0f6bcf | 148 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
0f8c9768 | 149 | #else |
6d0f6bcf | 150 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
0f8c9768 | 151 | #endif |
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
153 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
0f8c9768 WD |
154 | |
155 | /* | |
156 | * For booting Linux, the board info and command line data | |
157 | * have to be in the first 8 MB of memory, since this is | |
158 | * the maximum mapped by the Linux kernel during initialization. | |
159 | */ | |
6d0f6bcf | 160 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
0f8c9768 WD |
161 | /*----------------------------------------------------------------------- |
162 | * FLASH organization | |
163 | */ | |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_MAX_FLASH_BANKS 0 /* max number of memory banks */ |
165 | #define CONFIG_SYS_MAX_FLASH_SECT 0 /* max number of sectors on one chip */ | |
0f8c9768 | 166 | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */ |
168 | #define CONFIG_SYS_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */ | |
0f8c9768 | 169 | |
5a1aceb0 | 170 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
171 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
172 | #define CONFIG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */ | |
0f8c9768 WD |
173 | /*----------------------------------------------------------------------- |
174 | * Cache Configuration | |
175 | */ | |
6d0f6bcf | 176 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
fe7f782d | 177 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 178 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
0f8c9768 WD |
179 | #endif |
180 | ||
181 | /*----------------------------------------------------------------------- | |
182 | * SYPCR - System Protection Control 11-9 | |
183 | * SYPCR can only be written once after reset! | |
184 | *----------------------------------------------------------------------- | |
185 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
186 | */ | |
187 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 188 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
0f8c9768 WD |
189 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
190 | #else | |
6d0f6bcf | 191 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
0f8c9768 WD |
192 | #endif |
193 | ||
194 | /*----------------------------------------------------------------------- | |
195 | * SIUMCR - SIU Module Configuration 11-6 | |
196 | *----------------------------------------------------------------------- | |
197 | * PCMCIA config., multi-function pin tri-state | |
198 | */ | |
199 | /* 0x00000040 */ | |
6d0f6bcf | 200 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E) |
0f8c9768 WD |
201 | |
202 | /*----------------------------------------------------------------------- | |
203 | * TBSCR - Time Base Status and Control 11-26 | |
204 | *----------------------------------------------------------------------- | |
205 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
206 | */ | |
6d0f6bcf | 207 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
0f8c9768 WD |
208 | |
209 | /*----------------------------------------------------------------------- | |
210 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
211 | *----------------------------------------------------------------------- | |
212 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
213 | */ | |
6d0f6bcf | 214 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
0f8c9768 WD |
215 | |
216 | /*----------------------------------------------------------------------- | |
217 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
218 | *----------------------------------------------------------------------- | |
219 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
220 | * interrupt status bit, set PLL multiplication factor ! | |
221 | */ | |
222 | /* 0x00b0c0c0 */ | |
6d0f6bcf | 223 | #define CONFIG_SYS_PLPRCR \ |
0f8c9768 WD |
224 | ( (11 << PLPRCR_MF_SHIFT) | \ |
225 | PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ | |
226 | /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ | |
227 | PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ | |
228 | ) | |
229 | ||
230 | /*----------------------------------------------------------------------- | |
231 | * SCCR - System Clock and reset Control Register 15-27 | |
232 | *----------------------------------------------------------------------- | |
233 | * Set clock output, timebase and RTC source and divider, | |
234 | * power management and some other internal clocks | |
235 | */ | |
236 | #define SCCR_MASK SCCR_EBDF11 | |
237 | /* 0x01800014 */ | |
6d0f6bcf | 238 | #define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ |
0f8c9768 WD |
239 | SCCR_RTDIV | SCCR_RTSEL | \ |
240 | /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ | |
241 | SCCR_EBDF00 | SCCR_DFSYNC00 | \ | |
242 | SCCR_DFBRG00 | SCCR_DFNL000 | \ | |
243 | SCCR_DFNH000 | SCCR_DFLCD101 | \ | |
244 | SCCR_DFALCD00) | |
245 | ||
246 | /*----------------------------------------------------------------------- | |
247 | * RTCSC - Real-Time Clock Status and Control Register | |
248 | *----------------------------------------------------------------------- | |
249 | */ | |
250 | /* 0x00C3 */ | |
6d0f6bcf | 251 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
0f8c9768 WD |
252 | |
253 | ||
254 | /*----------------------------------------------------------------------- | |
255 | * RCCR - RISC Controller Configuration Register | |
256 | *----------------------------------------------------------------------- | |
257 | */ | |
258 | /* TIMEP=2 */ | |
6d0f6bcf | 259 | #define CONFIG_SYS_RCCR 0x0200 |
0f8c9768 WD |
260 | |
261 | /*----------------------------------------------------------------------- | |
262 | * RMDS - RISC Microcode Development Support Control Register | |
263 | *----------------------------------------------------------------------- | |
264 | */ | |
6d0f6bcf | 265 | #define CONFIG_SYS_RMDS 0 |
0f8c9768 WD |
266 | |
267 | /*----------------------------------------------------------------------- | |
268 | * SDSR - SDMA Status Register | |
269 | *----------------------------------------------------------------------- | |
270 | */ | |
6d0f6bcf | 271 | #define CONFIG_SYS_SDSR ((u_char)0x83) |
0f8c9768 WD |
272 | |
273 | /*----------------------------------------------------------------------- | |
274 | * SDMR - SDMA Mask Register | |
275 | *----------------------------------------------------------------------- | |
276 | */ | |
6d0f6bcf | 277 | #define CONFIG_SYS_SDMR ((u_char)0x00) |
0f8c9768 WD |
278 | |
279 | /*----------------------------------------------------------------------- | |
280 | * | |
281 | * Interrupt Levels | |
282 | *----------------------------------------------------------------------- | |
283 | */ | |
6d0f6bcf | 284 | #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ |
0f8c9768 WD |
285 | |
286 | /*----------------------------------------------------------------------- | |
287 | * PCMCIA stuff | |
288 | *----------------------------------------------------------------------- | |
289 | * | |
290 | */ | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
292 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
293 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
294 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
295 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
296 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
297 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
298 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
0f8c9768 WD |
299 | |
300 | /*----------------------------------------------------------------------- | |
301 | * IDE/ATA stuff | |
302 | *----------------------------------------------------------------------- | |
303 | */ | |
304 | #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ | |
305 | #define CONFIG_IDE_LED 1 /* LED for ide supported */ | |
306 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ | |
307 | ||
6d0f6bcf JCPV |
308 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
309 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ | |
0f8c9768 | 310 | |
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000 |
312 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
313 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 | |
0f8c9768 | 314 | |
6d0f6bcf JCPV |
315 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
316 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ | |
317 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ | |
0f8c9768 WD |
318 | |
319 | /*----------------------------------------------------------------------- | |
320 | * | |
321 | *----------------------------------------------------------------------- | |
322 | * | |
323 | */ | |
6d0f6bcf | 324 | #define CONFIG_SYS_DER 0 |
0f8c9768 WD |
325 | |
326 | /* | |
327 | * Init Memory Controller: | |
328 | * | |
329 | * BR0/1 and OR0/1 (FLASH) | |
330 | */ | |
331 | ||
332 | #define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ | |
333 | #define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */ | |
334 | ||
335 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
336 | * restrict access enough to keep SRAM working (if any) | |
337 | * but not too much to meddle with FLASH accesses | |
338 | */ | |
339 | /* EPROMs are 512kb */ | |
6d0f6bcf JCPV |
340 | #define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ |
341 | #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ | |
0f8c9768 WD |
342 | |
343 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
6d0f6bcf | 344 | #define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ |
0f8c9768 WD |
345 | OR_SCY_5_CLK | OR_EHTR) |
346 | ||
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
348 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
0f8c9768 | 349 | /* 16 bit, bank valid */ |
6d0f6bcf | 350 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
0f8c9768 | 351 | |
6d0f6bcf JCPV |
352 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
353 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
0f8c9768 | 354 | /* 16 bit, bank valid */ |
6d0f6bcf | 355 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
0f8c9768 WD |
356 | |
357 | /* | |
358 | * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC) | |
359 | * | |
360 | */ | |
361 | #define SRAM_BASE 0xFE200000 /* SRAM bank */ | |
362 | #define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */ | |
363 | ||
364 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ | |
365 | #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ | |
366 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ | |
367 | ||
368 | #define PER8_BASE 0xFE000000 /* PER8 bank */ | |
369 | #define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */ | |
370 | ||
371 | #define SHARC_BASE 0xFE400000 /* SHARC bank */ | |
372 | #define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */ | |
373 | ||
374 | /* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
375 | ||
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */ |
377 | #define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM ) | |
378 | #define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) | |
0f8c9768 WD |
379 | |
380 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
381 | ||
6d0f6bcf JCPV |
382 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */ |
383 | #define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) | |
384 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) | |
0f8c9768 | 385 | |
6d0f6bcf JCPV |
386 | #define CONFIG_SYS_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */ |
387 | #define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 ) | |
388 | #define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
0f8c9768 | 389 | |
6d0f6bcf JCPV |
390 | #define CONFIG_SYS_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */ |
391 | #define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC ) | |
392 | #define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) | |
0f8c9768 WD |
393 | /* |
394 | * Memory Periodic Timer Prescaler | |
395 | */ | |
396 | ||
397 | /* periodic timer for refresh */ | |
6d0f6bcf | 398 | #define CONFIG_SYS_MBMR_PTB 204 |
0f8c9768 WD |
399 | |
400 | /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ | |
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
402 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
0f8c9768 WD |
403 | |
404 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
406 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
0f8c9768 WD |
407 | |
408 | /* | |
409 | * MBMR settings for SDRAM | |
410 | */ | |
411 | ||
412 | /* 8 column SDRAM */ | |
6d0f6bcf | 413 | #define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ |
2535d602 WD |
414 | MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ |
415 | MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) | |
0f8c9768 WD |
416 | |
417 | /* | |
418 | * Internal Definitions | |
419 | * | |
420 | * Boot Flags | |
421 | */ | |
422 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
423 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
424 | ||
425 | #endif /* __CONFIG_H */ |