[people/ms/u-boot.git] / include / configs / SPD823TS.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
#define CONFIG_SPD823TS		1	/* ...on a SPD823TS board	*/

#define	CONFIG_SYS_TEXT_BASE	0xFF000000

#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/

#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
				"nfsaddrs=10.0.0.99:10.0.0.2"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_IDE

#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FLASH


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*----------------------------------------------------------------------*/
#define CONFIG_ETHADDR		00:D0:93:00:01:CB
#define CONFIG_IPADDR		10.0.0.98
#define CONFIG_SERVERIP		10.0.0.1
#undef	CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND	"tftp 200000 uImage;bootm 200000"
/*----------------------------------------------------------------------*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */

#define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/

#define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0008)	/* PC 12	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000 /* was: 0xFF000000 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#ifdef	DEBUG
#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
#else
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	0	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	0	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	0	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	0	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x0800	/* Total Size of Environment Sector	*/
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
/* 0x00000040 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit, set PLL multiplication factor !
 */
/* 0x00b0c0c0 */
#define CONFIG_SYS_PLPRCR							\
		(	(11 << PLPRCR_MF_SHIFT) |			\
			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
		)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
/* 0x01800014 */
#define CONFIG_SYS_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register
 *-----------------------------------------------------------------------
 */
/* 0x00C3 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)


/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration Register
 *-----------------------------------------------------------------------
 */
/* TIMEP=2 */
#define CONFIG_SYS_RCCR 0x0200

/*-----------------------------------------------------------------------
 * RMDS - RISC Microcode Development Support Control Register
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RMDS 0

/*-----------------------------------------------------------------------
 * SDSR - SDMA Status Register
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SDSR ((u_char)0x83)

/*-----------------------------------------------------------------------
 * SDMR - SDMA Mask Register
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SDMR ((u_char)0x00)

/*-----------------------------------------------------------------------
 *
 * Interrupt Levels
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define CONFIG_IDE_INIT_POSTRESET	1	/* Use postreset IDE hook */
#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
#define CONFIG_IDE_LED		1	/* LED   for ide supported	*/
#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/

#define CONFIG_SYS_IDE_MAXBUS		2	/* max. 2 IDE busses		*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR	0xFE100000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0C00

#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFF080000	/* FLASH bank #1	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
/* EPROMs are 512kb */
#define CONFIG_SYS_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
#define CONFIG_SYS_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
				 OR_SCY_5_CLK | OR_EHTR)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
/* 16 bit, bank valid */
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )

#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
/* 16 bit, bank valid */
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )

/*
 * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
 *
 */
#define SRAM_BASE	0xFE200000	/* SRAM bank */
#define SRAM_OR_AM	0xFFE00000	/* SRAM is 2 MB */

#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */

#define PER8_BASE	0xFE000000	/* PER8 bank */
#define PER8_OR_AM	0xFFF00000	/* PER8 is 1 MB */

#define SHARC_BASE	0xFE400000	/* SHARC bank */
#define SHARC_OR_AM	0xFFC00000	/* SHARC is 4 MB */

/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/

#define CONFIG_SYS_OR_TIMING_SRAM	0x00000D42	/* SRAM-Timing */
#define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM )
#define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/

#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00	/* SDRAM-Timing */
#define CONFIG_SYS_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )

#define CONFIG_SYS_OR_TIMING_PER8	0x00000F32	/* PER8-Timing */
#define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 )
#define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )

#define CONFIG_SYS_OR_TIMING_SHARC	0x00000700	/* SHARC-Timing */
#define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC )
#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MBMR_PTB	204

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MBMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
	37	#define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */
	38
2ae18241 WD	39	#define CONFIG_SYS_TEXT_BASE 0xFF000000
2ae18241 WD	40
004eca0c PT	41	#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
004eca0c PT	42
0f8c9768 WD	43	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	44	#undef CONFIG_8xx_CONS_SMC2
	45	#undef CONFIG_8xx_CONS_NONE
	46	#define CONFIG_BAUDRATE 115200
	47	#if 0
	48	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	49	#else
	50	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	51	#endif
	52
	53	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	54
	55	#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
	56
	57	#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
	58	"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
	59	"nfsaddrs=10.0.0.99:10.0.0.2"
	60
	61	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	62	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
0f8c9768 WD	63
	64	#undef CONFIG_WATCHDOG /* watchdog disabled */
	65
fe7f782d JL	66
	67	/*
	68	* Command line configuration.
	69	*/
	70	#include <config_cmd_default.h>
	71
	72	#define CONFIG_CMD_IDE
	73
bdab39d3	74	#undef CONFIG_CMD_SAVEENV
fe7f782d JL	75	#undef CONFIG_CMD_FLASH
	76
	77
0f8c9768 WD	78	#define CONFIG_MAC_PARTITION
	79	#define CONFIG_DOS_PARTITION
	80
18225e8d JL	81	/*
	82	* BOOTP options
	83	*/
	84	#define CONFIG_BOOTP_SUBNETMASK
	85	#define CONFIG_BOOTP_GATEWAY
	86	#define CONFIG_BOOTP_HOSTNAME
	87	#define CONFIG_BOOTP_BOOTPATH
	88	#define CONFIG_BOOTP_BOOTFILESIZE
	89
0f8c9768	90
0f8c9768 WD	91	/----------------------------------------------------------------------/
	92	#define CONFIG_ETHADDR 00:D0:93:00:01:CB
	93	#define CONFIG_IPADDR 10.0.0.98
	94	#define CONFIG_SERVERIP 10.0.0.1
	95	#undef CONFIG_BOOTCOMMAND
3bac3513	96	#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000"
0f8c9768 WD	97	/----------------------------------------------------------------------/
	98
	99	/*
	100	* Miscellaneous configurable options
	101	*/
6d0f6bcf JCPV	102	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	103	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
fe7f782d	104	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	105	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0f8c9768	106	#else
6d0f6bcf	107	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0f8c9768	108	#endif
6d0f6bcf JCPV	109	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	110	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	111	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0f8c9768	112
6d0f6bcf JCPV	113	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	114	#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
0f8c9768	115
6d0f6bcf	116	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
0f8c9768	117
6d0f6bcf	118	#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
0f8c9768	119
6d0f6bcf	120	#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */
0f8c9768	121
6d0f6bcf	122	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
0f8c9768	123
0f8c9768 WD	124	/*
	125	* Low Level Configuration Settings
	126	* (address mappings, register initial values, etc.)
	127	* You should know what you are doing if you make changes here.
	128	*/
	129	/*-----------------------------------------------------------------------
	130	* Internal Memory Mapped Register
	131	*/
6d0f6bcf	132	#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
0f8c9768 WD	133
	134	/*-----------------------------------------------------------------------
	135	* Definitions for initial stack pointer and data area (in DPRAM)
	136	*/
6d0f6bcf	137	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	138	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	139	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	140	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0f8c9768 WD	141
	142	/*-----------------------------------------------------------------------
	143	* Start addresses for the final memory configuration
	144	* (Set up by the startup code)
6d0f6bcf	145	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0f8c9768	146	*/
6d0f6bcf JCPV	147	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	148	#define CONFIG_SYS_FLASH_BASE 0xFF000000
0f8c9768	149	#ifdef DEBUG
6d0f6bcf	150	#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
0f8c9768	151	#else
6d0f6bcf	152	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
0f8c9768	153	#endif
6d0f6bcf JCPV	154	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	155	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
0f8c9768 WD	156
	157	/*
	158	* For booting Linux, the board info and command line data
	159	* have to be in the first 8 MB of memory, since this is
	160	* the maximum mapped by the Linux kernel during initialization.
	161	*/
6d0f6bcf	162	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0f8c9768 WD	163	/*-----------------------------------------------------------------------
	164	* FLASH organization
	165	*/
6d0f6bcf JCPV	166	#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* max number of memory banks */
6d0f6bcf JCPV	167	#define CONFIG_SYS_MAX_FLASH_SECT 0 /* max number of sectors on one chip */
0f8c9768	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	170	#define CONFIG_SYS_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */
0f8c9768	171
5a1aceb0	172	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	173	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	174	#define CONFIG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */
0f8c9768 WD	175	/*-----------------------------------------------------------------------
	176	* Cache Configuration
	177	*/
6d0f6bcf	178	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
fe7f782d	179	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	180	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
0f8c9768 WD	181	#endif
	182
	183	/*-----------------------------------------------------------------------
	184	* SYPCR - System Protection Control 11-9
	185	* SYPCR can only be written once after reset!
	186	*-----------------------------------------------------------------------
	187	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	188	*/
	189	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	190	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
0f8c9768 WD	191	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
0f8c9768 WD	192	#else
6d0f6bcf	193	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
0f8c9768 WD	194	#endif
	195
	196	/*-----------------------------------------------------------------------
	197	* SIUMCR - SIU Module Configuration 11-6
	198	*-----------------------------------------------------------------------
	199	* PCMCIA config., multi-function pin tri-state
	200	*/
	201	/* 0x00000040 */
6d0f6bcf	202	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC00 \| SIUMCR_GB5E)
0f8c9768 WD	203
	204	/*-----------------------------------------------------------------------
	205	* TBSCR - Time Base Status and Control 11-26
	206	*-----------------------------------------------------------------------
	207	* Clear Reference Interrupt Status, Timebase freezing enabled
	208	*/
6d0f6bcf	209	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
0f8c9768 WD	210
	211	/*-----------------------------------------------------------------------
	212	* PISCR - Periodic Interrupt Status and Control 11-31
	213	*-----------------------------------------------------------------------
	214	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	215	*/
6d0f6bcf	216	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
0f8c9768 WD	217
	218	/*-----------------------------------------------------------------------
	219	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	220	*-----------------------------------------------------------------------
	221	* Reset PLL lock status sticky bit, timer expired status bit and timer
	222	* interrupt status bit, set PLL multiplication factor !
	223	*/
	224	/* 0x00b0c0c0 */
6d0f6bcf	225	#define CONFIG_SYS_PLPRCR \
0f8c9768 WD	226	( (11 << PLPRCR_MF_SHIFT) \| \
	227	PLPRCR_SPLSS \| PLPRCR_TEXPS \| /PLPRCR_TMIST\|/ \
	228	/PLPRCR_CSRC\|/ PLPRCR_LPM_NORMAL \| \
	229	PLPRCR_CSR \| PLPRCR_LOLRE /\|PLPRCR_FIOPD/ \
	230	)
	231
	232	/*-----------------------------------------------------------------------
	233	* SCCR - System Clock and reset Control Register 15-27
	234	*-----------------------------------------------------------------------
	235	* Set clock output, timebase and RTC source and divider,
	236	* power management and some other internal clocks
	237	*/
	238	#define SCCR_MASK SCCR_EBDF11
	239	/* 0x01800014 */
6d0f6bcf	240	#define CONFIG_SYS_SCCR (SCCR_COM00 \| /SCCR_TBS\|/ \
0f8c9768 WD	241	SCCR_RTDIV \| SCCR_RTSEL \| \
	242	/SCCR_CRQEN\|/ /SCCR_PRQEN\|/ \
	243	SCCR_EBDF00 \| SCCR_DFSYNC00 \| \
	244	SCCR_DFBRG00 \| SCCR_DFNL000 \| \
	245	SCCR_DFNH000 \| SCCR_DFLCD101 \| \
	246	SCCR_DFALCD00)
	247
	248	/*-----------------------------------------------------------------------
	249	* RTCSC - Real-Time Clock Status and Control Register
	250	*-----------------------------------------------------------------------
	251	*/
	252	/* 0x00C3 */
6d0f6bcf	253	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
0f8c9768 WD	254
	255
	256	/*-----------------------------------------------------------------------
	257	* RCCR - RISC Controller Configuration Register
	258	*-----------------------------------------------------------------------
	259	*/
	260	/* TIMEP=2 */
6d0f6bcf	261	#define CONFIG_SYS_RCCR 0x0200
0f8c9768 WD	262
	263	/*-----------------------------------------------------------------------
	264	* RMDS - RISC Microcode Development Support Control Register
	265	*-----------------------------------------------------------------------
	266	*/
6d0f6bcf	267	#define CONFIG_SYS_RMDS 0
0f8c9768 WD	268
	269	/*-----------------------------------------------------------------------
	270	* SDSR - SDMA Status Register
	271	*-----------------------------------------------------------------------
	272	*/
6d0f6bcf	273	#define CONFIG_SYS_SDSR ((u_char)0x83)
0f8c9768 WD	274
	275	/*-----------------------------------------------------------------------
	276	* SDMR - SDMA Mask Register
	277	*-----------------------------------------------------------------------
	278	*/
6d0f6bcf	279	#define CONFIG_SYS_SDMR ((u_char)0x00)
0f8c9768 WD	280
	281	/*-----------------------------------------------------------------------
	282	*
	283	* Interrupt Levels
	284	*-----------------------------------------------------------------------
	285	*/
6d0f6bcf	286	#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
0f8c9768 WD	287
	288	/*-----------------------------------------------------------------------
	289	* PCMCIA stuff
	290	*-----------------------------------------------------------------------
	291	*
	292	*/
6d0f6bcf JCPV	293	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	294	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	295	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	296	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	297	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	298	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	299	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	300	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
0f8c9768 WD	301
	302	/*-----------------------------------------------------------------------
	303	* IDE/ATA stuff
	304	*-----------------------------------------------------------------------
	305	*/
8d1165e1 PH	306	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
8d1165e1 PH	307	#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
0f8c9768 WD	308	#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
	309	#define CONFIG_IDE_LED 1 /* LED for ide supported */
	310	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
	311
6d0f6bcf JCPV	312	#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
6d0f6bcf JCPV	313	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS2) / max. 2 drives per IDE bus */
0f8c9768	314
6d0f6bcf JCPV	315	#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
	316	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	317	#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00
0f8c9768	318
6d0f6bcf JCPV	319	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	320	#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
	321	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
0f8c9768 WD	322
	323	/*-----------------------------------------------------------------------
	324	*
	325	*-----------------------------------------------------------------------
	326	*
	327	*/
6d0f6bcf	328	#define CONFIG_SYS_DER 0
0f8c9768 WD	329
	330	/*
	331	* Init Memory Controller:
	332	*
	333	* BR0/1 and OR0/1 (FLASH)
	334	*/
	335
	336	#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
	337	#define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */
	338
	339	/* used to re-map FLASH both when starting from SRAM or FLASH:
	340	* restrict access enough to keep SRAM working (if any)
	341	* but not too much to meddle with FLASH accesses
	342	*/
	343	/* EPROMs are 512kb */
6d0f6bcf JCPV	344	#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
6d0f6bcf JCPV	345	#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
0f8c9768 WD	346
0f8c9768 WD	347	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
6d0f6bcf	348	#define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM \| */ OR_ACS_DIV4 \| OR_BI \| \
0f8c9768 WD	349	OR_SCY_5_CLK \| OR_EHTR)
0f8c9768 WD	350
6d0f6bcf JCPV	351	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	352	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
0f8c9768	353	/* 16 bit, bank valid */
6d0f6bcf	354	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
0f8c9768	355
6d0f6bcf JCPV	356	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
6d0f6bcf JCPV	357	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
0f8c9768	358	/* 16 bit, bank valid */
6d0f6bcf	359	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
0f8c9768 WD	360
	361	/*
	362	* BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
	363	*
	364	*/
	365	#define SRAM_BASE 0xFE200000 /* SRAM bank */
	366	#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */
	367
	368	#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
	369	#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
	370	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
	371
	372	#define PER8_BASE 0xFE000000 /* PER8 bank */
	373	#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */
	374
	375	#define SHARC_BASE 0xFE400000 /* SHARC bank */
	376	#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */
	377
	378	/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
	379
6d0f6bcf JCPV	380	#define CONFIG_SYS_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */
	381	#define CONFIG_SYS_OR2 (SRAM_OR_AM \| CONFIG_SYS_OR_TIMING_SRAM )
	382	#define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_V )
0f8c9768 WD	383
	384	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
	385
6d0f6bcf JCPV	386	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */
	387	#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
	388	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMB \| BR_V )
0f8c9768	389
6d0f6bcf JCPV	390	#define CONFIG_SYS_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */
	391	#define CONFIG_SYS_OR4 (PER8_OR_AM \| CONFIG_SYS_OR_TIMING_PER8 )
	392	#define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
0f8c9768	393
6d0f6bcf JCPV	394	#define CONFIG_SYS_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */
	395	#define CONFIG_SYS_OR5 (SHARC_OR_AM \| CONFIG_SYS_OR_TIMING_SHARC )
	396	#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) \| BR_PS_32 \| BR_MS_UPMA \| BR_V )
0f8c9768 WD	397	/*
	398	* Memory Periodic Timer Prescaler
	399	*/
	400
	401	/* periodic timer for refresh */
6d0f6bcf	402	#define CONFIG_SYS_MBMR_PTB 204
0f8c9768 WD	403
0f8c9768 WD	404	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	405	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	406	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
0f8c9768 WD	407
0f8c9768 WD	408	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	409	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	410	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
0f8c9768 WD	411
	412	/*
	413	* MBMR settings for SDRAM
	414	*/
	415
	416	/* 8 column SDRAM */
6d0f6bcf	417	#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) \| \
2535d602 WD	418	MBMR_AMB_TYPE_0 \| MBMR_DSB_1_CYCL \| MBMR_G0CLB_A11 \| \
2535d602 WD	419	MBMR_RLFB_1X \| MBMR_WLFB_1X \| MBMR_TLFB_4X)
0f8c9768	420
0f8c9768	421	#endif /* __CONFIG_H */