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c609719b | 1 | /* |
414eec35 | 2 | * (C) Copyright 2001-2005 |
c609719b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* ------------------------------------------------------------------------- */ | |
25 | ||
26 | /* | |
27 | * board/config.h - configuration options, board specific | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | ||
38 | #define CONFIG_MPC824X 1 | |
39 | #define CONFIG_MPC8240 1 | |
40 | #define CONFIG_SANDPOINT 1 | |
41 | ||
2ae18241 | 42 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
de550d6b | 43 | #define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds" |
2ae18241 | 44 | |
c609719b WD |
45 | #if 0 |
46 | #define USE_DINK32 1 | |
47 | #else | |
48 | #undef USE_DINK32 | |
49 | #endif | |
50 | ||
51 | #define CONFIG_CONS_INDEX 1 | |
149dded2 WD |
52 | #define CONFIG_BAUDRATE 9600 |
53 | ||
54 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
55 | ||
56 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
57 | ||
58 | #define CONFIG_PREBOOT "echo;" \ | |
59 | "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \ | |
60 | "echo" | |
61 | ||
62 | #undef CONFIG_BOOTARGS | |
63 | ||
64 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
65 | "netdev=eth0\0" \ | |
66 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 67 | "nfsroot=${serverip}:${rootpath}\0" \ |
149dded2 | 68 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
69 | "addip=setenv bootargs ${bootargs} " \ |
70 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
71 | ":${hostname}:${netdev}:off panic=1\0" \ | |
72 | "net_self=tftp ${kernel_addr} ${bootfile};" \ | |
73 | "tftp ${ramdisk_addr} ${ramdisk};" \ | |
149dded2 | 74 | "run ramargs addip;" \ |
fe126d8b WD |
75 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
76 | "net_nfs=tftp ${kernel_addr} ${bootfile};" \ | |
149dded2 WD |
77 | "run nfsargs addip;bootm\0" \ |
78 | "rootpath=/opt/eldk/ppc_82xx\0" \ | |
79 | "bootfile=/tftpboot/SP8240/uImage\0" \ | |
80 | "ramdisk=/tftpboot/SP8240/uRamdisk\0" \ | |
81 | "kernel_addr=200000\0" \ | |
82 | "ramdisk_addr=400000\0" \ | |
83 | "" | |
84 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
c609719b | 85 | |
fe7f782d | 86 | |
a1aa0bb5 JL |
87 | /* |
88 | * BOOTP options | |
89 | */ | |
90 | #define CONFIG_BOOTP_BOOTFILESIZE | |
91 | #define CONFIG_BOOTP_BOOTPATH | |
92 | #define CONFIG_BOOTP_GATEWAY | |
93 | #define CONFIG_BOOTP_HOSTNAME | |
94 | ||
95 | ||
fe7f782d JL |
96 | /* |
97 | * Command line configuration. | |
98 | */ | |
99 | #include <config_cmd_default.h> | |
100 | ||
101 | #define CONFIG_CMD_DHCP | |
102 | #define CONFIG_CMD_ELF | |
103 | #define CONFIG_CMD_I2C | |
104 | #define CONFIG_CMD_SDRAM | |
105 | #define CONFIG_CMD_EEPROM | |
106 | #define CONFIG_CMD_NFS | |
107 | #define CONFIG_CMD_PCI | |
108 | #define CONFIG_CMD_SNTP | |
109 | ||
c609719b | 110 | |
149dded2 | 111 | #define CONFIG_DRAM_SPEED 100 /* MHz */ |
c609719b WD |
112 | |
113 | /* | |
114 | * Miscellaneous configurable options | |
115 | */ | |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
117 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
118 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
119 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
120 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
121 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
122 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ | |
123 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
c609719b WD |
124 | |
125 | /*----------------------------------------------------------------------- | |
126 | * PCI stuff | |
127 | *----------------------------------------------------------------------- | |
128 | */ | |
129 | #define CONFIG_PCI /* include pci support */ | |
130 | #undef CONFIG_PCI_PNP | |
131 | ||
132 | #define CONFIG_NET_MULTI /* Multi ethernet cards support */ | |
133 | ||
134 | #define CONFIG_EEPRO100 | |
6d0f6bcf | 135 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
c609719b WD |
136 | |
137 | #define PCI_ENET0_IOADDR 0x80000000 | |
138 | #define PCI_ENET0_MEMADDR 0x80000000 | |
139 | #define PCI_ENET1_IOADDR 0x81000000 | |
140 | #define PCI_ENET1_MEMADDR 0x81000000 | |
141 | ||
142 | ||
143 | /*----------------------------------------------------------------------- | |
144 | * Start addresses for the final memory configuration | |
145 | * (Set up by the startup code) | |
6d0f6bcf | 146 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 147 | */ |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
149 | #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 | |
c609719b | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
c609719b WD |
152 | |
153 | #if defined (USE_DINK32) | |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_MONITOR_LEN 0x00030000 |
155 | #define CONFIG_SYS_MONITOR_BASE 0x00090000 | |
156 | #define CONFIG_SYS_RAMBOOT 1 | |
157 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
553f0982 | 158 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 |
25ddd1fb | 159 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 160 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c609719b | 161 | #else |
6d0f6bcf JCPV |
162 | #undef CONFIG_SYS_RAMBOOT |
163 | #define CONFIG_SYS_MONITOR_LEN 0x00030000 | |
14d0a02a | 164 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
c609719b | 165 | |
c609719b | 166 | |
6d0f6bcf | 167 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
553f0982 | 168 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
25ddd1fb | 169 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
c609719b WD |
170 | |
171 | #endif | |
172 | ||
6d0f6bcf | 173 | #define CONFIG_SYS_FLASH_BASE 0xFFF00000 |
c609719b | 174 | #if 0 |
6d0f6bcf | 175 | #define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ |
c609719b | 176 | #else |
6d0f6bcf | 177 | #define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ |
c609719b | 178 | #endif |
5a1aceb0 | 179 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
180 | #define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ |
181 | #define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ | |
c609719b | 182 | |
6d0f6bcf | 183 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ |
c609719b | 184 | |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
186 | #define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ | |
c609719b | 187 | |
6d0f6bcf | 188 | #define CONFIG_SYS_EUMB_ADDR 0xFC000000 |
c609719b | 189 | |
6d0f6bcf JCPV |
190 | #define CONFIG_SYS_ISA_MEM 0xFD000000 |
191 | #define CONFIG_SYS_ISA_IO 0xFE000000 | |
c609719b | 192 | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ |
194 | #define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 | |
c609719b WD |
195 | #define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ |
196 | #define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ | |
197 | ||
198 | /* | |
199 | * select i2c support configuration | |
200 | * | |
201 | * Supported configurations are {none, software, hardware} drivers. | |
202 | * If the software driver is chosen, there are some additional | |
203 | * configuration items that the driver uses to drive the port pins. | |
204 | */ | |
205 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
206 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
208 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
c609719b WD |
209 | |
210 | #ifdef CONFIG_SOFT_I2C | |
211 | #error "Soft I2C is not configured properly. Please review!" | |
212 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
213 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
214 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
215 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
216 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
217 | else iop->pdat &= ~0x00010000 | |
218 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
219 | else iop->pdat &= ~0x00020000 | |
220 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
221 | #endif /* CONFIG_SOFT_I2C */ | |
222 | ||
223 | ||
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ |
225 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
226 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* write page size */ | |
227 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ | |
c609719b WD |
228 | |
229 | ||
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
231 | #define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } | |
c609719b WD |
232 | |
233 | /*----------------------------------------------------------------------- | |
234 | * Definitions for initial stack pointer and data area (in DPRAM) | |
235 | */ | |
236 | ||
237 | ||
57d6c589 | 238 | /* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ |
240 | #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ | |
241 | #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ | |
c609719b | 242 | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
244 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ | |
c609719b WD |
245 | |
246 | /* | |
247 | * NS87308 Configuration | |
248 | */ | |
55d6d2d3 | 249 | #define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ |
c609719b | 250 | |
6d0f6bcf | 251 | #define CONFIG_SYS_NS87308_BADDR_10 1 |
c609719b | 252 | |
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ |
254 | CONFIG_SYS_NS87308_UART2 | \ | |
255 | CONFIG_SYS_NS87308_POWRMAN | \ | |
256 | CONFIG_SYS_NS87308_RTC_APC ) | |
c609719b | 257 | |
6d0f6bcf | 258 | #undef CONFIG_SYS_NS87308_PS2MOD |
c609719b | 259 | |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_NS87308_CS0_BASE 0x0076 |
261 | #define CONFIG_SYS_NS87308_CS0_CONF 0x30 | |
262 | #define CONFIG_SYS_NS87308_CS1_BASE 0x0075 | |
263 | #define CONFIG_SYS_NS87308_CS1_CONF 0x30 | |
264 | #define CONFIG_SYS_NS87308_CS2_BASE 0x0074 | |
265 | #define CONFIG_SYS_NS87308_CS2_CONF 0x30 | |
c609719b WD |
266 | |
267 | /* | |
268 | * NS16550 Configuration | |
269 | */ | |
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_NS16550 |
271 | #define CONFIG_SYS_NS16550_SERIAL | |
c609719b | 272 | |
6d0f6bcf | 273 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
c609719b | 274 | |
6d0f6bcf | 275 | #define CONFIG_SYS_NS16550_CLK 1843200 |
c609719b | 276 | |
6d0f6bcf JCPV |
277 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) |
278 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) | |
c609719b WD |
279 | |
280 | /* | |
281 | * Low Level Configuration Settings | |
282 | * (address mappings, register initial values, etc.) | |
283 | * You should know what you are doing if you make changes here. | |
284 | */ | |
285 | ||
286 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ | |
7cb22f97 | 287 | #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1 |
c609719b | 288 | |
6d0f6bcf JCPV |
289 | #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ |
290 | #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ | |
c609719b | 291 | |
6d0f6bcf | 292 | #define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ |
c609719b WD |
293 | |
294 | /* the following are for SDRAM only*/ | |
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ |
296 | #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ | |
297 | #define CONFIG_SYS_RDLAT 4 /* data latency from read command */ | |
298 | #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ | |
299 | #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ | |
300 | #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ | |
301 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ | |
302 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ | |
303 | #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ | |
304 | ||
305 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 | |
c609719b WD |
306 | |
307 | /* memory bank settings*/ | |
308 | /* | |
309 | * only bits 20-29 are actually used from these vales to set the | |
310 | * start/end address the upper two bits will be 0, and the lower 20 | |
311 | * bits will be set to 0x00000 for a start address, or 0xfffff for an | |
312 | * end address | |
313 | */ | |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_BANK0_START 0x00000000 |
315 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
316 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
317 | #define CONFIG_SYS_BANK1_START 0x3ff00000 | |
318 | #define CONFIG_SYS_BANK1_END 0x3fffffff | |
319 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
320 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
321 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
322 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
323 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
324 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
325 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
326 | #define CONFIG_SYS_BANK4_START 0x00000000 | |
327 | #define CONFIG_SYS_BANK4_END 0x00000000 | |
328 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
329 | #define CONFIG_SYS_BANK5_START 0x00000000 | |
330 | #define CONFIG_SYS_BANK5_END 0x00000000 | |
331 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
332 | #define CONFIG_SYS_BANK6_START 0x00000000 | |
333 | #define CONFIG_SYS_BANK6_END 0x00000000 | |
334 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
335 | #define CONFIG_SYS_BANK7_START 0x00000000 | |
336 | #define CONFIG_SYS_BANK7_END 0x00000000 | |
337 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
c609719b WD |
338 | /* |
339 | * Memory bank enable bitmask, specifying which of the banks defined above | |
340 | are actually present. MSB is for bank #7, LSB is for bank #0. | |
341 | */ | |
6d0f6bcf | 342 | #define CONFIG_SYS_BANK_ENABLE 0x01 |
c609719b | 343 | |
6d0f6bcf | 344 | #define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ |
c609719b | 345 | /* see 8240 book for bit definitions */ |
6d0f6bcf | 346 | #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ |
c609719b WD |
347 | /* currently accessed page in memory */ |
348 | /* see 8240 book for details */ | |
349 | ||
350 | /* SDRAM 0 - 256MB */ | |
6d0f6bcf JCPV |
351 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
352 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
c609719b WD |
353 | |
354 | /* stack in DCACHE @ 1GB (no backing mem) */ | |
355 | #if defined(USE_DINK32) | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) |
357 | #define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) | |
c609719b | 358 | #else |
6d0f6bcf JCPV |
359 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) |
360 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
c609719b WD |
361 | #endif |
362 | ||
363 | /* PCI memory */ | |
6d0f6bcf JCPV |
364 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
365 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
c609719b WD |
366 | |
367 | /* Flash, config addrs, etc */ | |
6d0f6bcf JCPV |
368 | #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
369 | #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
370 | ||
371 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
372 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
373 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
374 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
375 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
376 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
377 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
378 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
c609719b WD |
379 | |
380 | /* | |
381 | * For booting Linux, the board info and command line data | |
382 | * have to be in the first 8 MB of memory, since this is | |
383 | * the maximum mapped by the Linux kernel during initialization. | |
384 | */ | |
6d0f6bcf | 385 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
386 | /*----------------------------------------------------------------------- |
387 | * FLASH organization | |
388 | */ | |
6d0f6bcf JCPV |
389 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
390 | #define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ | |
c609719b | 391 | |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
393 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b WD |
394 | |
395 | /*----------------------------------------------------------------------- | |
396 | * Cache Configuration | |
397 | */ | |
6d0f6bcf | 398 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ |
fe7f782d | 399 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 400 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
c609719b WD |
401 | #endif |
402 | ||
c609719b WD |
403 | /* values according to the manual */ |
404 | ||
405 | #define CONFIG_DRAM_50MHZ 1 | |
406 | #define CONFIG_SDRAM_50MHZ | |
407 | ||
408 | #undef NR_8259_INTS | |
409 | #define NR_8259_INTS 1 | |
410 | ||
411 | ||
412 | #define CONFIG_DISK_SPINUP_TIME 1000000 | |
413 | ||
414 | ||
415 | #endif /* __CONFIG_H */ |