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c609719b | 1 | /* |
414eec35 | 2 | * (C) Copyright 2001-2005 |
c609719b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* ------------------------------------------------------------------------- */ | |
25 | ||
26 | /* | |
27 | * board/config.h - configuration options, board specific | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | ||
38 | #define CONFIG_MPC824X 1 | |
39 | #define CONFIG_MPC8245 1 | |
40 | #define CONFIG_SANDPOINT 1 | |
41 | ||
2ae18241 | 42 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
de550d6b | 43 | #define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds" |
2ae18241 | 44 | |
c609719b WD |
45 | #if 0 |
46 | #define USE_DINK32 1 | |
47 | #else | |
48 | #undef USE_DINK32 | |
49 | #endif | |
50 | ||
51 | #define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ | |
52 | #define CONFIG_BAUDRATE 9600 | |
53 | #define CONFIG_DRAM_SPEED 100 /* MHz */ | |
54 | ||
414eec35 WD |
55 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
56 | ||
c609719b | 57 | |
a1aa0bb5 JL |
58 | /* |
59 | * BOOTP options | |
60 | */ | |
61 | #define CONFIG_BOOTP_BOOTFILESIZE | |
62 | #define CONFIG_BOOTP_BOOTPATH | |
63 | #define CONFIG_BOOTP_GATEWAY | |
64 | #define CONFIG_BOOTP_HOSTNAME | |
65 | ||
66 | ||
fe7f782d JL |
67 | /* |
68 | * Command line configuration. | |
69 | */ | |
70 | #include <config_cmd_default.h> | |
71 | ||
72 | #define CONFIG_CMD_DHCP | |
73 | #define CONFIG_CMD_ELF | |
74 | #define CONFIG_CMD_I2C | |
75 | #define CONFIG_CMD_EEPROM | |
76 | #define CONFIG_CMD_NFS | |
77 | #define CONFIG_CMD_PCI | |
78 | #define CONFIG_CMD_SNTP | |
c609719b WD |
79 | |
80 | ||
81 | /* | |
82 | * Miscellaneous configurable options | |
83 | */ | |
6d0f6bcf JCPV |
84 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
85 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
86 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
87 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
88 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
89 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
90 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ | |
91 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
c609719b WD |
92 | |
93 | /*----------------------------------------------------------------------- | |
94 | * PCI stuff | |
95 | *----------------------------------------------------------------------- | |
96 | */ | |
97 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 98 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
c609719b WD |
99 | #undef CONFIG_PCI_PNP |
100 | ||
c609719b WD |
101 | |
102 | #define CONFIG_EEPRO100 | |
6d0f6bcf | 103 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
c609719b WD |
104 | #define CONFIG_NATSEMI |
105 | #define CONFIG_NS8382X | |
106 | ||
107 | #define PCI_ENET0_IOADDR 0x80000000 | |
108 | #define PCI_ENET0_MEMADDR 0x80000000 | |
109 | #define PCI_ENET1_IOADDR 0x81000000 | |
110 | #define PCI_ENET1_MEMADDR 0x81000000 | |
111 | ||
112 | ||
113 | /*----------------------------------------------------------------------- | |
114 | * Start addresses for the final memory configuration | |
115 | * (Set up by the startup code) | |
6d0f6bcf | 116 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 117 | */ |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
119 | #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 | |
c609719b | 120 | |
6d0f6bcf | 121 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
c609719b WD |
122 | |
123 | #if defined (USE_DINK32) | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_MONITOR_LEN 0x00030000 |
125 | #define CONFIG_SYS_MONITOR_BASE 0x00090000 | |
126 | #define CONFIG_SYS_RAMBOOT 1 | |
127 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
553f0982 | 128 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 |
25ddd1fb | 129 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 130 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c609719b | 131 | #else |
6d0f6bcf JCPV |
132 | #undef CONFIG_SYS_RAMBOOT |
133 | #define CONFIG_SYS_MONITOR_LEN 0x00030000 | |
14d0a02a | 134 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
c609719b | 135 | |
c609719b | 136 | |
6d0f6bcf | 137 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
553f0982 | 138 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
25ddd1fb | 139 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
c609719b WD |
140 | |
141 | #endif | |
142 | ||
6d0f6bcf | 143 | #define CONFIG_SYS_FLASH_BASE 0xFFF00000 |
c609719b | 144 | #if 0 |
6d0f6bcf | 145 | #define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ |
c609719b | 146 | #else |
6d0f6bcf | 147 | #define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ |
c609719b | 148 | #endif |
5a1aceb0 | 149 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
150 | #define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ |
151 | #define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ | |
c609719b | 152 | |
6d0f6bcf | 153 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ |
c609719b | 154 | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
156 | #define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ | |
c609719b | 157 | |
6d0f6bcf | 158 | #define CONFIG_SYS_EUMB_ADDR 0xFC000000 |
c609719b | 159 | |
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_ISA_MEM 0xFD000000 |
161 | #define CONFIG_SYS_ISA_IO 0xFE000000 | |
c609719b | 162 | |
6d0f6bcf JCPV |
163 | #define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ |
164 | #define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 | |
c609719b WD |
165 | #define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ |
166 | #define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ | |
167 | ||
168 | /* | |
169 | * select i2c support configuration | |
170 | * | |
171 | * Supported configurations are {none, software, hardware} drivers. | |
172 | * If the software driver is chosen, there are some additional | |
173 | * configuration items that the driver uses to drive the port pins. | |
174 | */ | |
ea818dbb HS |
175 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ |
176 | #undef CONFIG_SYS_I2C_SOFT | |
177 | #define CONFIG_SYS_I2C_SPEED 400000 | |
178 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
c609719b | 179 | |
ea818dbb | 180 | #ifdef CONFIG_SYS_I2C_SOFT |
c609719b | 181 | #error "Soft I2C is not configured properly. Please review!" |
ea818dbb HS |
182 | #define CONFIG_SYS_I2C |
183 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
184 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE | |
c609719b WD |
185 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
186 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
187 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
188 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
189 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
190 | else iop->pdat &= ~0x00010000 | |
191 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
192 | else iop->pdat &= ~0x00020000 | |
193 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
ea818dbb | 194 | #endif /* CONFIG_SYS_I2C_SOFT */ |
c609719b | 195 | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ |
197 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
198 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
199 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
c609719b | 200 | |
6d0f6bcf | 201 | #define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } |
c609719b WD |
202 | |
203 | /*----------------------------------------------------------------------- | |
204 | * Definitions for initial stack pointer and data area (in DPRAM) | |
205 | */ | |
206 | ||
207 | ||
57d6c589 | 208 | /* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ |
210 | #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ | |
211 | #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ | |
c609719b | 212 | |
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
214 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ | |
c609719b WD |
215 | |
216 | /* | |
217 | * NS87308 Configuration | |
218 | */ | |
55d6d2d3 | 219 | #define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ |
c609719b | 220 | |
6d0f6bcf | 221 | #define CONFIG_SYS_NS87308_BADDR_10 1 |
c609719b | 222 | |
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ |
224 | CONFIG_SYS_NS87308_UART2 | \ | |
225 | CONFIG_SYS_NS87308_POWRMAN | \ | |
226 | CONFIG_SYS_NS87308_RTC_APC ) | |
c609719b | 227 | |
6d0f6bcf | 228 | #undef CONFIG_SYS_NS87308_PS2MOD |
c609719b | 229 | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_NS87308_CS0_BASE 0x0076 |
231 | #define CONFIG_SYS_NS87308_CS0_CONF 0x30 | |
232 | #define CONFIG_SYS_NS87308_CS1_BASE 0x0075 | |
233 | #define CONFIG_SYS_NS87308_CS1_CONF 0x30 | |
234 | #define CONFIG_SYS_NS87308_CS2_BASE 0x0074 | |
235 | #define CONFIG_SYS_NS87308_CS2_CONF 0x30 | |
c609719b WD |
236 | |
237 | /* | |
238 | * NS16550 Configuration | |
239 | */ | |
6d0f6bcf JCPV |
240 | #define CONFIG_SYS_NS16550 |
241 | #define CONFIG_SYS_NS16550_SERIAL | |
c609719b | 242 | |
6d0f6bcf | 243 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
c609719b | 244 | |
f832d8a1 | 245 | #if (CONFIG_CONS_INDEX > 2) |
6d0f6bcf | 246 | #define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000 |
f832d8a1 | 247 | #else |
6d0f6bcf | 248 | #define CONFIG_SYS_NS16550_CLK 1843200 |
f832d8a1 | 249 | #endif |
49822e23 | 250 | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) |
252 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) | |
253 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500) | |
254 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600) | |
c609719b WD |
255 | |
256 | /* | |
257 | * Low Level Configuration Settings | |
258 | * (address mappings, register initial values, etc.) | |
259 | * You should know what you are doing if you make changes here. | |
260 | */ | |
261 | ||
262 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
263 | ||
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ |
265 | #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ | |
c609719b | 266 | |
6d0f6bcf | 267 | #define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ |
c609719b WD |
268 | |
269 | /* the following are for SDRAM only*/ | |
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ |
271 | #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ | |
272 | #define CONFIG_SYS_RDLAT 4 /* data latency from read command */ | |
273 | #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ | |
274 | #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ | |
275 | #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ | |
276 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ | |
277 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ | |
c609719b | 278 | #if 0 |
6d0f6bcf | 279 | #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ |
c609719b WD |
280 | #endif |
281 | ||
6d0f6bcf JCPV |
282 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 |
283 | #define CONFIG_SYS_EXTROM 1 | |
284 | #define CONFIG_SYS_REGDIMM 0 | |
c609719b WD |
285 | |
286 | ||
287 | /* memory bank settings*/ | |
288 | /* | |
289 | * only bits 20-29 are actually used from these vales to set the | |
290 | * start/end address the upper two bits will be 0, and the lower 20 | |
291 | * bits will be set to 0x00000 for a start address, or 0xfffff for an | |
292 | * end address | |
293 | */ | |
6d0f6bcf JCPV |
294 | #define CONFIG_SYS_BANK0_START 0x00000000 |
295 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
296 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
297 | #define CONFIG_SYS_BANK1_START 0x3ff00000 | |
298 | #define CONFIG_SYS_BANK1_END 0x3fffffff | |
299 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
300 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
301 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
302 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
303 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
304 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
305 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
306 | #define CONFIG_SYS_BANK4_START 0x00000000 | |
307 | #define CONFIG_SYS_BANK4_END 0x00000000 | |
308 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
309 | #define CONFIG_SYS_BANK5_START 0x00000000 | |
310 | #define CONFIG_SYS_BANK5_END 0x00000000 | |
311 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
312 | #define CONFIG_SYS_BANK6_START 0x00000000 | |
313 | #define CONFIG_SYS_BANK6_END 0x00000000 | |
314 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
315 | #define CONFIG_SYS_BANK7_START 0x00000000 | |
316 | #define CONFIG_SYS_BANK7_END 0x00000000 | |
317 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
c609719b WD |
318 | /* |
319 | * Memory bank enable bitmask, specifying which of the banks defined above | |
320 | are actually present. MSB is for bank #7, LSB is for bank #0. | |
321 | */ | |
6d0f6bcf | 322 | #define CONFIG_SYS_BANK_ENABLE 0x01 |
c609719b | 323 | |
6d0f6bcf | 324 | #define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ |
c609719b | 325 | /* see 8240 book for bit definitions */ |
6d0f6bcf | 326 | #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ |
c609719b WD |
327 | /* currently accessed page in memory */ |
328 | /* see 8240 book for details */ | |
329 | ||
330 | /* SDRAM 0 - 256MB */ | |
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
332 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
c609719b WD |
333 | |
334 | /* stack in DCACHE @ 1GB (no backing mem) */ | |
335 | #if defined(USE_DINK32) | |
6d0f6bcf JCPV |
336 | #define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) |
337 | #define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) | |
c609719b | 338 | #else |
6d0f6bcf JCPV |
339 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) |
340 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
c609719b WD |
341 | #endif |
342 | ||
343 | /* PCI memory */ | |
6d0f6bcf JCPV |
344 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
345 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
c609719b WD |
346 | |
347 | /* Flash, config addrs, etc */ | |
6d0f6bcf JCPV |
348 | #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
349 | #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
350 | ||
351 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
352 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
353 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
354 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
355 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
356 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
357 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
358 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
c609719b WD |
359 | |
360 | /* | |
361 | * For booting Linux, the board info and command line data | |
362 | * have to be in the first 8 MB of memory, since this is | |
363 | * the maximum mapped by the Linux kernel during initialization. | |
364 | */ | |
6d0f6bcf | 365 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
366 | /*----------------------------------------------------------------------- |
367 | * FLASH organization | |
368 | */ | |
6d0f6bcf JCPV |
369 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
370 | #define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ | |
c609719b | 371 | |
6d0f6bcf JCPV |
372 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
373 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b WD |
374 | |
375 | /*----------------------------------------------------------------------- | |
376 | * Cache Configuration | |
377 | */ | |
6d0f6bcf | 378 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ |
fe7f782d | 379 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 380 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
c609719b WD |
381 | #endif |
382 | ||
c609719b WD |
383 | /* values according to the manual */ |
384 | ||
385 | #define CONFIG_DRAM_50MHZ 1 | |
386 | #define CONFIG_SDRAM_50MHZ | |
387 | ||
388 | #undef NR_8259_INTS | |
389 | #define NR_8259_INTS 1 | |
390 | ||
391 | ||
392 | #define CONFIG_DISK_SPINUP_TIME 1000000 | |
393 | ||
394 | ||
395 | #endif /* __CONFIG_H */ |