[thirdparty/u-boot.git] / include / configs / T102xRDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2020-2021 NXP
 */

/*
 * T1024/T1023 RDB board configuration file
 */

#ifndef __T1024RDB_H
#define __T1024RDB_H

#include <linux/stringify.h>

/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
#define CONFIG_ENABLE_36BIT_PHYS

#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_PAD_TO		0x40000
#define CONFIG_SPL_MAX_SIZE		0x28000
#define RESET_VECTOR_OFFSET		0x27FFC
#define BOOT_PAGE_OFFSET		0x27000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_SKIP_RELOCATE
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif

#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START	0x30000000
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif

#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif

#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS	0x30000FFC
#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST	(0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_START	(0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif

#endif /* CONFIG_RAMBOOT_PBL */

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

/* PCIe Boot - Master */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
/*
 * for slave u-boot IMAGE instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
#else
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
#endif
/*
 * for slave UCODE and ENV instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS	 0x3ffe00000ull
#else
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
#endif
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE	0x40000 /* 256K */
/* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET	0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK	0x00000001 /* release core 0 */

/* PCIe Boot - Slave */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
/* Set 1M boot space for PCIe boot */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS	\
		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif

/*
 *  Config the L3 Cache as L3 SRAM
 */
#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
#define CONFIG_SYS_L3_SIZE		(256 << 10)
#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)

#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR		0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
#endif

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM	0

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_SPD_BUS_NUM	0
#define SPD_EEPROM_ADDRESS	0x51
#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_SDRAM_SIZE   2048
#endif

/*
 * IFC Definitions
 */
#define CONFIG_SYS_FLASH_BASE	0xe8000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#else
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
#endif

#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)

/* NOR Flash Timing Params */
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
				CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
#endif
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1A) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x0

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}

#ifdef CONFIG_TARGET_T1024RDB
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE		0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT		(0xf)
#define CONFIG_SYS_CSPR2		(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
						| CSPR_PORT_SIZE_8 \
						| CSPR_MSEL_GPCM \
						| CSPR_V)
#define CONFIG_SYS_AMASK2		IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR2		0x0

/* CPLD Timing parameters for IFC CS2 */
#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
						FTIM0_GPCM_TEADC(0x0e) | \
						FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
						FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
						FTIM2_GPCM_TCH(0x8) | \
						FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3		0x0
#endif

/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE		0xff800000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
#else
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
#endif
#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)

#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL 3Bytes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_128	/* Spare size = 128 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
#endif

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_DDR_LAW		11
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_HWCONFIG

/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
#endif
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)

/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)

/* I2C */

#define I2C_PCA6408_BUS_NUM		1
#define I2C_PCA6408_ADDR		0x20

/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT	0x8

/*
 * RTC configuration
 */
#define RTC
#define CONFIG_RTC_DS1337	1
#define CONFIG_SYS_I2C_RTC_ADDR	0x68

/*
 * eSPI - Enhanced SPI
 */

/*
 * General PCIe
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */
#define CONFIG_PCIE3		/* PCIE controller 3 */

#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
#endif

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
#endif

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
#endif

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#endif	/* CONFIG_PCI */

/*
 * USB
 */
#define CONFIG_HAS_FSL_DR_USB

#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif

/*
 * SDHC
 */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif

/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_BMAN_NUM_PORTALS	10
#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#else
#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
#endif
#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
					CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS	10
#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
#else
#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
#endif
#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
					CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08

#define CONFIG_SYS_DPAA_FMAN

#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_SYS_DPAA_FMAN
#if defined(CONFIG_TARGET_T1024RDB)
#define RGMII_PHY1_ADDR		0x2
#define RGMII_PHY2_ADDR		0x6
#define SGMII_AQR_PHY_ADDR	0x2
#define FM1_10GEC1_PHY_ADDR	0x1
#elif defined(CONFIG_TARGET_T1023RDB)
#define RGMII_PHY1_ADDR		0x1
#define SGMII_RTK_PHY_ADDR	0x3
#define SGMII_AQR_PHY_ADDR	0x2
#endif
#endif

/*
 * Dynamic MTD Partition support with mtdparts
 */

/*
 * Environment
 */
#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * Miscellaneous configurable options
 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
#define __USB_PHY_TYPE		utmi

#ifdef CONFIG_ARCH_T1024
#define ARCH_EXTRA_ENV_SETTINGS \
	"bank_intlv=cs0_cs1\0"			\
	"ramdiskfile=t1024rdb/ramdisk.uboot\0"	\
	"fdtfile=t1024rdb/t1024rdb.dtb\0"
#else
#define ARCH_EXTRA_ENV_SETTINGS \
	"bank_intlv=null\0"			\
	"ramdiskfile=t1023rdb/ramdisk.uboot\0"	\
	"fdtfile=t1023rdb/t1023rdb.dtb\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	ARCH_EXTRA_ENV_SETTINGS					\
	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
	"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
	"netdev=eth0\0"						\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
	"protect off $ubootaddr +$filesize && "			\
	"erase $ubootaddr +$filesize && "			\
	"cp.b $loadaddr $ubootaddr $filesize && "		\
	"protect on $ubootaddr +$filesize && "			\
	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
	"consoledev=ttyS0\0"					\
	"ramdiskaddr=2000000\0"					\
	"fdtaddr=1e00000\0"					\
	"bdev=sda3\0"

#include <asm/fsl_secure_boot.h>

#endif	/* __T1024RDB_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
48c6f328 SL	2	/*
48c6f328 SL	3	* Copyright 2014 Freescale Semiconductor, Inc.
a97a071d	4	* Copyright 2020-2021 NXP
48c6f328 SL	5	*/
	6
	7	/*
	8	* T1024/T1023 RDB board configuration file
	9	*/
	10
	11	#ifndef __T1024RDB_H
	12	#define __T1024RDB_H
	13
1af3c7f4 SG	14	#include <linux/stringify.h>
1af3c7f4 SG	15
48c6f328	16	/* High Level Configuration Options */
48c6f328	17	#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
48c6f328 SL	18	#define CONFIG_ENABLE_36BIT_PHYS
48c6f328 SL	19
48c6f328	20	#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
51370d56	21	#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
48c6f328	22
48c6f328	23	#ifdef CONFIG_RAMBOOT_PBL
48c6f328	24	#define CONFIG_SPL_FLUSH_IMAGE
48c6f328 SL	25	#define CONFIG_SPL_PAD_TO 0x40000
	26	#define CONFIG_SPL_MAX_SIZE 0x28000
	27	#define RESET_VECTOR_OFFSET 0x27FFC
	28	#define BOOT_PAGE_OFFSET 0x27000
	29	#ifdef CONFIG_SPL_BUILD
	30	#define CONFIG_SPL_SKIP_RELOCATE
	31	#define CONFIG_SPL_COMMON_INIT_DDR
	32	#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
48c6f328 SL	33	#endif
48c6f328 SL	34
88718be3	35	#ifdef CONFIG_MTD_RAW_NAND
48c6f328	36	#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
f49b8c1b	37	#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
f49b8c1b	38	#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
ab37df9d T	39	#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
	40	#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	41	#endif
48c6f328 SL	42	#endif
	43
	44	#ifdef CONFIG_SPIFLASH
f49b8c1b	45	#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
48c6f328 SL	46	#define CONFIG_SPL_SPI_FLASH_MINIMAL
48c6f328 SL	47	#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
f49b8c1b	48	#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
f49b8c1b	49	#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
48c6f328	50	#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
48c6f328 SL	51	#ifndef CONFIG_SPL_BUILD
	52	#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	53	#endif
48c6f328 SL	54	#endif
	55
	56	#ifdef CONFIG_SDCARD
f49b8c1b	57	#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
48c6f328	58	#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
f49b8c1b	59	#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
f49b8c1b	60	#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
48c6f328	61	#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
48c6f328 SL	62	#ifndef CONFIG_SPL_BUILD
	63	#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	64	#endif
48c6f328 SL	65	#endif
	66
	67	#endif /* CONFIG_RAMBOOT_PBL */
	68
48c6f328 SL	69	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	70	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	71	#endif
	72
48c6f328 SL	73	/* PCIe Boot - Master */
	74	#define CONFIG_SRIO_PCIE_BOOT_MASTER
	75	/*
	76	* for slave u-boot IMAGE instored in master memory space,
	77	* PHYS must be aligned based on the SIZE
	78	*/
	79	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
	80	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
	81	#ifdef CONFIG_PHYS_64BIT
	82	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
	83	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
	84	#else
	85	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
	86	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
	87	#endif
	88	/*
	89	* for slave UCODE and ENV instored in master memory space,
	90	* PHYS must be aligned based on the SIZE
	91	*/
	92	#ifdef CONFIG_PHYS_64BIT
	93	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
	94	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
	95	#else
	96	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
	97	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
	98	#endif
	99	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
	100	/* slave core release by master*/
	101	#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
	102	#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
	103
	104	/* PCIe Boot - Slave */
	105	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
	106	#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
	107	#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
	108	(0x300000000ull \| CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
	109	/* Set 1M boot space for PCIe boot */
	110	#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
	111	#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
	112	(0x300000000ull \| CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
	113	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
48c6f328 SL	114	#endif
48c6f328 SL	115
48c6f328 SL	116	/*
	117	* These can be toggled for performance analysis, otherwise use default.
	118	*/
	119	#define CONFIG_SYS_CACHE_STASHING
48c6f328	120	#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
48c6f328	121	#ifdef CONFIG_DDR_ECC
48c6f328 SL	122	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	123	#endif
	124
48c6f328 SL	125	/*
	126	* Config the L3 Cache as L3 SRAM
	127	*/
	128	#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
	129	#define CONFIG_SYS_L3_SIZE (256 << 10)
	130	#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
a09fea1d	131	#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
48c6f328 SL	132	#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
	133	#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
	134	#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
48c6f328 SL	135
	136	#ifdef CONFIG_PHYS_64BIT
	137	#define CONFIG_SYS_DCSRBAR 0xf0000000
	138	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
	139	#endif
	140
	141	/* EEPROM */
48c6f328 SL	142	#define CONFIG_SYS_I2C_EEPROM_NXID
48c6f328 SL	143	#define CONFIG_SYS_EEPROM_BUS_NUM 0
48c6f328 SL	144
	145	/*
	146	* DDR Setup
	147	*/
	148	#define CONFIG_VERY_BIG_RAM
	149	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	150	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
960286b6	151	#if defined(CONFIG_TARGET_T1024RDB)
48c6f328 SL	152	#define CONFIG_SYS_SPD_BUS_NUM 0
48c6f328 SL	153	#define SPD_EEPROM_ADDRESS 0x51
48c6f328	154	#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
9082405d	155	#elif defined(CONFIG_TARGET_T1023RDB)
e8a7f1c3 SL	156	#define CONFIG_SYS_DDR_RAW_TIMING
	157	#define CONFIG_SYS_SDRAM_SIZE 2048
	158	#endif
48c6f328 SL	159
	160	/*
	161	* IFC Definitions
	162	*/
	163	#define CONFIG_SYS_FLASH_BASE 0xe8000000
	164	#ifdef CONFIG_PHYS_64BIT
	165	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_FLASH_BASE)
	166	#else
	167	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	168	#endif
	169
	170	#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
	171	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	172	CSPR_PORT_SIZE_16 \| \
	173	CSPR_MSEL_NOR \| \
	174	CSPR_V)
	175	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	176
	177	/* NOR Flash Timing Params */
960286b6	178	#if defined(CONFIG_TARGET_T1024RDB)
48c6f328	179	#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
9082405d	180	#elif defined(CONFIG_TARGET_T1023RDB)
ff7ea2d1	181	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) \| \
e8a7f1c3 SL	182	CSOR_NAND_TRHZ_80 \| CSOR_NOR_ADM_SHFT_MODE_EN)
e8a7f1c3 SL	183	#endif
48c6f328 SL	184	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	185	FTIM0_NOR_TEADC(0x5) \| \
	186	FTIM0_NOR_TEAHC(0x5))
	187	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	188	FTIM1_NOR_TRAD_NOR(0x1A) \|\
	189	FTIM1_NOR_TSEQRAD_NOR(0x13))
	190	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	191	FTIM2_NOR_TCH(0x4) \| \
	192	FTIM2_NOR_TWPH(0x0E) \| \
	193	FTIM2_NOR_TWP(0x1c))
	194	#define CONFIG_SYS_NOR_FTIM3 0x0
	195
	196	#define CONFIG_SYS_FLASH_QUIET_TEST
	197	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	198
48c6f328 SL	199	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	200	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	201	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	202
	203	#define CONFIG_SYS_FLASH_EMPTY_INFO
	204	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
	205
960286b6	206	#ifdef CONFIG_TARGET_T1024RDB
48c6f328 SL	207	/* CPLD on IFC */
	208	#define CONFIG_SYS_CPLD_BASE 0xffdf0000
	209	#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_CPLD_BASE)
	210	#define CONFIG_SYS_CSPR2_EXT (0xf)
	211	#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
	212	\| CSPR_PORT_SIZE_8 \
	213	\| CSPR_MSEL_GPCM \
	214	\| CSPR_V)
	215	#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
	216	#define CONFIG_SYS_CSOR2 0x0
	217
	218	/* CPLD Timing parameters for IFC CS2 */
	219	#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	220	FTIM0_GPCM_TEADC(0x0e) \| \
	221	FTIM0_GPCM_TEAHC(0x0e))
	222	#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) \| \
	223	FTIM1_GPCM_TRAD(0x1f))
	224	#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) \| \
	225	FTIM2_GPCM_TCH(0x8) \| \
	226	FTIM2_GPCM_TWP(0x1f))
	227	#define CONFIG_SYS_CS2_FTIM3 0x0
e8a7f1c3	228	#endif
48c6f328 SL	229
48c6f328 SL	230	/* NAND Flash on IFC */
48c6f328 SL	231	#define CONFIG_SYS_NAND_BASE 0xff800000
	232	#ifdef CONFIG_PHYS_64BIT
	233	#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_NAND_BASE)
	234	#else
	235	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	236	#endif
	237	#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
	238	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	239	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	240	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	241	\| CSPR_V)
	242	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	243
960286b6	244	#if defined(CONFIG_TARGET_T1024RDB)
48c6f328 SL	245	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	246	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	247	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	248	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	249	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	250	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
	251	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
9082405d	252	#elif defined(CONFIG_TARGET_T1023RDB)
7842950f JS	253	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	254	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	255	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
e8a7f1c3 SL	256	\| CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
	257	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	258	\| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
	259	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
e8a7f1c3	260	#endif
48c6f328	261
48c6f328 SL	262	/* ONFI NAND Flash mode0 Timing Params */
	263	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	264	FTIM0_NAND_TWP(0x18) \| \
	265	FTIM0_NAND_TWCHT(0x07) \| \
	266	FTIM0_NAND_TWH(0x0a))
	267	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	268	FTIM1_NAND_TWBE(0x39) \| \
	269	FTIM1_NAND_TRR(0x0e) \| \
	270	FTIM1_NAND_TRP(0x18))
	271	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	272	FTIM2_NAND_TREH(0x0a) \| \
	273	FTIM2_NAND_TWHRE(0x1e))
	274	#define CONFIG_SYS_NAND_FTIM3 0x0
	275
	276	#define CONFIG_SYS_NAND_DDR_LAW 11
	277	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	278	#define CONFIG_SYS_MAX_NAND_DEVICE 1
48c6f328	279
88718be3	280	#if defined(CONFIG_MTD_RAW_NAND)
48c6f328 SL	281	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	282	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	283	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	284	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	285	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	286	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	287	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	288	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	289	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	290	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
	291	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	292	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	293	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	294	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	295	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	296	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	297	#else
	298	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	299	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	300	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	301	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	302	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	303	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	304	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	305	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	306	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
	307	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	308	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	309	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
	310	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	311	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	312	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	313	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
	314	#endif
	315
48c6f328 SL	316	#if defined(CONFIG_RAMBOOT_PBL)
	317	#define CONFIG_SYS_RAMBOOT
	318	#endif
	319
48c6f328 SL	320	#define CONFIG_HWCONFIG
	321
	322	/* define to use L1 as initial stack */
	323	#define CONFIG_L1_INIT_RAM
	324	#define CONFIG_SYS_INIT_RAM_LOCK
	325	#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
	326	#ifdef CONFIG_PHYS_64BIT
	327	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
b3142e2c	328	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
48c6f328 SL	329	/* The assembler doesn't like typecast */
	330	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	331	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	332	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
	333	#else
b3142e2c	334	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
48c6f328 SL	335	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
	336	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
	337	#endif
	338	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
	339
	340	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	341	GENERATED_GBL_DATA_SIZE)
	342	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	343
	344	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
48c6f328 SL	345
48c6f328 SL	346	/* Serial Port */
48c6f328 SL	347	#define CONFIG_SYS_NS16550_SERIAL
	348	#define CONFIG_SYS_NS16550_REG_SIZE 1
	349	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	350
	351	#define CONFIG_SYS_BAUDRATE_TABLE \
	352	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	353
	354	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
	355	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
	356	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
	357	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
48c6f328	358
48c6f328	359	/* I2C */
48c6f328	360
ff7ea2d1 SL	361	#define I2C_PCA6408_BUS_NUM 1
ff7ea2d1 SL	362	#define I2C_PCA6408_ADDR 0x20
48c6f328 SL	363
	364	/* I2C bus multiplexer */
	365	#define I2C_MUX_CH_DEFAULT 0x8
	366
	367	/*
	368	* RTC configuration
	369	*/
	370	#define RTC
	371	#define CONFIG_RTC_DS1337 1
	372	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	373
	374	/*
	375	* eSPI - Enhanced SPI
	376	*/
48c6f328 SL	377
	378	/*
	379	* General PCIe
	380	* Memory space is mapped 1-1, but I/O space must start from 0.
	381	*/
b38eaec5 RD	382	#define CONFIG_PCIE1 /* PCIE controller 1 */
	383	#define CONFIG_PCIE2 /* PCIE controller 2 */
	384	#define CONFIG_PCIE3 /* PCIE controller 3 */
48c6f328 SL	385
	386	#ifdef CONFIG_PCI
	387	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
	388	#ifdef CONFIG_PCIE1
	389	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
48c6f328	390	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
48c6f328	391	#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
48c6f328	392	#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
48c6f328 SL	393	#endif
	394
	395	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
	396	#ifdef CONFIG_PCIE2
	397	#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
48c6f328	398	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
48c6f328	399	#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
48c6f328	400	#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
48c6f328 SL	401	#endif
	402
	403	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
	404	#ifdef CONFIG_PCIE3
	405	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
48c6f328	406	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
48c6f328	407	#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
48c6f328	408	#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
48c6f328	409	#endif
f9abe6dd	410
48c6f328	411	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
48c6f328 SL	412	#endif /* CONFIG_PCI */
	413
	414	/*
	415	* USB
	416	*/
	417	#define CONFIG_HAS_FSL_DR_USB
	418
	419	#ifdef CONFIG_HAS_FSL_DR_USB
48c6f328	420	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
48c6f328 SL	421	#endif
	422
	423	/*
	424	* SDHC
	425	*/
48c6f328	426	#ifdef CONFIG_MMC
48c6f328	427	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
48c6f328 SL	428	#endif
	429
	430	/* Qman/Bman */
	431	#ifndef CONFIG_NOBQFMAN
2a8b3422	432	#define CONFIG_SYS_BMAN_NUM_PORTALS 10
48c6f328 SL	433	#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
	434	#ifdef CONFIG_PHYS_64BIT
	435	#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
	436	#else
	437	#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
	438	#endif
	439	#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
3fa66db4 JL	440	#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
	441	#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
	442	#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
	443	#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	444	#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
	445	CONFIG_SYS_BMAN_CENA_SIZE)
	446	#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	447	#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
2a8b3422	448	#define CONFIG_SYS_QMAN_NUM_PORTALS 10
48c6f328 SL	449	#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
	450	#ifdef CONFIG_PHYS_64BIT
	451	#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
	452	#else
	453	#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
	454	#endif
	455	#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
3fa66db4 JL	456	#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
	457	#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
	458	#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
	459	#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	460	#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
	461	CONFIG_SYS_QMAN_CENA_SIZE)
	462	#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	463	#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
48c6f328 SL	464
	465	#define CONFIG_SYS_DPAA_FMAN
	466
48c6f328 SL	467	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	468	#endif /* CONFIG_NOBQFMAN */
	469
	470	#ifdef CONFIG_SYS_DPAA_FMAN
960286b6	471	#if defined(CONFIG_TARGET_T1024RDB)
48c6f328 SL	472	#define RGMII_PHY1_ADDR 0x2
48c6f328 SL	473	#define RGMII_PHY2_ADDR 0x6
e8a7f1c3	474	#define SGMII_AQR_PHY_ADDR 0x2
48c6f328	475	#define FM1_10GEC1_PHY_ADDR 0x1
9082405d	476	#elif defined(CONFIG_TARGET_T1023RDB)
e8a7f1c3 SL	477	#define RGMII_PHY1_ADDR 0x1
	478	#define SGMII_RTK_PHY_ADDR 0x3
	479	#define SGMII_AQR_PHY_ADDR 0x2
	480	#endif
48c6f328 SL	481	#endif
48c6f328 SL	482
48c6f328 SL	483	/*
	484	* Dynamic MTD Partition support with mtdparts
	485	*/
48c6f328 SL	486
	487	/*
	488	* Environment
	489	*/
	490	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	491	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	492
48c6f328 SL	493	/*
	494	* Miscellaneous configurable options
	495	*/
48c6f328 SL	496
	497	/*
	498	* For booting Linux, the board info and command line data
	499	* have to be in the first 64 MB of memory, since this is
	500	* the maximum mapped by the Linux kernel during initialization.
	501	*/
	502	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
	503	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	504
48c6f328 SL	505	/*
	506	* Environment Configuration
	507	*/
	508	#define CONFIG_ROOTPATH "/opt/nfsroot"
e8a7f1c3	509	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
48c6f328 SL	510	#define __USB_PHY_TYPE utmi
48c6f328 SL	511
e5d5f5a8	512	#ifdef CONFIG_ARCH_T1024
47267f82 TR	513	#define ARCH_EXTRA_ENV_SETTINGS \
	514	"bank_intlv=cs0_cs1\0" \
	515	"ramdiskfile=t1024rdb/ramdisk.uboot\0" \
	516	"fdtfile=t1024rdb/t1024rdb.dtb\0"
48c6f328	517	#else
47267f82 TR	518	#define ARCH_EXTRA_ENV_SETTINGS \
	519	"bank_intlv=null\0" \
	520	"ramdiskfile=t1023rdb/ramdisk.uboot\0" \
	521	"fdtfile=t1023rdb/t1023rdb.dtb\0"
48c6f328 SL	522	#endif
	523
	524	#define CONFIG_EXTRA_ENV_SETTINGS \
47267f82	525	ARCH_EXTRA_ENV_SETTINGS \
48c6f328	526	"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
48c6f328	527	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
48c6f328 SL	528	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	529	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
	530	"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
	531	"netdev=eth0\0" \
	532	"tftpflash=tftpboot $loadaddr $uboot && " \
	533	"protect off $ubootaddr +$filesize && " \
	534	"erase $ubootaddr +$filesize && " \
	535	"cp.b $loadaddr $ubootaddr $filesize && " \
	536	"protect on $ubootaddr +$filesize && " \
	537	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	538	"consoledev=ttyS0\0" \
	539	"ramdiskaddr=2000000\0" \
b24a4f62	540	"fdtaddr=1e00000\0" \
48c6f328 SL	541	"bdev=sda3\0"
48c6f328 SL	542
48c6f328	543	#include <asm/fsl_secure_boot.h>
ef6c55a2	544
48c6f328	545	#endif /* __T1024RDB_H */