projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 7d436078 | 1 | /* |
| c60dee03 | 2 | * Copyright 2013-2014 Freescale Semiconductor, Inc. |
| 7d436078 PK |
3 | * |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | #ifndef __CONFIG_H | |
| 24 | #define __CONFIG_H | |
| 25 | ||
| 26 | /* | |
| 27 | * T1040 QDS board configuration file | |
| 28 | */ | |
| 7d436078 PK |
29 | |
| 30 | #ifdef CONFIG_RAMBOOT_PBL | |
| 31 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
| 32 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
| e4536f8e MY |
33 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg |
| 34 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg | |
| 7d436078 PK |
35 | #endif |
| 36 | ||
| 37 | /* High Level Configuration Options */ | |
| 7d436078 | 38 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
| 7d436078 | 39 | |
| 48f6a9a2 TY |
40 | /* support deep sleep */ |
| 41 | #define CONFIG_DEEP_SLEEP | |
| 48f6a9a2 | 42 | |
| 7d436078 PK |
43 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 44 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 45 | #endif | |
| 46 | ||
| 47 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
| 51370d56 | 48 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
| 7d436078 | 49 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| b38eaec5 RD |
50 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 51 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
| 52 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
| 53 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
| 7d436078 PK |
54 | |
| 55 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
| 56 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
| 57 | ||
| 7d436078 PK |
58 | #define CONFIG_ENV_OVERWRITE |
| 59 | ||
| e856bdcf | 60 | #ifdef CONFIG_MTD_NOR_FLASH |
| 7d436078 | 61 | #if defined(CONFIG_SPIFLASH) |
| 7d436078 | 62 | #elif defined(CONFIG_SDCARD) |
| 7d436078 | 63 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 7d436078 | 64 | #endif |
| 7d436078 PK |
65 | #endif |
| 66 | ||
| 67 | #ifndef __ASSEMBLY__ | |
| 68 | unsigned long get_board_sys_clk(void); | |
| 69 | unsigned long get_board_ddr_clk(void); | |
| 70 | #endif | |
| 71 | ||
| 72 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ | |
| 73 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
| 74 | ||
| 75 | /* | |
| 76 | * These can be toggled for performance analysis, otherwise use default. | |
| 77 | */ | |
| 78 | #define CONFIG_SYS_CACHE_STASHING | |
| 79 | #define CONFIG_BACKSIDE_L2_CACHE | |
| 80 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
| 81 | #define CONFIG_BTB /* toggle branch predition */ | |
| 82 | #define CONFIG_DDR_ECC | |
| 83 | #ifdef CONFIG_DDR_ECC | |
| 84 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 85 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 86 | #endif | |
| 87 | ||
| 88 | #define CONFIG_ENABLE_36BIT_PHYS | |
| 89 | ||
| 90 | #define CONFIG_ADDR_MAP | |
| 91 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
| 92 | ||
| 93 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
| 94 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| 7d436078 PK |
95 | |
| 96 | /* | |
| 97 | * Config the L3 Cache as L3 SRAM | |
| 98 | */ | |
| 99 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 | |
| 100 | ||
| 101 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
| 102 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
| 103 | ||
| 104 | /* EEPROM */ | |
| 105 | #define CONFIG_ID_EEPROM | |
| 106 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 107 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 108 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 109 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 110 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 111 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 112 | ||
| 113 | /* | |
| 114 | * DDR Setup | |
| 115 | */ | |
| 116 | #define CONFIG_VERY_BIG_RAM | |
| 117 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 118 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 119 | ||
| 7d436078 | 120 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 2eb3ac7f | 121 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 7d436078 PK |
122 | |
| 123 | #define CONFIG_DDR_SPD | |
| 7d436078 PK |
124 | |
| 125 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
| 126 | #define SPD_EEPROM_ADDRESS 0x51 | |
| 127 | ||
| 128 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
| 129 | ||
| 130 | /* | |
| 131 | * IFC Definitions | |
| 132 | */ | |
| 133 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 | |
| 134 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
| 135 | ||
| 136 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
| 137 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 138 | + 0x8000000) | \ | |
| 139 | CSPR_PORT_SIZE_16 | \ | |
| 140 | CSPR_MSEL_NOR | \ | |
| 141 | CSPR_V) | |
| 142 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) | |
| 143 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 144 | CSPR_PORT_SIZE_16 | \ | |
| 145 | CSPR_MSEL_NOR | \ | |
| 146 | CSPR_V) | |
| 147 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 377ffcfa SS |
148 | |
| 149 | /* | |
| 150 | * TDM Definition | |
| 151 | */ | |
| 152 | #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 | |
| 153 | ||
| 7d436078 PK |
154 | /* NOR Flash Timing Params */ |
| 155 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
| 156 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 157 | FTIM0_NOR_TEADC(0x5) | \ | |
| 158 | FTIM0_NOR_TEAHC(0x5)) | |
| 159 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 160 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
| 161 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 162 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 163 | FTIM2_NOR_TCH(0x4) | \ | |
| 164 | FTIM2_NOR_TWPH(0x0E) | \ | |
| 165 | FTIM2_NOR_TWP(0x1c)) | |
| 166 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 167 | ||
| 168 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 169 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 170 | ||
| 171 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 172 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 173 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 174 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 175 | ||
| 176 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 177 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 178 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
| 179 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
| 180 | #define QIXIS_BASE 0xffdf0000 | |
| 181 | #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) | |
| 182 | #define QIXIS_LBMAP_SWITCH 0x06 | |
| 183 | #define QIXIS_LBMAP_MASK 0x0f | |
| 184 | #define QIXIS_LBMAP_SHIFT 0 | |
| 185 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 186 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
| 187 | #define QIXIS_RST_CTL_RESET 0x31 | |
| 188 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 189 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 190 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 8c618dd6 | 191 | #define QIXIS_RST_FORCE_MEM 0x01 |
| 7d436078 PK |
192 | |
| 193 | #define CONFIG_SYS_CSPR3_EXT (0xf) | |
| 194 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
| 195 | | CSPR_PORT_SIZE_8 \ | |
| 196 | | CSPR_MSEL_GPCM \ | |
| 197 | | CSPR_V) | |
| 088d52cf | 198 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) |
| 7d436078 PK |
199 | #define CONFIG_SYS_CSOR3 0x0 |
| 200 | /* QIXIS Timing parameters for IFC CS3 */ | |
| 201 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 202 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 203 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 204 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
| 205 | FTIM1_GPCM_TRAD(0x3f)) | |
| 206 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| 562de1d6 | 207 | FTIM2_GPCM_TCH(0x8) | \ |
| 7d436078 PK |
208 | FTIM2_GPCM_TWP(0x1f)) |
| 209 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
| 210 | ||
| 211 | #define CONFIG_NAND_FSL_IFC | |
| 212 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 213 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
| 214 | ||
| 215 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
| 216 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 217 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 218 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 219 | | CSPR_V) | |
| 220 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 221 | ||
| 222 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 223 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 224 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 225 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
| 226 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
| 227 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
| 228 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 229 | ||
| 230 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 231 | ||
| 232 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 233 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
| 234 | FTIM0_NAND_TWP(0x18) | \ | |
| 235 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 236 | FTIM0_NAND_TWH(0x0a)) | |
| 237 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
| 238 | FTIM1_NAND_TWBE(0x39) | \ | |
| 239 | FTIM1_NAND_TRR(0x0e) | \ | |
| 240 | FTIM1_NAND_TRP(0x18)) | |
| 241 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 242 | FTIM2_NAND_TREH(0x0a) | \ | |
| 243 | FTIM2_NAND_TWHRE(0x1e)) | |
| 244 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 245 | ||
| 246 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
| 247 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 248 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 7d436078 PK |
249 | |
| 250 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| 251 | ||
| 88718be3 | 252 | #if defined(CONFIG_MTD_RAW_NAND) |
| 7d436078 PK |
253 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 254 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 255 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 256 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 257 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 258 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 259 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 260 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 261 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 262 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
| 263 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 264 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 265 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 266 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 267 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 268 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 269 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
| 270 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
| 271 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
| 272 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
| 273 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 274 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 275 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 276 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 277 | #else | |
| 278 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 279 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
| 280 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 281 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 282 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 283 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 284 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 285 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 286 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
| 287 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
| 288 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 289 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 290 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 291 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 292 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 293 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 294 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 295 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
| 296 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
| 297 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
| 298 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 299 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 300 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 301 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 302 | #endif | |
| 303 | ||
| 304 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
| 305 | ||
| 306 | #if defined(CONFIG_RAMBOOT_PBL) | |
| 307 | #define CONFIG_SYS_RAMBOOT | |
| 308 | #endif | |
| 309 | ||
| 7d436078 PK |
310 | #define CONFIG_HWCONFIG |
| 311 | ||
| 312 | /* define to use L1 as initial stack */ | |
| 313 | #define CONFIG_L1_INIT_RAM | |
| 314 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 315 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
| 316 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
| b3142e2c | 317 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
| 7d436078 PK |
318 | /* The assembler doesn't like typecast */ |
| 319 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
| 320 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
| 321 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
| 322 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
| 323 | ||
| 324 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 325 | GENERATED_GBL_DATA_SIZE) | |
| 326 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 327 | ||
| 9307cbab | 328 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 337b0c52 | 329 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
| 7d436078 PK |
330 | |
| 331 | /* Serial Port - controlled on board with jumper J8 | |
| 332 | * open - index 2 | |
| 333 | * shorted - index 1 | |
| 334 | */ | |
| 7d436078 PK |
335 | #define CONFIG_SYS_NS16550_SERIAL |
| 336 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 337 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
| 338 | ||
| 339 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 340 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 341 | ||
| 342 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
| 343 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
| 344 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
| 345 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
| 7d436078 | 346 | |
| 337b0c52 PJ |
347 | /* Video */ |
| 348 | #define CONFIG_FSL_DIU_FB | |
| 349 | #ifdef CONFIG_FSL_DIU_FB | |
| c53711bb | 350 | #define CONFIG_FSL_DIU_CH7301 |
| 337b0c52 | 351 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) |
| 337b0c52 PJ |
352 | #define CONFIG_VIDEO_LOGO |
| 353 | #define CONFIG_VIDEO_BMP_LOGO | |
| 354 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
| 355 | /* | |
| 356 | * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so | |
| 357 | * disable empty flash sector detection, which is I/O-intensive. | |
| 358 | */ | |
| 359 | #undef CONFIG_SYS_FLASH_EMPTY_INFO | |
| 360 | #endif | |
| 361 | ||
| 7d436078 PK |
362 | /* I2C */ |
| 363 | #define CONFIG_SYS_I2C | |
| 364 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ | |
| 2eb3ac7f | 365 | #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ |
| b0d97cd2 SL |
366 | #define CONFIG_SYS_FSL_I2C2_SPEED 50000 |
| 367 | #define CONFIG_SYS_FSL_I2C3_SPEED 50000 | |
| 368 | #define CONFIG_SYS_FSL_I2C4_SPEED 50000 | |
| 7d436078 | 369 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 7d436078 | 370 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| b0d97cd2 SL |
371 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F |
| 372 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
| 7d436078 | 373 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
| b0d97cd2 SL |
374 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
| 375 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
| 376 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
| 7d436078 PK |
377 | |
| 378 | #define I2C_MUX_PCA_ADDR 0x77 | |
| 379 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ | |
| 380 | ||
| 7d436078 PK |
381 | /* I2C bus multiplexer */ |
| 382 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| 337b0c52 PJ |
383 | #define I2C_MUX_CH_DIU 0xC |
| 384 | ||
| 385 | /* LDI/DVI Encoder for display */ | |
| 386 | #define CONFIG_SYS_I2C_LDI_ADDR 0x38 | |
| 387 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
| 7d436078 PK |
388 | |
| 389 | /* | |
| 390 | * RTC configuration | |
| 391 | */ | |
| 392 | #define RTC | |
| 393 | #define CONFIG_RTC_DS3231 1 | |
| 394 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 395 | ||
| 396 | /* | |
| 397 | * eSPI - Enhanced SPI | |
| 398 | */ | |
| 7d436078 PK |
399 | |
| 400 | /* | |
| 401 | * General PCI | |
| 402 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 403 | */ | |
| 404 | ||
| 405 | #ifdef CONFIG_PCI | |
| 406 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
| 407 | #ifdef CONFIG_PCIE1 | |
| 408 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
| 409 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
| 410 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
| 411 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
| 412 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
| 413 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 414 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
| 415 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 416 | #endif | |
| 417 | ||
| 418 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
| 419 | #ifdef CONFIG_PCIE2 | |
| 420 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 | |
| 421 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
| 422 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull | |
| 423 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
| 424 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
| 425 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 426 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
| 427 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
| 428 | #endif | |
| 429 | ||
| 430 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
| 431 | #ifdef CONFIG_PCIE3 | |
| 432 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 | |
| 433 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
| 434 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
| 435 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
| 436 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
| 437 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
| 438 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
| 439 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
| 440 | #endif | |
| 441 | ||
| 442 | /* controller 4, Base address 203000 */ | |
| 443 | #ifdef CONFIG_PCIE4 | |
| 444 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 | |
| 445 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
| 446 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull | |
| 447 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
| 448 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 | |
| 449 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
| 450 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
| 451 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
| 452 | #endif | |
| 453 | ||
| 7d436078 | 454 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 7d436078 PK |
455 | #endif /* CONFIG_PCI */ |
| 456 | ||
| 457 | /* SATA */ | |
| 458 | #define CONFIG_FSL_SATA_V2 | |
| 459 | #ifdef CONFIG_FSL_SATA_V2 | |
| 7d436078 PK |
460 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
| 461 | #define CONFIG_SATA1 | |
| 462 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 463 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 464 | #define CONFIG_SATA2 | |
| 465 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 466 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 467 | ||
| 468 | #define CONFIG_LBA48 | |
| 7d436078 PK |
469 | #endif |
| 470 | ||
| 471 | /* | |
| 472 | * USB | |
| 473 | */ | |
| 474 | #define CONFIG_HAS_FSL_DR_USB | |
| 475 | ||
| 476 | #ifdef CONFIG_HAS_FSL_DR_USB | |
| 8850c5d5 | 477 | #ifdef CONFIG_USB_EHCI_HCD |
| 7d436078 PK |
478 | #define CONFIG_USB_EHCI_FSL |
| 479 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 7d436078 PK |
480 | #endif |
| 481 | #endif | |
| 482 | ||
| 7d436078 | 483 | #ifdef CONFIG_MMC |
| 12486f38 | 484 | #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
| 7d436078 | 485 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| fa1e035e | 486 | #define CONFIG_FSL_ESDHC_ADAPTER_IDENT |
| 7d436078 PK |
487 | #endif |
| 488 | ||
| 489 | /* Qman/Bman */ | |
| 490 | #ifndef CONFIG_NOBQFMAN | |
| 2a8b3422 | 491 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
| 7d436078 PK |
492 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
| 493 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
| 494 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
495 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 496 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
| 497 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
| 498 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 499 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
| 500 | CONFIG_SYS_BMAN_CENA_SIZE) | |
| 501 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 502 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
| 2a8b3422 | 503 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
| 7d436078 PK |
504 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
| 505 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
| 506 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
507 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 508 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
| 509 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
| 510 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 511 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
| 512 | CONFIG_SYS_QMAN_CENA_SIZE) | |
| 513 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 514 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
| 7d436078 PK |
515 | |
| 516 | #define CONFIG_SYS_DPAA_FMAN | |
| 517 | #define CONFIG_SYS_DPAA_PME | |
| 518 | ||
| 519 | /* Default address of microcode for the Linux Fman driver */ | |
| 520 | #if defined(CONFIG_SPIFLASH) | |
| 521 | /* | |
| 522 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
| 523 | * env, so we got 0x110000. | |
| 524 | */ | |
| dcf1d774 | 525 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
| 7d436078 PK |
526 | #elif defined(CONFIG_SDCARD) |
| 527 | /* | |
| 528 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
| e222b1f3 PK |
529 | * about 825KB (1650 blocks), Env is stored after the image, and the env size is |
| 530 | * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. | |
| 7d436078 | 531 | */ |
| dcf1d774 | 532 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) |
| 88718be3 | 533 | #elif defined(CONFIG_MTD_RAW_NAND) |
| dcf1d774 | 534 | #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 7d436078 | 535 | #else |
| dcf1d774 | 536 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
| 6259e291 | 537 | #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 |
| 7d436078 PK |
538 | #endif |
| 539 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
| 540 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
| 541 | #endif /* CONFIG_NOBQFMAN */ | |
| 542 | ||
| 543 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| 7d436078 PK |
544 | #define CONFIG_PHYLIB_10G |
| 545 | #define CONFIG_PHY_VITESSE | |
| 546 | #define CONFIG_PHY_REALTEK | |
| 547 | #define CONFIG_PHY_TERANETICS | |
| 548 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | |
| 549 | #define SGMII_CARD_PORT2_PHY_ADDR 0x10 | |
| 550 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | |
| 551 | #define SGMII_CARD_PORT4_PHY_ADDR 0x11 | |
| 552 | #endif | |
| 553 | ||
| 554 | #ifdef CONFIG_FMAN_ENET | |
| 5b7672fc PK |
555 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 |
| 556 | #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 | |
| 7d436078 PK |
557 | |
| 558 | #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c | |
| 559 | #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d | |
| 560 | #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e | |
| 561 | #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f | |
| 562 | ||
| 7d436078 | 563 | #define CONFIG_ETHPRIME "FM1@DTSEC1" |
| 7d436078 PK |
564 | #endif |
| 565 | ||
| a83fccc2 CC |
566 | /* Enable VSC9953 L2 Switch driver */ |
| 567 | #define CONFIG_VSC9953 | |
| a83fccc2 CC |
568 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 |
| 569 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 | |
| 570 | ||
| 68b74739 PK |
571 | /* |
| 572 | * Dynamic MTD Partition support with mtdparts | |
| 573 | */ | |
| 68b74739 | 574 | |
| 7d436078 PK |
575 | /* |
| 576 | * Environment | |
| 577 | */ | |
| 578 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 579 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 580 | ||
| 7d436078 PK |
581 | /* |
| 582 | * Miscellaneous configurable options | |
| 583 | */ | |
| 7d436078 | 584 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 7d436078 PK |
585 | |
| 586 | /* | |
| 587 | * For booting Linux, the board info and command line data | |
| 588 | * have to be in the first 64 MB of memory, since this is | |
| 589 | * the maximum mapped by the Linux kernel during initialization. | |
| 590 | */ | |
| 591 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
| 592 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 593 | ||
| 594 | #ifdef CONFIG_CMD_KGDB | |
| 595 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 7d436078 PK |
596 | #endif |
| 597 | ||
| 598 | /* | |
| 599 | * Environment Configuration | |
| 600 | */ | |
| 601 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| 602 | #define CONFIG_BOOTFILE "uImage" | |
| 603 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
| 604 | ||
| 605 | /* default location for tftp and bootm */ | |
| 606 | #define CONFIG_LOADADDR 1000000 | |
| 607 | ||
| 7d436078 PK |
608 | #define __USB_PHY_TYPE utmi |
| 609 | ||
| 610 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 1b2af9b4 | 611 | "hwconfig=fsl_ddr:bank_intlv=auto;" \ |
| 7d436078 PK |
612 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ |
| 613 | "netdev=eth0\0" \ | |
| 337b0c52 | 614 | "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ |
| 7d436078 PK |
615 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 616 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
| 617 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
| 618 | "protect off $ubootaddr +$filesize && " \ | |
| 619 | "erase $ubootaddr +$filesize && " \ | |
| 620 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
| 621 | "protect on $ubootaddr +$filesize && " \ | |
| 622 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
| 623 | "consoledev=ttyS0\0" \ | |
| 624 | "ramdiskaddr=2000000\0" \ | |
| 625 | "ramdiskfile=t1040qds/ramdisk.uboot\0" \ | |
| b24a4f62 | 626 | "fdtaddr=1e00000\0" \ |
| 7d436078 | 627 | "fdtfile=t1040qds/t1040qds.dtb\0" \ |
| 3246584d | 628 | "bdev=sda3\0" |
| 7d436078 PK |
629 | |
| 630 | #define CONFIG_LINUX \ | |
| 631 | "setenv bootargs root=/dev/ram rw " \ | |
| 632 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 633 | "setenv ramdiskaddr 0x02000000;" \ | |
| 634 | "setenv fdtaddr 0x00c00000;" \ | |
| 635 | "setenv loadaddr 0x1000000;" \ | |
| 636 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 637 | ||
| 638 | #define CONFIG_HDBOOT \ | |
| 639 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 640 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 641 | "tftp $loadaddr $bootfile;" \ | |
| 642 | "tftp $fdtaddr $fdtfile;" \ | |
| 643 | "bootm $loadaddr - $fdtaddr" | |
| 644 | ||
| 645 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 646 | "setenv bootargs root=/dev/nfs rw " \ | |
| 647 | "nfsroot=$serverip:$rootpath " \ | |
| 648 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 649 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 650 | "tftp $loadaddr $bootfile;" \ | |
| 651 | "tftp $fdtaddr $fdtfile;" \ | |
| 652 | "bootm $loadaddr - $fdtaddr" | |
| 653 | ||
| 654 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 655 | "setenv bootargs root=/dev/ram rw " \ | |
| 656 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 657 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 658 | "tftp $loadaddr $bootfile;" \ | |
| 659 | "tftp $fdtaddr $fdtfile;" \ | |
| 660 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 661 | ||
| 662 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
| 663 | ||
| 7d436078 | 664 | #include <asm/fsl_secure_boot.h> |
| ef6c55a2 | 665 | |
| 7d436078 | 666 | #endif /* __CONFIG_H */ |