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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
062ef1a6 | 2 | /* |
83d290c5 | 3 | * Copyright 2014 Freescale Semiconductor, Inc. |
d2e3f7c6 | 4 | * Copyright 2020 NXP |
83d290c5 | 5 | */ |
062ef1a6 PJ |
6 | |
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
10 | /* | |
f4c3917a | 11 | * T104x RDB board configuration file |
062ef1a6 | 12 | */ |
9f074e67 PK |
13 | #include <asm/config_mpc85xx.h> |
14 | ||
062ef1a6 | 15 | #ifdef CONFIG_RAMBOOT_PBL |
aa36c84e | 16 | |
bef18454 | 17 | #ifndef CONFIG_NXP_ESBC |
18c01445 | 18 | #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg |
aa36c84e SG |
19 | #else |
20 | #define CONFIG_SYS_FSL_PBL_PBI \ | |
21 | $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg | |
22 | #endif | |
23 | ||
18c01445 | 24 | #define CONFIG_SPL_FLUSH_IMAGE |
18c01445 PK |
25 | #define CONFIG_SPL_PAD_TO 0x40000 |
26 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
27 | #ifdef CONFIG_SPL_BUILD | |
28 | #define CONFIG_SPL_SKIP_RELOCATE | |
29 | #define CONFIG_SPL_COMMON_INIT_DDR | |
30 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
d2e3f7c6 | 31 | #undef CONFIG_DM_I2C |
18c01445 PK |
32 | #endif |
33 | #define RESET_VECTOR_OFFSET 0x27FFC | |
34 | #define BOOT_PAGE_OFFSET 0x27000 | |
35 | ||
88718be3 | 36 | #ifdef CONFIG_MTD_RAW_NAND |
bef18454 | 37 | #ifdef CONFIG_NXP_ESBC |
aa36c84e SG |
38 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
39 | /* | |
40 | * HDR would be appended at end of image and copied to DDR along | |
41 | * with U-Boot image. | |
42 | */ | |
43 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ | |
44 | CONFIG_U_BOOT_HDR_SIZE) | |
45 | #else | |
18c01445 | 46 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
aa36c84e | 47 | #endif |
ce249d95 TY |
48 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 |
49 | #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 | |
18c01445 | 50 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) |
6fcddd09 | 51 | #ifdef CONFIG_TARGET_T1040RDB |
ec90ac73 ZQ |
52 | #define CONFIG_SYS_FSL_PBL_RCW \ |
53 | $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg | |
54 | #endif | |
55ed8ae3 | 55 | #ifdef CONFIG_TARGET_T1042RDB_PI |
ec90ac73 ZQ |
56 | #define CONFIG_SYS_FSL_PBL_RCW \ |
57 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg | |
58 | #endif | |
0167369c | 59 | #ifdef CONFIG_TARGET_T1042RDB |
ec90ac73 ZQ |
60 | #define CONFIG_SYS_FSL_PBL_RCW \ |
61 | $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg | |
62 | #endif | |
a016735c | 63 | #ifdef CONFIG_TARGET_T1040D4RDB |
ec90ac73 ZQ |
64 | #define CONFIG_SYS_FSL_PBL_RCW \ |
65 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg | |
66 | #endif | |
319ed24a | 67 | #ifdef CONFIG_TARGET_T1042D4RDB |
ec90ac73 ZQ |
68 | #define CONFIG_SYS_FSL_PBL_RCW \ |
69 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg | |
70 | #endif | |
18c01445 PK |
71 | #endif |
72 | ||
73 | #ifdef CONFIG_SPIFLASH | |
ce249d95 | 74 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
18c01445 PK |
75 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
76 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
ce249d95 TY |
77 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) |
78 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) | |
18c01445 | 79 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) |
18c01445 PK |
80 | #ifndef CONFIG_SPL_BUILD |
81 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
82 | #endif | |
6fcddd09 | 83 | #ifdef CONFIG_TARGET_T1040RDB |
ec90ac73 ZQ |
84 | #define CONFIG_SYS_FSL_PBL_RCW \ |
85 | $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg | |
86 | #endif | |
55ed8ae3 | 87 | #ifdef CONFIG_TARGET_T1042RDB_PI |
ec90ac73 ZQ |
88 | #define CONFIG_SYS_FSL_PBL_RCW \ |
89 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg | |
90 | #endif | |
0167369c | 91 | #ifdef CONFIG_TARGET_T1042RDB |
ec90ac73 ZQ |
92 | #define CONFIG_SYS_FSL_PBL_RCW \ |
93 | $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg | |
94 | #endif | |
a016735c | 95 | #ifdef CONFIG_TARGET_T1040D4RDB |
ec90ac73 ZQ |
96 | #define CONFIG_SYS_FSL_PBL_RCW \ |
97 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg | |
98 | #endif | |
319ed24a | 99 | #ifdef CONFIG_TARGET_T1042D4RDB |
ec90ac73 ZQ |
100 | #define CONFIG_SYS_FSL_PBL_RCW \ |
101 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg | |
102 | #endif | |
18c01445 PK |
103 | #endif |
104 | ||
105 | #ifdef CONFIG_SDCARD | |
ce249d95 | 106 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
18c01445 | 107 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
ce249d95 TY |
108 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) |
109 | #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) | |
18c01445 | 110 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) |
18c01445 PK |
111 | #ifndef CONFIG_SPL_BUILD |
112 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
113 | #endif | |
6fcddd09 | 114 | #ifdef CONFIG_TARGET_T1040RDB |
ec90ac73 ZQ |
115 | #define CONFIG_SYS_FSL_PBL_RCW \ |
116 | $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg | |
117 | #endif | |
55ed8ae3 | 118 | #ifdef CONFIG_TARGET_T1042RDB_PI |
ec90ac73 ZQ |
119 | #define CONFIG_SYS_FSL_PBL_RCW \ |
120 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg | |
121 | #endif | |
0167369c | 122 | #ifdef CONFIG_TARGET_T1042RDB |
ec90ac73 ZQ |
123 | #define CONFIG_SYS_FSL_PBL_RCW \ |
124 | $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg | |
125 | #endif | |
a016735c | 126 | #ifdef CONFIG_TARGET_T1040D4RDB |
ec90ac73 ZQ |
127 | #define CONFIG_SYS_FSL_PBL_RCW \ |
128 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg | |
129 | #endif | |
319ed24a | 130 | #ifdef CONFIG_TARGET_T1042D4RDB |
ec90ac73 ZQ |
131 | #define CONFIG_SYS_FSL_PBL_RCW \ |
132 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg | |
133 | #endif | |
18c01445 PK |
134 | #endif |
135 | ||
062ef1a6 PJ |
136 | #endif |
137 | ||
138 | /* High Level Configuration Options */ | |
062ef1a6 | 139 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
062ef1a6 | 140 | |
5303a3de TY |
141 | /* support deep sleep */ |
142 | #define CONFIG_DEEP_SLEEP | |
5303a3de | 143 | |
062ef1a6 PJ |
144 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
145 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
146 | #endif | |
147 | ||
148 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
51370d56 | 149 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
b38eaec5 RD |
150 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
151 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
152 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
153 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
062ef1a6 | 154 | |
062ef1a6 PJ |
155 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
156 | ||
062ef1a6 PJ |
157 | #define CONFIG_ENV_OVERWRITE |
158 | ||
062ef1a6 | 159 | #if defined(CONFIG_SPIFLASH) |
062ef1a6 | 160 | #elif defined(CONFIG_SDCARD) |
062ef1a6 | 161 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
88718be3 | 162 | #elif defined(CONFIG_MTD_RAW_NAND) |
bef18454 | 163 | #ifdef CONFIG_NXP_ESBC |
aa36c84e SG |
164 | #define CONFIG_RAMBOOT_NAND |
165 | #define CONFIG_BOOTSCRIPT_COPY_RAM | |
166 | #endif | |
062ef1a6 | 167 | #endif |
062ef1a6 PJ |
168 | |
169 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
170 | #define CONFIG_DDR_CLK_FREQ 66666666 | |
171 | ||
172 | /* | |
173 | * These can be toggled for performance analysis, otherwise use default. | |
174 | */ | |
175 | #define CONFIG_SYS_CACHE_STASHING | |
176 | #define CONFIG_BACKSIDE_L2_CACHE | |
177 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
178 | #define CONFIG_BTB /* toggle branch predition */ | |
179 | #define CONFIG_DDR_ECC | |
180 | #ifdef CONFIG_DDR_ECC | |
181 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
182 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
183 | #endif | |
184 | ||
185 | #define CONFIG_ENABLE_36BIT_PHYS | |
186 | ||
187 | #define CONFIG_ADDR_MAP | |
188 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
189 | ||
062ef1a6 PJ |
190 | /* |
191 | * Config the L3 Cache as L3 SRAM | |
192 | */ | |
193 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 | |
aa36c84e SG |
194 | /* |
195 | * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence | |
196 | * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address | |
197 | * (CONFIG_SYS_INIT_L3_VADDR) will be different. | |
198 | */ | |
199 | #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 | |
18c01445 | 200 | #define CONFIG_SYS_L3_SIZE 256 << 10 |
aa36c84e | 201 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) |
a09fea1d | 202 | #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) |
18c01445 PK |
203 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) |
204 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) | |
205 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
062ef1a6 PJ |
206 | |
207 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
208 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
209 | ||
210 | /* | |
211 | * DDR Setup | |
212 | */ | |
213 | #define CONFIG_VERY_BIG_RAM | |
214 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
215 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
216 | ||
062ef1a6 | 217 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
96ac18c9 | 218 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
062ef1a6 PJ |
219 | |
220 | #define CONFIG_DDR_SPD | |
062ef1a6 PJ |
221 | |
222 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
223 | #define SPD_EEPROM_ADDRESS 0x51 | |
224 | ||
225 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
226 | ||
227 | /* | |
228 | * IFC Definitions | |
229 | */ | |
230 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 | |
231 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
232 | ||
233 | #define CONFIG_SYS_NOR_CSPR_EXT (0xf) | |
234 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ | |
235 | CSPR_PORT_SIZE_16 | \ | |
236 | CSPR_MSEL_NOR | \ | |
237 | CSPR_V) | |
238 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
377ffcfa SS |
239 | |
240 | /* | |
241 | * TDM Definition | |
242 | */ | |
243 | #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 | |
244 | ||
062ef1a6 PJ |
245 | /* NOR Flash Timing Params */ |
246 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
247 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
248 | FTIM0_NOR_TEADC(0x5) | \ | |
249 | FTIM0_NOR_TEAHC(0x5)) | |
250 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
251 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
252 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
253 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
254 | FTIM2_NOR_TCH(0x4) | \ | |
255 | FTIM2_NOR_TWPH(0x0E) | \ | |
256 | FTIM2_NOR_TWP(0x1c)) | |
257 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
258 | ||
259 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
260 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
261 | ||
262 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
263 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
264 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
265 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
266 | ||
267 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
268 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
269 | ||
270 | /* CPLD on IFC */ | |
55153d6c PK |
271 | #define CPLD_LBMAP_MASK 0x3F |
272 | #define CPLD_BANK_SEL_MASK 0x07 | |
273 | #define CPLD_BANK_OVERRIDE 0x40 | |
274 | #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ | |
275 | #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ | |
276 | #define CPLD_LBMAP_RESET 0xFF | |
277 | #define CPLD_LBMAP_SHIFT 0x03 | |
4b6067ae | 278 | |
55ed8ae3 | 279 | #if defined(CONFIG_TARGET_T1042RDB_PI) |
cf8ddacf | 280 | #define CPLD_DIU_SEL_DFP 0x80 |
319ed24a | 281 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae PJ |
282 | #define CPLD_DIU_SEL_DFP 0xc0 |
283 | #endif | |
284 | ||
a016735c | 285 | #if defined(CONFIG_TARGET_T1040D4RDB) |
4b6067ae PJ |
286 | #define CPLD_INT_MASK_ALL 0xFF |
287 | #define CPLD_INT_MASK_THERM 0x80 | |
288 | #define CPLD_INT_MASK_DVI_DFP 0x40 | |
289 | #define CPLD_INT_MASK_QSGMII1 0x20 | |
290 | #define CPLD_INT_MASK_QSGMII2 0x10 | |
291 | #define CPLD_INT_MASK_SGMI1 0x08 | |
292 | #define CPLD_INT_MASK_SGMI2 0x04 | |
293 | #define CPLD_INT_MASK_TDMR1 0x02 | |
294 | #define CPLD_INT_MASK_TDMR2 0x01 | |
cf8ddacf | 295 | #endif |
55153d6c | 296 | |
062ef1a6 PJ |
297 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 |
298 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
9b444be3 | 299 | #define CONFIG_SYS_CSPR2_EXT (0xf) |
062ef1a6 PJ |
300 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ |
301 | | CSPR_PORT_SIZE_8 \ | |
302 | | CSPR_MSEL_GPCM \ | |
303 | | CSPR_V) | |
304 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
305 | #define CONFIG_SYS_CSOR2 0x0 | |
306 | /* CPLD Timing parameters for IFC CS2 */ | |
307 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
308 | FTIM0_GPCM_TEADC(0x0e) | \ | |
309 | FTIM0_GPCM_TEAHC(0x0e)) | |
310 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
311 | FTIM1_GPCM_TRAD(0x1f)) | |
312 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
de519163 | 313 | FTIM2_GPCM_TCH(0x8) | \ |
062ef1a6 PJ |
314 | FTIM2_GPCM_TWP(0x1f)) |
315 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
316 | ||
317 | /* NAND Flash on IFC */ | |
318 | #define CONFIG_NAND_FSL_IFC | |
319 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
320 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
321 | ||
322 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
323 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
324 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
325 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
326 | | CSPR_V) | |
327 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
328 | ||
329 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
330 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
331 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
332 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
333 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
334 | | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ | |
335 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
336 | ||
337 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
338 | ||
339 | /* ONFI NAND Flash mode0 Timing Params */ | |
340 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
341 | FTIM0_NAND_TWP(0x18) | \ | |
342 | FTIM0_NAND_TWCHT(0x07) | \ | |
343 | FTIM0_NAND_TWH(0x0a)) | |
344 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
345 | FTIM1_NAND_TWBE(0x39) | \ | |
346 | FTIM1_NAND_TRR(0x0e) | \ | |
347 | FTIM1_NAND_TRP(0x18)) | |
348 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
349 | FTIM2_NAND_TREH(0x0a) | \ | |
350 | FTIM2_NAND_TWHRE(0x1e)) | |
351 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
352 | ||
353 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
354 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
355 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
062ef1a6 PJ |
356 | |
357 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
358 | ||
88718be3 | 359 | #if defined(CONFIG_MTD_RAW_NAND) |
062ef1a6 PJ |
360 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
361 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
362 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
363 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
364 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
365 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
366 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
367 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
368 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT | |
369 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
370 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
371 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
372 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
373 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
374 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
375 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
376 | #else | |
377 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT | |
378 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR | |
379 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
380 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
381 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
382 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
383 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
384 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
385 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
386 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
387 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
388 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
389 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
390 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
391 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
392 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
393 | #endif | |
394 | ||
18c01445 PK |
395 | #ifdef CONFIG_SPL_BUILD |
396 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
397 | #else | |
398 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
399 | #endif | |
062ef1a6 PJ |
400 | |
401 | #if defined(CONFIG_RAMBOOT_PBL) | |
402 | #define CONFIG_SYS_RAMBOOT | |
403 | #endif | |
404 | ||
9f074e67 | 405 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 |
88718be3 | 406 | #if defined(CONFIG_MTD_RAW_NAND) |
9f074e67 PK |
407 | #define CONFIG_A008044_WORKAROUND |
408 | #endif | |
409 | #endif | |
410 | ||
062ef1a6 PJ |
411 | #define CONFIG_HWCONFIG |
412 | ||
413 | /* define to use L1 as initial stack */ | |
414 | #define CONFIG_L1_INIT_RAM | |
415 | #define CONFIG_SYS_INIT_RAM_LOCK | |
416 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
417 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
b3142e2c | 418 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
062ef1a6 PJ |
419 | /* The assembler doesn't like typecast */ |
420 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
421 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
422 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
423 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
424 | ||
425 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
426 | GENERATED_GBL_DATA_SIZE) | |
427 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
428 | ||
9307cbab | 429 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
062ef1a6 PJ |
430 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
431 | ||
432 | /* Serial Port - controlled on board with jumper J8 | |
433 | * open - index 2 | |
434 | * shorted - index 1 | |
435 | */ | |
062ef1a6 PJ |
436 | #define CONFIG_SYS_NS16550_SERIAL |
437 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
438 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
439 | ||
440 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
441 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
442 | ||
443 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
444 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
445 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
446 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
062ef1a6 | 447 | |
319ed24a | 448 | #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) |
cf8ddacf JJ |
449 | /* Video */ |
450 | #define CONFIG_FSL_DIU_FB | |
451 | ||
452 | #ifdef CONFIG_FSL_DIU_FB | |
453 | #define CONFIG_FSL_DIU_CH7301 | |
454 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) | |
cf8ddacf JJ |
455 | #define CONFIG_VIDEO_LOGO |
456 | #define CONFIG_VIDEO_BMP_LOGO | |
457 | #endif | |
458 | #endif | |
459 | ||
062ef1a6 | 460 | /* I2C */ |
d2e3f7c6 | 461 | #ifndef CONFIG_DM_I2C |
062ef1a6 | 462 | #define CONFIG_SYS_I2C |
062ef1a6 | 463 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ |
b0d97cd2 SL |
464 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
465 | #define CONFIG_SYS_FSL_I2C3_SPEED 400000 | |
466 | #define CONFIG_SYS_FSL_I2C4_SPEED 400000 | |
062ef1a6 | 467 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
062ef1a6 | 468 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
b0d97cd2 SL |
469 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F |
470 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
062ef1a6 | 471 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
b0d97cd2 SL |
472 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
473 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
474 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
d2e3f7c6 BL |
475 | #else |
476 | #define CONFIG_I2C_SET_DEFAULT_BUS_NUM | |
477 | #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 | |
478 | #endif | |
062ef1a6 | 479 | |
d2e3f7c6 | 480 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ |
062ef1a6 PJ |
481 | /* I2C bus multiplexer */ |
482 | #define I2C_MUX_PCA_ADDR 0x70 | |
483 | #define I2C_MUX_CH_DEFAULT 0x8 | |
f4c3917a | 484 | |
78e56995 YS |
485 | #if defined(CONFIG_TARGET_T1042RDB_PI) || \ |
486 | defined(CONFIG_TARGET_T1040D4RDB) || \ | |
487 | defined(CONFIG_TARGET_T1042D4RDB) | |
cf8ddacf JJ |
488 | /* LDI/DVI Encoder for display */ |
489 | #define CONFIG_SYS_I2C_LDI_ADDR 0x38 | |
490 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
d2e3f7c6 | 491 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 |
cf8ddacf | 492 | |
f4c3917a | 493 | /* |
494 | * RTC configuration | |
495 | */ | |
496 | #define RTC | |
497 | #define CONFIG_RTC_DS1337 1 | |
498 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
062ef1a6 | 499 | |
f4c3917a | 500 | /*DVI encoder*/ |
501 | #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 | |
502 | #endif | |
062ef1a6 PJ |
503 | |
504 | /* | |
505 | * eSPI - Enhanced SPI | |
506 | */ | |
062ef1a6 PJ |
507 | |
508 | /* | |
509 | * General PCI | |
510 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
511 | */ | |
512 | ||
513 | #ifdef CONFIG_PCI | |
514 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
515 | #ifdef CONFIG_PCIE1 | |
516 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
062ef1a6 | 517 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
062ef1a6 | 518 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
062ef1a6 | 519 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
062ef1a6 PJ |
520 | #endif |
521 | ||
522 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
523 | #ifdef CONFIG_PCIE2 | |
524 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 | |
062ef1a6 | 525 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull |
062ef1a6 | 526 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
062ef1a6 | 527 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
062ef1a6 PJ |
528 | #endif |
529 | ||
530 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
531 | #ifdef CONFIG_PCIE3 | |
532 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 | |
062ef1a6 | 533 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull |
062ef1a6 | 534 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
062ef1a6 | 535 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
062ef1a6 PJ |
536 | #endif |
537 | ||
538 | /* controller 4, Base address 203000 */ | |
539 | #ifdef CONFIG_PCIE4 | |
540 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 | |
062ef1a6 | 541 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull |
062ef1a6 | 542 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 |
062ef1a6 | 543 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
062ef1a6 PJ |
544 | #endif |
545 | ||
75974847 HZ |
546 | #if !defined(CONFIG_DM_PCI) |
547 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
548 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
549 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
550 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
551 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
552 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
553 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
554 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
555 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
556 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
557 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
558 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
559 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
560 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
561 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
562 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
563 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
564 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
565 | #endif | |
062ef1a6 | 566 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
062ef1a6 PJ |
567 | #endif /* CONFIG_PCI */ |
568 | ||
569 | /* SATA */ | |
570 | #define CONFIG_FSL_SATA_V2 | |
571 | #ifdef CONFIG_FSL_SATA_V2 | |
062ef1a6 PJ |
572 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
573 | #define CONFIG_SATA1 | |
574 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
575 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
576 | ||
577 | #define CONFIG_LBA48 | |
062ef1a6 PJ |
578 | #endif |
579 | ||
580 | /* | |
581 | * USB | |
582 | */ | |
583 | #define CONFIG_HAS_FSL_DR_USB | |
584 | ||
585 | #ifdef CONFIG_HAS_FSL_DR_USB | |
8850c5d5 | 586 | #ifdef CONFIG_USB_EHCI_HCD |
062ef1a6 PJ |
587 | #define CONFIG_USB_EHCI_FSL |
588 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
062ef1a6 PJ |
589 | #endif |
590 | #endif | |
591 | ||
062ef1a6 | 592 | #ifdef CONFIG_MMC |
062ef1a6 | 593 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
062ef1a6 PJ |
594 | #endif |
595 | ||
596 | /* Qman/Bman */ | |
597 | #ifndef CONFIG_NOBQFMAN | |
2a8b3422 | 598 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
062ef1a6 PJ |
599 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
600 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
601 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
602 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
603 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
604 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
605 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
606 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
607 | CONFIG_SYS_BMAN_CENA_SIZE) | |
608 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
609 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
2a8b3422 | 610 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
062ef1a6 PJ |
611 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
612 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
613 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
614 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
615 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
616 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
617 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
618 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
619 | CONFIG_SYS_QMAN_CENA_SIZE) | |
620 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
621 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
062ef1a6 PJ |
622 | |
623 | #define CONFIG_SYS_DPAA_FMAN | |
624 | #define CONFIG_SYS_DPAA_PME | |
625 | ||
59ff5d33 ZQ |
626 | #define CONFIG_U_QE |
627 | ||
062ef1a6 PJ |
628 | /* Default address of microcode for the Linux Fman driver */ |
629 | #if defined(CONFIG_SPIFLASH) | |
630 | /* | |
631 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
632 | * env, so we got 0x110000. | |
633 | */ | |
dcf1d774 | 634 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
062ef1a6 PJ |
635 | #elif defined(CONFIG_SDCARD) |
636 | /* | |
637 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
18c01445 PK |
638 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
639 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
062ef1a6 | 640 | */ |
18c01445 | 641 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
88718be3 | 642 | #elif defined(CONFIG_MTD_RAW_NAND) |
18c01445 | 643 | #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) |
062ef1a6 | 644 | #else |
dcf1d774 | 645 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
18c01445 PK |
646 | #endif |
647 | ||
18c01445 PK |
648 | #if defined(CONFIG_SPIFLASH) |
649 | #define CONFIG_SYS_QE_FW_ADDR 0x130000 | |
650 | #elif defined(CONFIG_SDCARD) | |
651 | #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) | |
88718be3 | 652 | #elif defined(CONFIG_MTD_RAW_NAND) |
18c01445 PK |
653 | #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) |
654 | #else | |
59ff5d33 | 655 | #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 |
062ef1a6 | 656 | #endif |
18c01445 | 657 | |
062ef1a6 PJ |
658 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
659 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
660 | #endif /* CONFIG_NOBQFMAN */ | |
661 | ||
062ef1a6 | 662 | #ifdef CONFIG_FMAN_ENET |
0167369c | 663 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) |
4b6067ae | 664 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 |
a016735c | 665 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
94af6842 | 666 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 |
319ed24a | 667 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae PJ |
668 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 |
669 | #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 | |
670 | #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 | |
671 | #endif | |
672 | ||
78e56995 | 673 | #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae PJ |
674 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 |
675 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 | |
676 | #else | |
677 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 | |
678 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 | |
f4c3917a | 679 | #endif |
062ef1a6 | 680 | |
db4a1767 | 681 | /* Enable VSC9953 L2 Switch driver on T1040 SoC */ |
6fcddd09 | 682 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) |
db4a1767 | 683 | #define CONFIG_VSC9953 |
6fcddd09 | 684 | #ifdef CONFIG_TARGET_T1040RDB |
db4a1767 CC |
685 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 |
686 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 | |
4b6067ae PJ |
687 | #else |
688 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 | |
689 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c | |
690 | #endif | |
db4a1767 CC |
691 | #endif |
692 | ||
714fd406 | 693 | #define CONFIG_ETHPRIME "FM1@DTSEC4" |
062ef1a6 PJ |
694 | #endif |
695 | ||
696 | /* | |
697 | * Environment | |
698 | */ | |
699 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
700 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
701 | ||
062ef1a6 PJ |
702 | /* |
703 | * Miscellaneous configurable options | |
704 | */ | |
062ef1a6 | 705 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
062ef1a6 PJ |
706 | |
707 | /* | |
708 | * For booting Linux, the board info and command line data | |
709 | * have to be in the first 64 MB of memory, since this is | |
710 | * the maximum mapped by the Linux kernel during initialization. | |
711 | */ | |
712 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
713 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
714 | ||
715 | #ifdef CONFIG_CMD_KGDB | |
716 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
062ef1a6 PJ |
717 | #endif |
718 | ||
68b74739 PK |
719 | /* |
720 | * Dynamic MTD Partition support with mtdparts | |
721 | */ | |
68b74739 | 722 | |
062ef1a6 PJ |
723 | /* |
724 | * Environment Configuration | |
725 | */ | |
726 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
727 | #define CONFIG_BOOTFILE "uImage" | |
728 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
729 | ||
730 | /* default location for tftp and bootm */ | |
731 | #define CONFIG_LOADADDR 1000000 | |
732 | ||
062ef1a6 | 733 | #define __USB_PHY_TYPE utmi |
363fb32a | 734 | #define RAMDISKFILE "t104xrdb/ramdisk.uboot" |
062ef1a6 | 735 | |
6fcddd09 | 736 | #ifdef CONFIG_TARGET_T1040RDB |
f4c3917a | 737 | #define FDTFILE "t1040rdb/t1040rdb.dtb" |
55ed8ae3 | 738 | #elif defined(CONFIG_TARGET_T1042RDB_PI) |
363fb32a | 739 | #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" |
0167369c | 740 | #elif defined(CONFIG_TARGET_T1042RDB) |
363fb32a | 741 | #define FDTFILE "t1042rdb/t1042rdb.dtb" |
a016735c | 742 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
4b6067ae | 743 | #define FDTFILE "t1042rdb/t1040d4rdb.dtb" |
319ed24a | 744 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae | 745 | #define FDTFILE "t1042rdb/t1042d4rdb.dtb" |
f4c3917a | 746 | #endif |
747 | ||
cf8ddacf JJ |
748 | #ifdef CONFIG_FSL_DIU_FB |
749 | #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" | |
750 | #else | |
751 | #define DIU_ENVIRONMENT | |
752 | #endif | |
753 | ||
062ef1a6 | 754 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
9b444be3 PJ |
755 | "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ |
756 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ | |
757 | "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
062ef1a6 | 758 | "netdev=eth0\0" \ |
cf8ddacf | 759 | "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ |
062ef1a6 PJ |
760 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
761 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
762 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
763 | "protect off $ubootaddr +$filesize && " \ | |
764 | "erase $ubootaddr +$filesize && " \ | |
765 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
766 | "protect on $ubootaddr +$filesize && " \ | |
767 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
768 | "consoledev=ttyS0\0" \ | |
769 | "ramdiskaddr=2000000\0" \ | |
f4c3917a | 770 | "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ |
b24a4f62 | 771 | "fdtaddr=1e00000\0" \ |
f4c3917a | 772 | "fdtfile=" __stringify(FDTFILE) "\0" \ |
3246584d | 773 | "bdev=sda3\0" |
062ef1a6 PJ |
774 | |
775 | #define CONFIG_LINUX \ | |
776 | "setenv bootargs root=/dev/ram rw " \ | |
777 | "console=$consoledev,$baudrate $othbootargs;" \ | |
778 | "setenv ramdiskaddr 0x02000000;" \ | |
779 | "setenv fdtaddr 0x00c00000;" \ | |
780 | "setenv loadaddr 0x1000000;" \ | |
781 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
782 | ||
783 | #define CONFIG_HDBOOT \ | |
784 | "setenv bootargs root=/dev/$bdev rw " \ | |
785 | "console=$consoledev,$baudrate $othbootargs;" \ | |
786 | "tftp $loadaddr $bootfile;" \ | |
787 | "tftp $fdtaddr $fdtfile;" \ | |
788 | "bootm $loadaddr - $fdtaddr" | |
789 | ||
790 | #define CONFIG_NFSBOOTCOMMAND \ | |
791 | "setenv bootargs root=/dev/nfs rw " \ | |
792 | "nfsroot=$serverip:$rootpath " \ | |
793 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
794 | "console=$consoledev,$baudrate $othbootargs;" \ | |
795 | "tftp $loadaddr $bootfile;" \ | |
796 | "tftp $fdtaddr $fdtfile;" \ | |
797 | "bootm $loadaddr - $fdtaddr" | |
798 | ||
799 | #define CONFIG_RAMBOOTCOMMAND \ | |
800 | "setenv bootargs root=/dev/ram rw " \ | |
801 | "console=$consoledev,$baudrate $othbootargs;" \ | |
802 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
803 | "tftp $loadaddr $bootfile;" \ | |
804 | "tftp $fdtaddr $fdtfile;" \ | |
805 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
806 | ||
807 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
808 | ||
062ef1a6 | 809 | #include <asm/fsl_secure_boot.h> |
ef6c55a2 | 810 | |
062ef1a6 | 811 | #endif /* __CONFIG_H */ |