projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 062ef1a6 | 2 | /* |
| 83d290c5 TR |
3 | * Copyright 2014 Freescale Semiconductor, Inc. |
| 4 | */ | |
| 062ef1a6 PJ |
5 | |
| 6 | #ifndef __CONFIG_H | |
| 7 | #define __CONFIG_H | |
| 8 | ||
| 9 | /* | |
| f4c3917a | 10 | * T104x RDB board configuration file |
| 062ef1a6 | 11 | */ |
| 9f074e67 PK |
12 | #include <asm/config_mpc85xx.h> |
| 13 | ||
| 062ef1a6 | 14 | #ifdef CONFIG_RAMBOOT_PBL |
| aa36c84e SG |
15 | |
| 16 | #ifndef CONFIG_SECURE_BOOT | |
| 18c01445 | 17 | #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg |
| aa36c84e SG |
18 | #else |
| 19 | #define CONFIG_SYS_FSL_PBL_PBI \ | |
| 20 | $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg | |
| 21 | #endif | |
| 22 | ||
| 18c01445 PK |
23 | #define CONFIG_SPL_FLUSH_IMAGE |
| 24 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 18c01445 PK |
25 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 |
| 26 | #define CONFIG_SPL_PAD_TO 0x40000 | |
| 27 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
| 28 | #ifdef CONFIG_SPL_BUILD | |
| 29 | #define CONFIG_SPL_SKIP_RELOCATE | |
| 30 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 31 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
| 18c01445 PK |
32 | #endif |
| 33 | #define RESET_VECTOR_OFFSET 0x27FFC | |
| 34 | #define BOOT_PAGE_OFFSET 0x27000 | |
| 35 | ||
| 36 | #ifdef CONFIG_NAND | |
| aa36c84e SG |
37 | #ifdef CONFIG_SECURE_BOOT |
| 38 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) | |
| 39 | /* | |
| 40 | * HDR would be appended at end of image and copied to DDR along | |
| 41 | * with U-Boot image. | |
| 42 | */ | |
| 43 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ | |
| 44 | CONFIG_U_BOOT_HDR_SIZE) | |
| 45 | #else | |
| 18c01445 | 46 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
| aa36c84e | 47 | #endif |
| ce249d95 TY |
48 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 |
| 49 | #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 | |
| 18c01445 PK |
50 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) |
| 51 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
| 6fcddd09 | 52 | #ifdef CONFIG_TARGET_T1040RDB |
| ec90ac73 ZQ |
53 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 54 | $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg | |
| 55 | #endif | |
| 55ed8ae3 | 56 | #ifdef CONFIG_TARGET_T1042RDB_PI |
| ec90ac73 ZQ |
57 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 58 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg | |
| 59 | #endif | |
| 0167369c | 60 | #ifdef CONFIG_TARGET_T1042RDB |
| ec90ac73 ZQ |
61 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 62 | $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg | |
| 63 | #endif | |
| a016735c | 64 | #ifdef CONFIG_TARGET_T1040D4RDB |
| ec90ac73 ZQ |
65 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 66 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg | |
| 67 | #endif | |
| 319ed24a | 68 | #ifdef CONFIG_TARGET_T1042D4RDB |
| ec90ac73 ZQ |
69 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 70 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg | |
| 71 | #endif | |
| 18c01445 PK |
72 | #define CONFIG_SPL_NAND_BOOT |
| 73 | #endif | |
| 74 | ||
| 75 | #ifdef CONFIG_SPIFLASH | |
| ce249d95 | 76 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
| 18c01445 PK |
77 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 78 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
| ce249d95 TY |
79 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) |
| 80 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) | |
| 18c01445 PK |
81 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) |
| 82 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
| 83 | #ifndef CONFIG_SPL_BUILD | |
| 84 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 85 | #endif | |
| 6fcddd09 | 86 | #ifdef CONFIG_TARGET_T1040RDB |
| ec90ac73 ZQ |
87 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 88 | $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg | |
| 89 | #endif | |
| 55ed8ae3 | 90 | #ifdef CONFIG_TARGET_T1042RDB_PI |
| ec90ac73 ZQ |
91 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 92 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg | |
| 93 | #endif | |
| 0167369c | 94 | #ifdef CONFIG_TARGET_T1042RDB |
| ec90ac73 ZQ |
95 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 96 | $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg | |
| 97 | #endif | |
| a016735c | 98 | #ifdef CONFIG_TARGET_T1040D4RDB |
| ec90ac73 ZQ |
99 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 100 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg | |
| 101 | #endif | |
| 319ed24a | 102 | #ifdef CONFIG_TARGET_T1042D4RDB |
| ec90ac73 ZQ |
103 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 104 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg | |
| 105 | #endif | |
| 18c01445 PK |
106 | #define CONFIG_SPL_SPI_BOOT |
| 107 | #endif | |
| 108 | ||
| 109 | #ifdef CONFIG_SDCARD | |
| ce249d95 | 110 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
| 18c01445 | 111 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| ce249d95 TY |
112 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) |
| 113 | #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) | |
| 18c01445 PK |
114 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) |
| 115 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
| 116 | #ifndef CONFIG_SPL_BUILD | |
| 117 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 118 | #endif | |
| 6fcddd09 | 119 | #ifdef CONFIG_TARGET_T1040RDB |
| ec90ac73 ZQ |
120 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 121 | $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg | |
| 122 | #endif | |
| 55ed8ae3 | 123 | #ifdef CONFIG_TARGET_T1042RDB_PI |
| ec90ac73 ZQ |
124 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 125 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg | |
| 126 | #endif | |
| 0167369c | 127 | #ifdef CONFIG_TARGET_T1042RDB |
| ec90ac73 ZQ |
128 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 129 | $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg | |
| 130 | #endif | |
| a016735c | 131 | #ifdef CONFIG_TARGET_T1040D4RDB |
| ec90ac73 ZQ |
132 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 133 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg | |
| 134 | #endif | |
| 319ed24a | 135 | #ifdef CONFIG_TARGET_T1042D4RDB |
| ec90ac73 ZQ |
136 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 137 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg | |
| 138 | #endif | |
| 18c01445 PK |
139 | #define CONFIG_SPL_MMC_BOOT |
| 140 | #endif | |
| 141 | ||
| 062ef1a6 PJ |
142 | #endif |
| 143 | ||
| 144 | /* High Level Configuration Options */ | |
| 062ef1a6 | 145 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
| 062ef1a6 PJ |
146 | #define CONFIG_MP /* support multiple processors */ |
| 147 | ||
| 5303a3de TY |
148 | /* support deep sleep */ |
| 149 | #define CONFIG_DEEP_SLEEP | |
| 5303a3de | 150 | |
| 062ef1a6 PJ |
151 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 152 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 153 | #endif | |
| 154 | ||
| 155 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
| 51370d56 | 156 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
| 062ef1a6 | 157 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| b38eaec5 RD |
158 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 159 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
| 160 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
| 161 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
| 062ef1a6 PJ |
162 | |
| 163 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
| 164 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
| 165 | ||
| 062ef1a6 PJ |
166 | #define CONFIG_ENV_OVERWRITE |
| 167 | ||
| e856bdcf | 168 | #ifdef CONFIG_MTD_NOR_FLASH |
| 062ef1a6 PJ |
169 | #define CONFIG_FLASH_CFI_DRIVER |
| 170 | #define CONFIG_SYS_FLASH_CFI | |
| 171 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 172 | #endif | |
| 173 | ||
| 062ef1a6 PJ |
174 | #if defined(CONFIG_SPIFLASH) |
| 175 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 062ef1a6 PJ |
176 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 177 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 178 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 179 | #elif defined(CONFIG_SDCARD) | |
| 180 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 062ef1a6 PJ |
181 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 182 | #define CONFIG_ENV_SIZE 0x2000 | |
| 18c01445 | 183 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
| 062ef1a6 | 184 | #elif defined(CONFIG_NAND) |
| aa36c84e SG |
185 | #ifdef CONFIG_SECURE_BOOT |
| 186 | #define CONFIG_RAMBOOT_NAND | |
| 187 | #define CONFIG_BOOTSCRIPT_COPY_RAM | |
| 188 | #endif | |
| 062ef1a6 | 189 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 18c01445 | 190 | #define CONFIG_ENV_SIZE 0x2000 |
| e222b1f3 | 191 | #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 062ef1a6 | 192 | #else |
| 062ef1a6 PJ |
193 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 194 | #define CONFIG_ENV_SIZE 0x2000 | |
| 195 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 196 | #endif | |
| 062ef1a6 PJ |
197 | |
| 198 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
| 199 | #define CONFIG_DDR_CLK_FREQ 66666666 | |
| 200 | ||
| 201 | /* | |
| 202 | * These can be toggled for performance analysis, otherwise use default. | |
| 203 | */ | |
| 204 | #define CONFIG_SYS_CACHE_STASHING | |
| 205 | #define CONFIG_BACKSIDE_L2_CACHE | |
| 206 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
| 207 | #define CONFIG_BTB /* toggle branch predition */ | |
| 208 | #define CONFIG_DDR_ECC | |
| 209 | #ifdef CONFIG_DDR_ECC | |
| 210 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 211 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 212 | #endif | |
| 213 | ||
| 214 | #define CONFIG_ENABLE_36BIT_PHYS | |
| 215 | ||
| 216 | #define CONFIG_ADDR_MAP | |
| 217 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
| 218 | ||
| 219 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
| 220 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| 062ef1a6 PJ |
221 | |
| 222 | /* | |
| 223 | * Config the L3 Cache as L3 SRAM | |
| 224 | */ | |
| 225 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 | |
| aa36c84e SG |
226 | /* |
| 227 | * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence | |
| 228 | * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address | |
| 229 | * (CONFIG_SYS_INIT_L3_VADDR) will be different. | |
| 230 | */ | |
| 231 | #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 | |
| 18c01445 | 232 | #define CONFIG_SYS_L3_SIZE 256 << 10 |
| aa36c84e | 233 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) |
| 18c01445 PK |
234 | #ifdef CONFIG_RAMBOOT_PBL |
| 235 | #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) | |
| 236 | #endif | |
| 237 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) | |
| 238 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) | |
| 239 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
| 240 | #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) | |
| 062ef1a6 PJ |
241 | |
| 242 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
| 243 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
| 244 | ||
| 245 | /* | |
| 246 | * DDR Setup | |
| 247 | */ | |
| 248 | #define CONFIG_VERY_BIG_RAM | |
| 249 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 250 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 251 | ||
| 062ef1a6 | 252 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 96ac18c9 | 253 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 062ef1a6 PJ |
254 | |
| 255 | #define CONFIG_DDR_SPD | |
| 062ef1a6 PJ |
256 | |
| 257 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
| 258 | #define SPD_EEPROM_ADDRESS 0x51 | |
| 259 | ||
| 260 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
| 261 | ||
| 262 | /* | |
| 263 | * IFC Definitions | |
| 264 | */ | |
| 265 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 | |
| 266 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
| 267 | ||
| 268 | #define CONFIG_SYS_NOR_CSPR_EXT (0xf) | |
| 269 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ | |
| 270 | CSPR_PORT_SIZE_16 | \ | |
| 271 | CSPR_MSEL_NOR | \ | |
| 272 | CSPR_V) | |
| 273 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 377ffcfa SS |
274 | |
| 275 | /* | |
| 276 | * TDM Definition | |
| 277 | */ | |
| 278 | #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 | |
| 279 | ||
| 062ef1a6 PJ |
280 | /* NOR Flash Timing Params */ |
| 281 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
| 282 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 283 | FTIM0_NOR_TEADC(0x5) | \ | |
| 284 | FTIM0_NOR_TEAHC(0x5)) | |
| 285 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 286 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
| 287 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 288 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 289 | FTIM2_NOR_TCH(0x4) | \ | |
| 290 | FTIM2_NOR_TWPH(0x0E) | \ | |
| 291 | FTIM2_NOR_TWP(0x1c)) | |
| 292 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 293 | ||
| 294 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 295 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 296 | ||
| 297 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 298 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 299 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 300 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 301 | ||
| 302 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 303 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
| 304 | ||
| 305 | /* CPLD on IFC */ | |
| 55153d6c PK |
306 | #define CPLD_LBMAP_MASK 0x3F |
| 307 | #define CPLD_BANK_SEL_MASK 0x07 | |
| 308 | #define CPLD_BANK_OVERRIDE 0x40 | |
| 309 | #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ | |
| 310 | #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ | |
| 311 | #define CPLD_LBMAP_RESET 0xFF | |
| 312 | #define CPLD_LBMAP_SHIFT 0x03 | |
| 4b6067ae | 313 | |
| 55ed8ae3 | 314 | #if defined(CONFIG_TARGET_T1042RDB_PI) |
| cf8ddacf | 315 | #define CPLD_DIU_SEL_DFP 0x80 |
| 319ed24a | 316 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
| 4b6067ae PJ |
317 | #define CPLD_DIU_SEL_DFP 0xc0 |
| 318 | #endif | |
| 319 | ||
| a016735c | 320 | #if defined(CONFIG_TARGET_T1040D4RDB) |
| 4b6067ae PJ |
321 | #define CPLD_INT_MASK_ALL 0xFF |
| 322 | #define CPLD_INT_MASK_THERM 0x80 | |
| 323 | #define CPLD_INT_MASK_DVI_DFP 0x40 | |
| 324 | #define CPLD_INT_MASK_QSGMII1 0x20 | |
| 325 | #define CPLD_INT_MASK_QSGMII2 0x10 | |
| 326 | #define CPLD_INT_MASK_SGMI1 0x08 | |
| 327 | #define CPLD_INT_MASK_SGMI2 0x04 | |
| 328 | #define CPLD_INT_MASK_TDMR1 0x02 | |
| 329 | #define CPLD_INT_MASK_TDMR2 0x01 | |
| cf8ddacf | 330 | #endif |
| 55153d6c | 331 | |
| 062ef1a6 PJ |
332 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 |
| 333 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
| 9b444be3 | 334 | #define CONFIG_SYS_CSPR2_EXT (0xf) |
| 062ef1a6 PJ |
335 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ |
| 336 | | CSPR_PORT_SIZE_8 \ | |
| 337 | | CSPR_MSEL_GPCM \ | |
| 338 | | CSPR_V) | |
| 339 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
| 340 | #define CONFIG_SYS_CSOR2 0x0 | |
| 341 | /* CPLD Timing parameters for IFC CS2 */ | |
| 342 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 343 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 344 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 345 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
| 346 | FTIM1_GPCM_TRAD(0x1f)) | |
| 347 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| de519163 | 348 | FTIM2_GPCM_TCH(0x8) | \ |
| 062ef1a6 PJ |
349 | FTIM2_GPCM_TWP(0x1f)) |
| 350 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
| 351 | ||
| 352 | /* NAND Flash on IFC */ | |
| 353 | #define CONFIG_NAND_FSL_IFC | |
| 354 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 355 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
| 356 | ||
| 357 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
| 358 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 359 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 360 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 361 | | CSPR_V) | |
| 362 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 363 | ||
| 364 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 365 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 366 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 367 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
| 368 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
| 369 | | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ | |
| 370 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 371 | ||
| 372 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 373 | ||
| 374 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 375 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
| 376 | FTIM0_NAND_TWP(0x18) | \ | |
| 377 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 378 | FTIM0_NAND_TWH(0x0a)) | |
| 379 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
| 380 | FTIM1_NAND_TWBE(0x39) | \ | |
| 381 | FTIM1_NAND_TRR(0x0e) | \ | |
| 382 | FTIM1_NAND_TRP(0x18)) | |
| 383 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 384 | FTIM2_NAND_TREH(0x0a) | \ | |
| 385 | FTIM2_NAND_TWHRE(0x1e)) | |
| 386 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 387 | ||
| 388 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
| 389 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 390 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 062ef1a6 PJ |
391 | |
| 392 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
| 393 | ||
| 394 | #if defined(CONFIG_NAND) | |
| 395 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 396 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 397 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 398 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 399 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 400 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 401 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 402 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 403 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT | |
| 404 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
| 405 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 406 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 407 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 408 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 409 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 410 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 411 | #else | |
| 412 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT | |
| 413 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR | |
| 414 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 415 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 416 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 417 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 418 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 419 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 420 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 421 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
| 422 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
| 423 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
| 424 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 425 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 426 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 427 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 428 | #endif | |
| 429 | ||
| 18c01445 PK |
430 | #ifdef CONFIG_SPL_BUILD |
| 431 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
| 432 | #else | |
| 433 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 434 | #endif | |
| 062ef1a6 PJ |
435 | |
| 436 | #if defined(CONFIG_RAMBOOT_PBL) | |
| 437 | #define CONFIG_SYS_RAMBOOT | |
| 438 | #endif | |
| 439 | ||
| 9f074e67 PK |
440 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 |
| 441 | #if defined(CONFIG_NAND) | |
| 442 | #define CONFIG_A008044_WORKAROUND | |
| 443 | #endif | |
| 444 | #endif | |
| 445 | ||
| 062ef1a6 PJ |
446 | #define CONFIG_MISC_INIT_R |
| 447 | ||
| 448 | #define CONFIG_HWCONFIG | |
| 449 | ||
| 450 | /* define to use L1 as initial stack */ | |
| 451 | #define CONFIG_L1_INIT_RAM | |
| 452 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 453 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
| 454 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
| b3142e2c | 455 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
| 062ef1a6 PJ |
456 | /* The assembler doesn't like typecast */ |
| 457 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
| 458 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
| 459 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
| 460 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
| 461 | ||
| 462 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 463 | GENERATED_GBL_DATA_SIZE) | |
| 464 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 465 | ||
| 9307cbab | 466 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 062ef1a6 PJ |
467 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
| 468 | ||
| 469 | /* Serial Port - controlled on board with jumper J8 | |
| 470 | * open - index 2 | |
| 471 | * shorted - index 1 | |
| 472 | */ | |
| 062ef1a6 PJ |
473 | #define CONFIG_SYS_NS16550_SERIAL |
| 474 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 475 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
| 476 | ||
| 477 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 478 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 479 | ||
| 480 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
| 481 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
| 482 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
| 483 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
| 062ef1a6 | 484 | |
| 319ed24a | 485 | #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) |
| cf8ddacf JJ |
486 | /* Video */ |
| 487 | #define CONFIG_FSL_DIU_FB | |
| 488 | ||
| 489 | #ifdef CONFIG_FSL_DIU_FB | |
| 490 | #define CONFIG_FSL_DIU_CH7301 | |
| 491 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) | |
| cf8ddacf JJ |
492 | #define CONFIG_VIDEO_LOGO |
| 493 | #define CONFIG_VIDEO_BMP_LOGO | |
| 494 | #endif | |
| 495 | #endif | |
| 496 | ||
| 062ef1a6 PJ |
497 | /* I2C */ |
| 498 | #define CONFIG_SYS_I2C | |
| 499 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ | |
| 500 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ | |
| b0d97cd2 SL |
501 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| 502 | #define CONFIG_SYS_FSL_I2C3_SPEED 400000 | |
| 503 | #define CONFIG_SYS_FSL_I2C4_SPEED 400000 | |
| 062ef1a6 | 504 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 062ef1a6 | 505 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| b0d97cd2 SL |
506 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F |
| 507 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
| 062ef1a6 | 508 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
| b0d97cd2 SL |
509 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
| 510 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
| 511 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
| 062ef1a6 PJ |
512 | |
| 513 | /* I2C bus multiplexer */ | |
| 514 | #define I2C_MUX_PCA_ADDR 0x70 | |
| 515 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| f4c3917a | 516 | |
| 78e56995 YS |
517 | #if defined(CONFIG_TARGET_T1042RDB_PI) || \ |
| 518 | defined(CONFIG_TARGET_T1040D4RDB) || \ | |
| 519 | defined(CONFIG_TARGET_T1042D4RDB) | |
| cf8ddacf JJ |
520 | /* LDI/DVI Encoder for display */ |
| 521 | #define CONFIG_SYS_I2C_LDI_ADDR 0x38 | |
| 522 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
| 523 | ||
| f4c3917a | 524 | /* |
| 525 | * RTC configuration | |
| 526 | */ | |
| 527 | #define RTC | |
| 528 | #define CONFIG_RTC_DS1337 1 | |
| 529 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 062ef1a6 | 530 | |
| f4c3917a | 531 | /*DVI encoder*/ |
| 532 | #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 | |
| 533 | #endif | |
| 062ef1a6 PJ |
534 | |
| 535 | /* | |
| 536 | * eSPI - Enhanced SPI | |
| 537 | */ | |
| 7172de33 | 538 | #define CONFIG_SPI_FLASH_BAR |
| 062ef1a6 PJ |
539 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 540 | #define CONFIG_SF_DEFAULT_MODE 0 | |
| 9b444be3 PJ |
541 | #define CONFIG_ENV_SPI_BUS 0 |
| 542 | #define CONFIG_ENV_SPI_CS 0 | |
| 543 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 544 | #define CONFIG_ENV_SPI_MODE 0 | |
| 062ef1a6 PJ |
545 | |
| 546 | /* | |
| 547 | * General PCI | |
| 548 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 549 | */ | |
| 550 | ||
| 551 | #ifdef CONFIG_PCI | |
| 552 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
| 553 | #ifdef CONFIG_PCIE1 | |
| 554 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
| 555 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
| 556 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
| 557 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
| 558 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
| 559 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 560 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
| 561 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 562 | #endif | |
| 563 | ||
| 564 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
| 565 | #ifdef CONFIG_PCIE2 | |
| 566 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 | |
| 567 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
| 568 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull | |
| 569 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
| 570 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
| 571 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 572 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
| 573 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
| 574 | #endif | |
| 575 | ||
| 576 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
| 577 | #ifdef CONFIG_PCIE3 | |
| 578 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 | |
| 579 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
| 580 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
| 581 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
| 582 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
| 583 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
| 584 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
| 585 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
| 586 | #endif | |
| 587 | ||
| 588 | /* controller 4, Base address 203000 */ | |
| 589 | #ifdef CONFIG_PCIE4 | |
| 590 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 | |
| 591 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
| 592 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull | |
| 593 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
| 594 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 | |
| 595 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
| 596 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
| 597 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
| 598 | #endif | |
| 599 | ||
| 062ef1a6 | 600 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 062ef1a6 PJ |
601 | #endif /* CONFIG_PCI */ |
| 602 | ||
| 603 | /* SATA */ | |
| 604 | #define CONFIG_FSL_SATA_V2 | |
| 605 | #ifdef CONFIG_FSL_SATA_V2 | |
| 062ef1a6 PJ |
606 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
| 607 | #define CONFIG_SATA1 | |
| 608 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 609 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 610 | ||
| 611 | #define CONFIG_LBA48 | |
| 062ef1a6 PJ |
612 | #endif |
| 613 | ||
| 614 | /* | |
| 615 | * USB | |
| 616 | */ | |
| 617 | #define CONFIG_HAS_FSL_DR_USB | |
| 618 | ||
| 619 | #ifdef CONFIG_HAS_FSL_DR_USB | |
| 8850c5d5 | 620 | #ifdef CONFIG_USB_EHCI_HCD |
| 062ef1a6 PJ |
621 | #define CONFIG_USB_EHCI_FSL |
| 622 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| e6a727ff | 623 | #define CONFIG_EHCI_DESC_BIG_ENDIAN |
| 062ef1a6 PJ |
624 | #endif |
| 625 | #endif | |
| 626 | ||
| 062ef1a6 | 627 | #ifdef CONFIG_MMC |
| 062ef1a6 | 628 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 062ef1a6 PJ |
629 | #endif |
| 630 | ||
| 631 | /* Qman/Bman */ | |
| 632 | #ifndef CONFIG_NOBQFMAN | |
| 2a8b3422 | 633 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
| 062ef1a6 PJ |
634 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
| 635 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
| 636 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
637 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 638 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
| 639 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
| 640 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 641 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
| 642 | CONFIG_SYS_BMAN_CENA_SIZE) | |
| 643 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 644 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
| 2a8b3422 | 645 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
| 062ef1a6 PJ |
646 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
| 647 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
| 648 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
649 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 650 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
| 651 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
| 652 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 653 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
| 654 | CONFIG_SYS_QMAN_CENA_SIZE) | |
| 655 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 656 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
| 062ef1a6 PJ |
657 | |
| 658 | #define CONFIG_SYS_DPAA_FMAN | |
| 659 | #define CONFIG_SYS_DPAA_PME | |
| 660 | ||
| 59ff5d33 ZQ |
661 | #define CONFIG_QE |
| 662 | #define CONFIG_U_QE | |
| 663 | ||
| 062ef1a6 PJ |
664 | /* Default address of microcode for the Linux Fman driver */ |
| 665 | #if defined(CONFIG_SPIFLASH) | |
| 666 | /* | |
| 667 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
| 668 | * env, so we got 0x110000. | |
| 669 | */ | |
| 670 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
| dcf1d774 | 671 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
| 062ef1a6 PJ |
672 | #elif defined(CONFIG_SDCARD) |
| 673 | /* | |
| 674 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
| 18c01445 PK |
675 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
| 676 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
| 062ef1a6 PJ |
677 | */ |
| 678 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
| 18c01445 | 679 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
| 062ef1a6 PJ |
680 | #elif defined(CONFIG_NAND) |
| 681 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
| 18c01445 | 682 | #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 062ef1a6 PJ |
683 | #else |
| 684 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
| dcf1d774 | 685 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
| 18c01445 PK |
686 | #endif |
| 687 | ||
| 18c01445 PK |
688 | #if defined(CONFIG_SPIFLASH) |
| 689 | #define CONFIG_SYS_QE_FW_ADDR 0x130000 | |
| 690 | #elif defined(CONFIG_SDCARD) | |
| 691 | #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) | |
| 692 | #elif defined(CONFIG_NAND) | |
| 693 | #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
| 694 | #else | |
| 59ff5d33 | 695 | #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 |
| 062ef1a6 | 696 | #endif |
| 18c01445 | 697 | |
| 062ef1a6 PJ |
698 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 699 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
| 700 | #endif /* CONFIG_NOBQFMAN */ | |
| 701 | ||
| 702 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| 703 | #define CONFIG_FMAN_ENET | |
| 704 | #define CONFIG_PHY_VITESSE | |
| 705 | #define CONFIG_PHY_REALTEK | |
| 706 | #endif | |
| 707 | ||
| 708 | #ifdef CONFIG_FMAN_ENET | |
| 0167369c | 709 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) |
| 4b6067ae | 710 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 |
| a016735c | 711 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
| 94af6842 | 712 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 |
| 319ed24a | 713 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
| 4b6067ae PJ |
714 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 |
| 715 | #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 | |
| 716 | #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 | |
| 717 | #endif | |
| 718 | ||
| 78e56995 | 719 | #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) |
| 4b6067ae PJ |
720 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 |
| 721 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 | |
| 722 | #else | |
| 723 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 | |
| 724 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 | |
| f4c3917a | 725 | #endif |
| 062ef1a6 | 726 | |
| db4a1767 | 727 | /* Enable VSC9953 L2 Switch driver on T1040 SoC */ |
| 6fcddd09 | 728 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) |
| db4a1767 | 729 | #define CONFIG_VSC9953 |
| 6fcddd09 | 730 | #ifdef CONFIG_TARGET_T1040RDB |
| db4a1767 CC |
731 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 |
| 732 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 | |
| 4b6067ae PJ |
733 | #else |
| 734 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 | |
| 735 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c | |
| 736 | #endif | |
| db4a1767 CC |
737 | #endif |
| 738 | ||
| 062ef1a6 | 739 | #define CONFIG_MII /* MII PHY management */ |
| 714fd406 | 740 | #define CONFIG_ETHPRIME "FM1@DTSEC4" |
| 062ef1a6 PJ |
741 | #endif |
| 742 | ||
| 743 | /* | |
| 744 | * Environment | |
| 745 | */ | |
| 746 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 747 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 748 | ||
| 062ef1a6 PJ |
749 | /* |
| 750 | * Miscellaneous configurable options | |
| 751 | */ | |
| 062ef1a6 | 752 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 062ef1a6 PJ |
753 | |
| 754 | /* | |
| 755 | * For booting Linux, the board info and command line data | |
| 756 | * have to be in the first 64 MB of memory, since this is | |
| 757 | * the maximum mapped by the Linux kernel during initialization. | |
| 758 | */ | |
| 759 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
| 760 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 761 | ||
| 762 | #ifdef CONFIG_CMD_KGDB | |
| 763 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 062ef1a6 PJ |
764 | #endif |
| 765 | ||
| 68b74739 PK |
766 | /* |
| 767 | * Dynamic MTD Partition support with mtdparts | |
| 768 | */ | |
| e856bdcf | 769 | #ifdef CONFIG_MTD_NOR_FLASH |
| 68b74739 PK |
770 | #define CONFIG_MTD_DEVICE |
| 771 | #define CONFIG_MTD_PARTITIONS | |
| 68b74739 | 772 | #define CONFIG_FLASH_CFI_MTD |
| 68b74739 PK |
773 | #endif |
| 774 | ||
| 062ef1a6 PJ |
775 | /* |
| 776 | * Environment Configuration | |
| 777 | */ | |
| 778 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| 779 | #define CONFIG_BOOTFILE "uImage" | |
| 780 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
| 781 | ||
| 782 | /* default location for tftp and bootm */ | |
| 783 | #define CONFIG_LOADADDR 1000000 | |
| 784 | ||
| 062ef1a6 | 785 | #define __USB_PHY_TYPE utmi |
| 363fb32a | 786 | #define RAMDISKFILE "t104xrdb/ramdisk.uboot" |
| 062ef1a6 | 787 | |
| 6fcddd09 | 788 | #ifdef CONFIG_TARGET_T1040RDB |
| f4c3917a | 789 | #define FDTFILE "t1040rdb/t1040rdb.dtb" |
| 55ed8ae3 | 790 | #elif defined(CONFIG_TARGET_T1042RDB_PI) |
| 363fb32a | 791 | #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" |
| 0167369c | 792 | #elif defined(CONFIG_TARGET_T1042RDB) |
| 363fb32a | 793 | #define FDTFILE "t1042rdb/t1042rdb.dtb" |
| a016735c | 794 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
| 4b6067ae | 795 | #define FDTFILE "t1042rdb/t1040d4rdb.dtb" |
| 319ed24a | 796 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
| 4b6067ae | 797 | #define FDTFILE "t1042rdb/t1042d4rdb.dtb" |
| f4c3917a | 798 | #endif |
| 799 | ||
| cf8ddacf JJ |
800 | #ifdef CONFIG_FSL_DIU_FB |
| 801 | #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" | |
| 802 | #else | |
| 803 | #define DIU_ENVIRONMENT | |
| 804 | #endif | |
| 805 | ||
| 062ef1a6 | 806 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 9b444be3 PJ |
807 | "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ |
| 808 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ | |
| 809 | "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
| 062ef1a6 | 810 | "netdev=eth0\0" \ |
| cf8ddacf | 811 | "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ |
| 062ef1a6 PJ |
812 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 813 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
| 814 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
| 815 | "protect off $ubootaddr +$filesize && " \ | |
| 816 | "erase $ubootaddr +$filesize && " \ | |
| 817 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
| 818 | "protect on $ubootaddr +$filesize && " \ | |
| 819 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
| 820 | "consoledev=ttyS0\0" \ | |
| 821 | "ramdiskaddr=2000000\0" \ | |
| f4c3917a | 822 | "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ |
| b24a4f62 | 823 | "fdtaddr=1e00000\0" \ |
| f4c3917a | 824 | "fdtfile=" __stringify(FDTFILE) "\0" \ |
| 3246584d | 825 | "bdev=sda3\0" |
| 062ef1a6 PJ |
826 | |
| 827 | #define CONFIG_LINUX \ | |
| 828 | "setenv bootargs root=/dev/ram rw " \ | |
| 829 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 830 | "setenv ramdiskaddr 0x02000000;" \ | |
| 831 | "setenv fdtaddr 0x00c00000;" \ | |
| 832 | "setenv loadaddr 0x1000000;" \ | |
| 833 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 834 | ||
| 835 | #define CONFIG_HDBOOT \ | |
| 836 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 837 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 838 | "tftp $loadaddr $bootfile;" \ | |
| 839 | "tftp $fdtaddr $fdtfile;" \ | |
| 840 | "bootm $loadaddr - $fdtaddr" | |
| 841 | ||
| 842 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 843 | "setenv bootargs root=/dev/nfs rw " \ | |
| 844 | "nfsroot=$serverip:$rootpath " \ | |
| 845 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 846 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 847 | "tftp $loadaddr $bootfile;" \ | |
| 848 | "tftp $fdtaddr $fdtfile;" \ | |
| 849 | "bootm $loadaddr - $fdtaddr" | |
| 850 | ||
| 851 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 852 | "setenv bootargs root=/dev/ram rw " \ | |
| 853 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 854 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 855 | "tftp $loadaddr $bootfile;" \ | |
| 856 | "tftp $fdtaddr $fdtfile;" \ | |
| 857 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 858 | ||
| 859 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
| 860 | ||
| 062ef1a6 | 861 | #include <asm/fsl_secure_boot.h> |
| ef6c55a2 | 862 | |
| 062ef1a6 | 863 | #endif /* __CONFIG_H */ |