[thirdparty/u-boot.git] / include / configs / T208xRDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2020-2021 NXP
 */

/*
 * T2080 RDB/PCIe board configuration file
 */

#ifndef __T2080RDB_H
#define __T2080RDB_H

#include <linux/stringify.h>

#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
#define CONFIG_FSL_SATA_V2

/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
#define CONFIG_ENABLE_36BIT_PHYS

#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS

#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET		0x27FFC
#define BOOT_PAGE_OFFSET		0x27000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif

#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif

#ifdef CONFIG_SPIFLASH
#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif

#ifdef CONFIG_SDCARD
#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
#define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
#define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif

#endif /* CONFIG_RAMBOOT_PBL */

#define CONFIG_SRIO_PCIE_BOOT_MASTER
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_SYS_CACHE_STASHING
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif

/*
 * Config the L3 Cache as L3 SRAM
 */
#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
#define CONFIG_SYS_L3_SIZE		(512 << 10)
#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)

#define CONFIG_SYS_DCSRBAR	0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM	0

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SPD_BUS_NUM	0
#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1	0x51
#define SPD_EEPROM_ADDRESS2	0x52
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
#define CTRL_INTLV_PREFERED	cacheline

/*
 * IFC Definitions
 */
#define CONFIG_SYS_FLASH_BASE		0xe8000000
#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80

#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1A) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x0

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS }

/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE	0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT	(0xf)
#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR2	0x0

/* CPLD Timing parameters for IFC CS2 */
#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
					FTIM2_GPCM_TCH(0x8) | \
					FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3		0x0

/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE		0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)

#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)

#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)    | \
					FTIM0_NAND_TWCHT(0x07)  | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)   | \
					FTIM1_NAND_TRR(0x0e)    | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
					FTIM2_NAND_TREH(0x0a)   | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_DDR_LAW		11
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_HWCONFIG

/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)

/*
 * I2C
 */

#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
#define I2C_MUX_CH_DEFAULT	0x8

#define I2C_MUX_CH_VOL_MONITOR	0xa

/* The lowest and highest voltage allowed for T208xRDB */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

/*
 * RapidIO
 */
#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
/*
 * for slave u-boot IMAGE instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
 * for slave UCODE and ENV instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */

/* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */

/*
 * SRIO_PCIE_BOOT - SLAVE
 */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif

/*
 * eSPI - Enhanced SPI
 */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */
#define CONFIG_PCIE3		/* PCIE controller 3 */
#define CONFIG_PCIE4		/* PCIE controller 4 */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull

/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#endif

/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_BMAN_NUM_PORTALS	18
#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
					CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS	18
#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
					CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08

#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
#define CONFIG_SYS_PMAN
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN		/* RMan */
#define CONFIG_SYS_INTERLAKEN

#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR		0x01  /* RealTek RTL8211E */
#define RGMII_PHY2_ADDR		0x02
#define CORTINA_PHY_ADDR1	0x0c  /* Cortina CS4315 */
#define CORTINA_PHY_ADDR2	0x0d
/* Aquantia AQ1202 10G Base-T used by board revisions up to C */
#define FM1_10GEC3_PHY_ADDR	0x00
#define FM1_10GEC4_PHY_ADDR	0x01
/* Aquantia AQR113C 10G Base-T used by board revisions D and up */
#define AQR113C_PHY_ADDR1	0x00
#define AQR113C_PHY_ADDR2	0x08
#endif

/*
 * SATA
 */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
#define CONFIG_LBA48
#endif

/*
 * USB
 */
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
#endif

/*
 * SDHC
 */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif

/*
 * Dynamic MTD Partition support with mtdparts
 */

/*
 * Environment
 */

/*
 * Miscellaneous configurable options
 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH	 "/opt/nfsroot"
#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */

#define __USB_PHY_TYPE		utmi

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"hwconfig=fsl_ddr:"					\
	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
	"bank_intlv=auto;"					\
	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
	"protect off $ubootaddr +$filesize && "			\
	"erase $ubootaddr +$filesize && "			\
	"cp.b $loadaddr $ubootaddr $filesize && "		\
	"protect on $ubootaddr +$filesize && "			\
	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
	"consoledev=ttyS0\0"					\
	"ramdiskaddr=2000000\0"					\
	"ramdiskfile=t2080rdb/ramdisk.uboot\0"			\
	"fdtaddr=1e00000\0"					\
	"fdtfile=t2080rdb/t2080rdb.dtb\0"			\
	"bdev=sda3\0"

/*
 * For emulation this causes u-boot to jump to the start of the
 * proof point app code automatically
 */
#define PROOF_POINTS				\
	"setenv bootargs root=/dev/$bdev rw "		\
	"console=$consoledev,$baudrate $othbootargs;"	\
	"cpu 1 release 0x29000000 - - -;"		\
	"cpu 2 release 0x29000000 - - -;"		\
	"cpu 3 release 0x29000000 - - -;"		\
	"cpu 4 release 0x29000000 - - -;"		\
	"cpu 5 release 0x29000000 - - -;"		\
	"cpu 6 release 0x29000000 - - -;"		\
	"cpu 7 release 0x29000000 - - -;"		\
	"go 0x29000000"

#define HVBOOT				\
	"setenv bootargs config-addr=0x60000000; "	\
	"bootm 0x01000000 - 0x00f00000"

#define ALU				\
	"setenv bootargs root=/dev/$bdev rw "		\
	"console=$consoledev,$baudrate $othbootargs;"	\
	"cpu 1 release 0x01000000 - - -;"		\
	"cpu 2 release 0x01000000 - - -;"		\
	"cpu 3 release 0x01000000 - - -;"		\
	"cpu 4 release 0x01000000 - - -;"		\
	"cpu 5 release 0x01000000 - - -;"		\
	"cpu 6 release 0x01000000 - - -;"		\
	"cpu 7 release 0x01000000 - - -;"		\
	"go 0x01000000"

#include <asm/fsl_secure_boot.h>

#endif	/* __T2080RDB_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
8d67c368 SL	2	/*
8d67c368 SL	3	* Copyright 2014 Freescale Semiconductor, Inc.
34f39ce8	4	* Copyright 2020-2021 NXP
8d67c368 SL	5	*/
	6
	7	/*
	8	* T2080 RDB/PCIe board configuration file
	9	*/
	10
	11	#ifndef __T2080RDB_H
	12	#define __T2080RDB_H
	13
1af3c7f4 SG	14	#include <linux/stringify.h>
1af3c7f4 SG	15
8d67c368	16	#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
8d67c368 SL	17	#define CONFIG_FSL_SATA_V2
	18
	19	/* High Level Configuration Options */
8d67c368	20	#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
8d67c368 SL	21	#define CONFIG_ENABLE_36BIT_PHYS
8d67c368 SL	22
8d67c368	23	#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
51370d56	24	#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
8d67c368 SL	25
8d67c368 SL	26	#ifdef CONFIG_RAMBOOT_PBL
4d666683 SL	27	#define RESET_VECTOR_OFFSET 0x27FFC
	28	#define BOOT_PAGE_OFFSET 0x27000
	29	#ifdef CONFIG_SPL_BUILD
4d666683 SL	30	#define CONFIG_SPL_COMMON_INIT_DDR
4d666683 SL	31	#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
4d666683 SL	32	#endif
4d666683 SL	33
88718be3	34	#ifdef CONFIG_MTD_RAW_NAND
4d666683 SL	35	#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
	36	#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
	37	#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
ab37df9d T	38	#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
	39	#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	40	#endif
4d666683 SL	41	#endif
	42
	43	#ifdef CONFIG_SPIFLASH
	44	#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
4d666683 SL	45	#define CONFIG_SPL_SPI_FLASH_MINIMAL
	46	#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
	47	#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
	48	#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
	49	#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
4d666683 SL	50	#ifndef CONFIG_SPL_BUILD
	51	#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	52	#endif
4d666683 SL	53	#endif
	54
	55	#ifdef CONFIG_SDCARD
	56	#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
4d666683 SL	57	#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
	58	#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
	59	#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
	60	#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
4d666683 SL	61	#ifndef CONFIG_SPL_BUILD
	62	#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	63	#endif
8d67c368 SL	64	#endif
8d67c368 SL	65
4d666683 SL	66	#endif /* CONFIG_RAMBOOT_PBL */
4d666683 SL	67
8d67c368 SL	68	#define CONFIG_SRIO_PCIE_BOOT_MASTER
	69	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
	70	/* Set 1M boot space */
	71	#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
	72	#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
	73	(0x300000000ull \| CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
	74	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
8d67c368 SL	75	#endif
8d67c368 SL	76
8d67c368 SL	77	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	78	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	79	#endif
	80
	81	/*
	82	* These can be toggled for performance analysis, otherwise use default.
	83	*/
	84	#define CONFIG_SYS_CACHE_STASHING
8d67c368	85	#ifdef CONFIG_DDR_ECC
8d67c368 SL	86	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	87	#endif
	88
8d67c368 SL	89	/*
	90	* Config the L3 Cache as L3 SRAM
	91	*/
4d666683 SL	92	#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
	93	#define CONFIG_SYS_L3_SIZE (512 << 10)
	94	#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
a09fea1d	95	#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
4d666683 SL	96	#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
	97	#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
	98	#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
8d67c368 SL	99
	100	#define CONFIG_SYS_DCSRBAR 0xf0000000
	101	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
	102
	103	/* EEPROM */
8d67c368 SL	104	#define CONFIG_SYS_I2C_EEPROM_NXID
8d67c368 SL	105	#define CONFIG_SYS_EEPROM_BUS_NUM 0
8d67c368 SL	106
	107	/*
	108	* DDR Setup
	109	*/
	110	#define CONFIG_VERY_BIG_RAM
	111	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	112	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
8d67c368 SL	113	#define CONFIG_SYS_SPD_BUS_NUM 0
	114	#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
	115	#define SPD_EEPROM_ADDRESS1 0x51
	116	#define SPD_EEPROM_ADDRESS2 0x52
	117	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
	118	#define CTRL_INTLV_PREFERED cacheline
	119
	120	/*
	121	* IFC Definitions
	122	*/
	123	#define CONFIG_SYS_FLASH_BASE 0xe8000000
	124	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_FLASH_BASE)
	125	#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
	126	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	127	CSPR_PORT_SIZE_16 \| \
	128	CSPR_MSEL_NOR \| \
	129	CSPR_V)
	130	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	131
	132	/* NOR Flash Timing Params */
	133	#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
	134
	135	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	136	FTIM0_NOR_TEADC(0x5) \| \
	137	FTIM0_NOR_TEAHC(0x5))
	138	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	139	FTIM1_NOR_TRAD_NOR(0x1A) \|\
	140	FTIM1_NOR_TSEQRAD_NOR(0x13))
	141	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	142	FTIM2_NOR_TCH(0x4) \| \
	143	FTIM2_NOR_TWPH(0x0E) \| \
	144	FTIM2_NOR_TWP(0x1c))
	145	#define CONFIG_SYS_NOR_FTIM3 0x0
	146
	147	#define CONFIG_SYS_FLASH_QUIET_TEST
	148	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	149
8d67c368 SL	150	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	151	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	152	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	153	#define CONFIG_SYS_FLASH_EMPTY_INFO
	154	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
	155
	156	/* CPLD on IFC */
	157	#define CONFIG_SYS_CPLD_BASE 0xffdf0000
	158	#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_CPLD_BASE)
	159	#define CONFIG_SYS_CSPR2_EXT (0xf)
	160	#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
	161	\| CSPR_PORT_SIZE_8 \
	162	\| CSPR_MSEL_GPCM \
	163	\| CSPR_V)
	164	#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
	165	#define CONFIG_SYS_CSOR2 0x0
	166
	167	/* CPLD Timing parameters for IFC CS2 */
	168	#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	169	FTIM0_GPCM_TEADC(0x0e) \| \
	170	FTIM0_GPCM_TEAHC(0x0e))
	171	#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) \| \
	172	FTIM1_GPCM_TRAD(0x1f))
	173	#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) \| \
de519163	174	FTIM2_GPCM_TCH(0x8) \| \
8d67c368 SL	175	FTIM2_GPCM_TWP(0x1f))
	176	#define CONFIG_SYS_CS2_FTIM3 0x0
	177
	178	/* NAND Flash on IFC */
8d67c368 SL	179	#define CONFIG_SYS_NAND_BASE 0xff800000
	180	#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_NAND_BASE)
	181
	182	#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
	183	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	184	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	185	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	186	\| CSPR_V)
	187	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	188
	189	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	190	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	191	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	192	\| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
	193	\| CSOR_NAND_PGS_2K /* Page Size = 2K */\
	194	\| CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
	195	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	196
8d67c368 SL	197	/* ONFI NAND Flash mode0 Timing Params */
	198	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	199	FTIM0_NAND_TWP(0x18) \| \
	200	FTIM0_NAND_TWCHT(0x07) \| \
	201	FTIM0_NAND_TWH(0x0a))
	202	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	203	FTIM1_NAND_TWBE(0x39) \| \
	204	FTIM1_NAND_TRR(0x0e) \| \
	205	FTIM1_NAND_TRP(0x18))
	206	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	207	FTIM2_NAND_TREH(0x0a) \| \
	208	FTIM2_NAND_TWHRE(0x1e))
	209	#define CONFIG_SYS_NAND_FTIM3 0x0
	210
	211	#define CONFIG_SYS_NAND_DDR_LAW 11
	212	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	213	#define CONFIG_SYS_MAX_NAND_DEVICE 1
8d67c368	214
88718be3	215	#if defined(CONFIG_MTD_RAW_NAND)
8d67c368 SL	216	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	217	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	218	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	219	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	220	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	221	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	222	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	223	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	224	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	225	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
	226	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	227	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	228	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	229	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	230	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	231	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	232	#else
	233	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	234	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	235	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	236	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	237	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	238	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	239	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	240	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	241	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
	242	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	243	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	244	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
	245	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	246	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	247	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	248	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
	249	#endif
	250
	251	#if defined(CONFIG_RAMBOOT_PBL)
	252	#define CONFIG_SYS_RAMBOOT
	253	#endif
	254
8d67c368 SL	255	#define CONFIG_HWCONFIG
	256
	257	/* define to use L1 as initial stack */
	258	#define CONFIG_L1_INIT_RAM
	259	#define CONFIG_SYS_INIT_RAM_LOCK
	260	#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
	261	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
b3142e2c	262	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
8d67c368 SL	263	/* The assembler doesn't like typecast */
	264	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	265	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	266	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
	267	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
	268	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	269	GENERATED_GBL_DATA_SIZE)
	270	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
9307cbab	271	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
8d67c368 SL	272
	273	/*
	274	* Serial Port
	275	*/
8d67c368 SL	276	#define CONFIG_SYS_NS16550_SERIAL
	277	#define CONFIG_SYS_NS16550_REG_SIZE 1
	278	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	279	#define CONFIG_SYS_BAUDRATE_TABLE \
	280	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	281	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
	282	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
	283	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
	284	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
	285
8d67c368 SL	286	/*
	287	* I2C
	288	*/
8e4be6df	289
8d67c368 SL	290	#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
	291	#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
	292	#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
	293	#define I2C_MUX_CH_DEFAULT 0x8
	294
e5abb92c YZ	295	#define I2C_MUX_CH_VOL_MONITOR 0xa
e5abb92c YZ	296
e5abb92c YZ	297	/* The lowest and highest voltage allowed for T208xRDB */
	298	#define VDD_MV_MIN 819
	299	#define VDD_MV_MAX 1212
8d67c368 SL	300
	301	/*
	302	* RapidIO
	303	*/
	304	#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
	305	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
	306	#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
	307	#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
	308	#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
	309	#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
	310	/*
	311	* for slave u-boot IMAGE instored in master memory space,
	312	* PHYS must be aligned based on the SIZE
	313	*/
e4911815 LG	314	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
	315	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
	316	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
	317	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
8d67c368 SL	318	/*
	319	* for slave UCODE and ENV instored in master memory space,
	320	* PHYS must be aligned based on the SIZE
	321	*/
e4911815	322	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
8d67c368 SL	323	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
	324	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
	325
	326	/* slave core release by master*/
	327	#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
	328	#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
	329
	330	/*
	331	* SRIO_PCIE_BOOT - SLAVE
	332	*/
	333	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
	334	#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
	335	#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
	336	(0x300000000ull \| CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
	337	#endif
	338
	339	/*
	340	* eSPI - Enhanced SPI
	341	*/
8d67c368 SL	342
	343	/*
	344	* General PCI
	345	* Memory space is mapped 1-1, but I/O space must start from 0.
	346	*/
b38eaec5 RD	347	#define CONFIG_PCIE1 /* PCIE controller 1 */
	348	#define CONFIG_PCIE2 /* PCIE controller 2 */
	349	#define CONFIG_PCIE3 /* PCIE controller 3 */
	350	#define CONFIG_PCIE4 /* PCIE controller 4 */
8d67c368 SL	351	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
8d67c368 SL	352	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
8d67c368	353	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
8d67c368	354	#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
8d67c368	355	#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
8d67c368 SL	356
	357	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
	358	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
8d67c368	359	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
8d67c368	360	#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
8d67c368	361	#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
8d67c368 SL	362
	363	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
	364	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
8d67c368	365	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
8d67c368	366	#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
8d67c368	367	#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
8d67c368 SL	368
	369	/* controller 4, Base address 203000 */
	370	#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
8d67c368	371	#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
8d67c368	372	#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
8d67c368 SL	373
8d67c368 SL	374	#ifdef CONFIG_PCI
8d67c368	375	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
8d67c368 SL	376	#endif
	377
	378	/* Qman/Bman */
	379	#ifndef CONFIG_NOBQFMAN
8d67c368 SL	380	#define CONFIG_SYS_BMAN_NUM_PORTALS 18
	381	#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
	382	#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
	383	#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
3fa66db4 JL	384	#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
	385	#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
	386	#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
	387	#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	388	#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
	389	CONFIG_SYS_BMAN_CENA_SIZE)
	390	#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	391	#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
8d67c368 SL	392	#define CONFIG_SYS_QMAN_NUM_PORTALS 18
	393	#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
	394	#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
	395	#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
3fa66db4 JL	396	#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
	397	#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
	398	#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
	399	#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	400	#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
	401	CONFIG_SYS_QMAN_CENA_SIZE)
	402	#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	403	#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
8d67c368 SL	404
	405	#define CONFIG_SYS_DPAA_FMAN
	406	#define CONFIG_SYS_DPAA_PME
	407	#define CONFIG_SYS_PMAN
	408	#define CONFIG_SYS_DPAA_DCE
	409	#define CONFIG_SYS_DPAA_RMAN /* RMan */
	410	#define CONFIG_SYS_INTERLAKEN
	411
8d67c368 SL	412	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	413	#endif /* CONFIG_NOBQFMAN */
	414
	415	#ifdef CONFIG_SYS_DPAA_FMAN
8d67c368 SL	416	#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
	417	#define RGMII_PHY2_ADDR 0x02
	418	#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
	419	#define CORTINA_PHY_ADDR2 0x0d
4e21a555 CG	420	/* Aquantia AQ1202 10G Base-T used by board revisions up to C */
4e21a555 CG	421	#define FM1_10GEC3_PHY_ADDR 0x00
8d67c368	422	#define FM1_10GEC4_PHY_ADDR 0x01
4e21a555 CG	423	/* Aquantia AQR113C 10G Base-T used by board revisions D and up */
	424	#define AQR113C_PHY_ADDR1 0x00
	425	#define AQR113C_PHY_ADDR2 0x08
8d67c368 SL	426	#endif
8d67c368 SL	427
8d67c368 SL	428	/*
	429	* SATA
	430	*/
	431	#ifdef CONFIG_FSL_SATA_V2
8d67c368 SL	432	#define CONFIG_SATA1
	433	#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
	434	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
	435	#define CONFIG_SATA2
	436	#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
	437	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
	438	#define CONFIG_LBA48
8d67c368 SL	439	#endif
	440
	441	/*
	442	* USB
	443	*/
8850c5d5	444	#ifdef CONFIG_USB_EHCI_HCD
8d67c368	445	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
8d67c368 SL	446	#define CONFIG_HAS_FSL_DR_USB
	447	#endif
	448
	449	/*
	450	* SDHC
	451	*/
	452	#ifdef CONFIG_MMC
8d67c368 SL	453	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
8d67c368 SL	454	#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
8d67c368 SL	455	#endif
8d67c368 SL	456
4feac1c6 SL	457	/*
	458	* Dynamic MTD Partition support with mtdparts
	459	*/
4feac1c6	460
8d67c368 SL	461	/*
	462	* Environment
	463	*/
	464
8d67c368 SL	465	/*
	466	* Miscellaneous configurable options
	467	*/
8d67c368 SL	468
	469	/*
	470	* For booting Linux, the board info and command line data
	471	* have to be in the first 64 MB of memory, since this is
	472	* the maximum mapped by the Linux kernel during initialization.
	473	*/
	474	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
	475	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	476
8d67c368 SL	477	/*
	478	* Environment Configuration
	479	*/
	480	#define CONFIG_ROOTPATH "/opt/nfsroot"
8d67c368 SL	481	#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
8d67c368 SL	482
8d67c368 SL	483	#define __USB_PHY_TYPE utmi
	484
	485	#define CONFIG_EXTRA_ENV_SETTINGS \
	486	"hwconfig=fsl_ddr:" \
	487	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
	488	"bank_intlv=auto;" \
	489	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
	490	"netdev=eth0\0" \
	491	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	492	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
	493	"tftpflash=tftpboot $loadaddr $uboot && " \
	494	"protect off $ubootaddr +$filesize && " \
	495	"erase $ubootaddr +$filesize && " \
	496	"cp.b $loadaddr $ubootaddr $filesize && " \
	497	"protect on $ubootaddr +$filesize && " \
	498	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	499	"consoledev=ttyS0\0" \
	500	"ramdiskaddr=2000000\0" \
	501	"ramdiskfile=t2080rdb/ramdisk.uboot\0" \
b24a4f62	502	"fdtaddr=1e00000\0" \
8d67c368	503	"fdtfile=t2080rdb/t2080rdb.dtb\0" \
3246584d	504	"bdev=sda3\0"
8d67c368 SL	505
	506	/*
	507	* For emulation this causes u-boot to jump to the start of the
	508	* proof point app code automatically
	509	*/
7ae1b080	510	#define PROOF_POINTS \
8d67c368 SL	511	"setenv bootargs root=/dev/$bdev rw " \
	512	"console=$consoledev,$baudrate $othbootargs;" \
	513	"cpu 1 release 0x29000000 - - -;" \
	514	"cpu 2 release 0x29000000 - - -;" \
	515	"cpu 3 release 0x29000000 - - -;" \
	516	"cpu 4 release 0x29000000 - - -;" \
	517	"cpu 5 release 0x29000000 - - -;" \
	518	"cpu 6 release 0x29000000 - - -;" \
	519	"cpu 7 release 0x29000000 - - -;" \
	520	"go 0x29000000"
	521
7ae1b080	522	#define HVBOOT \
8d67c368 SL	523	"setenv bootargs config-addr=0x60000000; " \
	524	"bootm 0x01000000 - 0x00f00000"
	525
7ae1b080	526	#define ALU \
8d67c368 SL	527	"setenv bootargs root=/dev/$bdev rw " \
	528	"console=$consoledev,$baudrate $othbootargs;" \
	529	"cpu 1 release 0x01000000 - - -;" \
	530	"cpu 2 release 0x01000000 - - -;" \
	531	"cpu 3 release 0x01000000 - - -;" \
	532	"cpu 4 release 0x01000000 - - -;" \
	533	"cpu 5 release 0x01000000 - - -;" \
	534	"cpu 6 release 0x01000000 - - -;" \
	535	"cpu 7 release 0x01000000 - - -;" \
	536	"go 0x01000000"
	537
8d67c368	538	#include <asm/fsl_secure_boot.h>
ef6c55a2	539
8d67c368	540	#endif /* __T2080RDB_H */