[thirdparty/u-boot.git] / include / configs / T4240RDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2020-2023 NXP
 */

/*
 * T4240 RDB board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#include <linux/stringify.h>

#define CFG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */

#ifdef CONFIG_RAMBOOT_PBL
#ifndef CONFIG_SDCARD
#define CFG_RESET_VECTOR_ADDRESS     0xfffffffc
#else
#define RESET_VECTOR_OFFSET		0x27FFC
#define BOOT_PAGE_OFFSET		0x27000

#ifdef	CONFIG_SDCARD
#define CFG_RESET_VECTOR_ADDRESS	0x200FFC
#define CFG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST	0x00200000
#define CFG_SYS_MMC_U_BOOT_START	0x00200000
#define CFG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
#endif

#endif
#endif /* CONFIG_RAMBOOT_PBL */

/* High Level Configuration Options */

#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#define CFG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS

/*
 *  Config the L3 Cache as L3 SRAM
 */
#define CFG_SYS_INIT_L3_ADDR		0xFFFC0000
#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)

#define CFG_SYS_DCSRBAR		0xf0000000
#define CFG_SYS_DCSRBAR_PHYS		0xf00000000ull

/*
 * DDR Setup
 */
#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE

/*
 * IFC Definitions
 */
#define CFG_SYS_FLASH_BASE	0xe0000000
#define CFG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CFG_SYS_FLASH_BASE)

/* define to use L1 as initial stack */
#define CFG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
/* The assembler doesn't like typecast */
#define CFG_SYS_INIT_RAM_ADDR_PHYS \
	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CFG_SYS_INIT_RAM_SIZE		0x00004000

#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#if !CONFIG_IS_ENABLED(DM_SERIAL)
#define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
#endif

#define CFG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x11C500)
#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x11C600)
#define CFG_SYS_NS16550_COM3	(CFG_SYS_CCSRBAR+0x11D500)
#define CFG_SYS_NS16550_COM4	(CFG_SYS_CCSRBAR+0x11D600)

/* I2C */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CFG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CFG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS	0xff8000000ull

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CFG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CFG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
#define CFG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CFG_SYS_PCIE2_IO_PHYS	0xff8010000ull

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CFG_SYS_PCIE3_MEM_VIRT	0xc0000000
#define CFG_SYS_PCIE3_MEM_PHYS	0xc40000000ull

/* controller 4, Base address 203000 */
#define CFG_SYS_PCIE4_MEM_BUS	0xe0000000
#define CFG_SYS_PCIE4_MEM_PHYS	0xc60000000ull

/*
 * Miscellaneous configurable options
 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/

/*
 * Environment Configuration
 */

#define HVBOOT					\
	"setenv bootargs config-addr=0x60000000; "	\
	"bootm 0x01000000 - 0x00f00000"

/*
 * DDR Setup
 */
#define SPD_EEPROM_ADDRESS1	0x52
#define SPD_EEPROM_ADDRESS2	0x54
#define SPD_EEPROM_ADDRESS3	0x56
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
#define CFG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */

/*
 * IFC Definitions
 */
#define CFG_SYS_NOR0_CSPR_EXT	(0xf)
#define CFG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
				+ 0x8000000) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CFG_SYS_NOR1_CSPR_EXT	(0xf)
#define CFG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CFG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
#define CFG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80

#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1A) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3	0x0

#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS \
					+ 0x8000000, CFG_SYS_FLASH_BASE_PHYS}

/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE		0xff800000
#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)

#define CFG_SYS_NAND_CSPR_EXT	(0xf)
#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)

#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(128))	/*Page Per Block = 128*/

/* ONFI NAND Flash mode0 Timing Params */
#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CFG_SYS_NAND_FTIM3		0x0

#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }

#if defined(CONFIG_MTD_RAW_NAND)
#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR2_EXT		CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR2		CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK2		CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR2		CFG_SYS_NOR_CSOR
#define CFG_SYS_CS2_FTIM0		CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS2_FTIM1		CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS2_FTIM2		CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS2_FTIM3		CFG_SYS_NOR_FTIM3
#else
#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR1		CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK1		CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR1		CFG_SYS_NAND_CSOR
#define CFG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
#endif
#define CFG_SYS_CSPR2_EXT		CFG_SYS_NOR1_CSPR_EXT
#define CFG_SYS_CSPR2		CFG_SYS_NOR1_CSPR
#define CFG_SYS_AMASK2		CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR2		CFG_SYS_NOR_CSOR
#define CFG_SYS_CS2_FTIM0		CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS2_FTIM1		CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS2_FTIM2		CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS2_FTIM3		CFG_SYS_NOR_FTIM3

/* CPLD on IFC */
#define CFG_SYS_CPLD_BASE	0xffdf0000
#define CFG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CFG_SYS_CPLD_BASE)
#define CFG_SYS_CSPR3_EXT	(0xf)
#define CFG_SYS_CSPR3	(CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)

#define CFG_SYS_AMASK3	IFC_AMASK(64 * 1024)
#define CFG_SYS_CSOR3	0x0

/* CPLD Timing parameters for IFC CS3 */
#define CFG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CFG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CFG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
					FTIM2_GPCM_TCH(0x8) | \
					FTIM2_GPCM_TWP(0x1f))
#define CFG_SYS_CS3_FTIM3		0x0

/* I2C */
#define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */

#define I2C_MUX_CH_DEFAULT	0x8
#define I2C_MUX_CH_VOL_MONITOR	0xa
#define I2C_MUX_CH_VSC3316_FS	0xc
#define I2C_MUX_CH_VSC3316_BS	0xd

/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR		0x40
#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT	3

/* The lowest and highest voltage allowed for T4240RDB */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

/*
 * eSPI - Enhanced SPI
 */

/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CFG_SYS_BMAN_NUM_PORTALS	50
#define CFG_SYS_BMAN_MEM_BASE	0xf4000000
#define CFG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#define CFG_SYS_BMAN_MEM_SIZE	0x02000000
#define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
					CFG_SYS_BMAN_CENA_SIZE)
#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_SWP_ISDR_REG    0xE08
#define CFG_SYS_QMAN_NUM_PORTALS	50
#define CFG_SYS_QMAN_MEM_BASE	0xf6000000
#define CFG_SYS_QMAN_MEM_PHYS	0xff6000000ull
#define CFG_SYS_QMAN_MEM_SIZE	0x02000000
#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
					CFG_SYS_QMAN_CENA_SIZE)
#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_SWP_ISDR_REG	0xE08
#endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_SYS_DPAA_FMAN
#define SGMII_PHY_ADDR1 0x0
#define SGMII_PHY_ADDR2 0x1
#define SGMII_PHY_ADDR3 0x2
#define SGMII_PHY_ADDR4 0x3
#define SGMII_PHY_ADDR5 0x4
#define SGMII_PHY_ADDR6 0x5
#define SGMII_PHY_ADDR7 0x6
#define SGMII_PHY_ADDR8 0x7
#define FM1_10GEC1_PHY_ADDR	0x10
#define FM1_10GEC2_PHY_ADDR	0x11
#define FM2_10GEC1_PHY_ADDR	0x12
#define FM2_10GEC2_PHY_ADDR	0x13
#define CORTINA_PHY_ADDR1	FM1_10GEC1_PHY_ADDR
#define CORTINA_PHY_ADDR2	FM1_10GEC2_PHY_ADDR
#define CORTINA_PHY_ADDR3	FM2_10GEC1_PHY_ADDR
#define CORTINA_PHY_ADDR4	FM2_10GEC2_PHY_ADDR
#endif

/*
* USB
*/

#ifdef CONFIG_MMC
#define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
#endif


#define __USB_PHY_TYPE	utmi

/*
 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 * interleaving. It can be cacheline, page, bank, superbank.
 * See doc/README.fsl-ddr for details.
 */
#ifdef CONFIG_ARCH_T4240
#define CTRL_INTLV_PREFERED 3way_4KB
#else
#define CTRL_INTLV_PREFERED cacheline
#endif

#define	CFG_EXTRA_ENV_SETTINGS				\
	"hwconfig=fsl_ddr:"					\
	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
	"bank_intlv=auto;"					\
	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
	"netdev=eth0\0"						\
	"uboot=" CONFIG_UBOOTPATH "\0"		\
	"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
	"protect off $ubootaddr +$filesize && "			\
	"erase $ubootaddr +$filesize && "			\
	"cp.b $loadaddr $ubootaddr $filesize && "		\
	"protect on $ubootaddr +$filesize && "			\
	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
	"consoledev=ttyS0\0"					\
	"ramdiskaddr=2000000\0"					\
	"ramdiskfile=t4240rdb/ramdisk.uboot\0"			\
	"fdtaddr=1e00000\0"					\
	"fdtfile=t4240rdb/t4240rdb.dtb\0"			\
	"bdev=sda3\0"

#define HVBOOT					\
	"setenv bootargs config-addr=0x60000000; "	\
	"bootm 0x01000000 - 0x00f00000"

#include <asm/fsl_secure_boot.h>

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
0b2e13d9 CL	2	/*
0b2e13d9 CL	3	* Copyright 2014 Freescale Semiconductor, Inc.
a325e7e8	4	* Copyright 2020-2023 NXP
0b2e13d9 CL	5	*/
	6
	7	/*
	8	* T4240 RDB board configuration file
	9	*/
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
1af3c7f4 SG	13	#include <linux/stringify.h>
1af3c7f4 SG	14
cdbf8459	15	#define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
0b2e13d9 CL	16
0b2e13d9 CL	17	#ifdef CONFIG_RAMBOOT_PBL
373762c3	18	#ifndef CONFIG_SDCARD
3db78c83	19	#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
373762c3	20	#else
373762c3 CL	21	#define RESET_VECTOR_OFFSET 0x27FFC
	22	#define BOOT_PAGE_OFFSET 0x27000
	23
	24	#ifdef CONFIG_SDCARD
3db78c83	25	#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
65cc0e2a TR	26	#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
	27	#define CFG_SYS_MMC_U_BOOT_DST 0x00200000
	28	#define CFG_SYS_MMC_U_BOOT_START 0x00200000
	29	#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
373762c3 CL	30	#endif
373762c3 CL	31
0b2e13d9	32	#endif
373762c3	33	#endif /* CONFIG_RAMBOOT_PBL */
0b2e13d9	34
0b2e13d9	35	/* High Level Configuration Options */
0b2e13d9	36
3db78c83 TR	37	#ifndef CFG_RESET_VECTOR_ADDRESS
3db78c83 TR	38	#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
0b2e13d9 CL	39	#endif
0b2e13d9 CL	40
cdc5ed8f	41	#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
0b2e13d9	42
0b2e13d9 CL	43	/*
	44	* Config the L3 Cache as L3 SRAM
	45	*/
65cc0e2a	46	#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
a09fea1d	47	#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
0b2e13d9	48
65cc0e2a TR	49	#define CFG_SYS_DCSRBAR 0xf0000000
65cc0e2a TR	50	#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
0b2e13d9 CL	51
	52	/*
	53	* DDR Setup
	54	*/
65cc0e2a TR	55	#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
65cc0e2a TR	56	#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
0b2e13d9	57
0b2e13d9 CL	58	/*
	59	* IFC Definitions
	60	*/
65cc0e2a TR	61	#define CFG_SYS_FLASH_BASE 0xe0000000
65cc0e2a TR	62	#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CFG_SYS_FLASH_BASE)
0b2e13d9	63
0b2e13d9	64	/* define to use L1 as initial stack */
65cc0e2a TR	65	#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
	66	#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
	67	#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
0b2e13d9	68	/* The assembler doesn't like typecast */
65cc0e2a TR	69	#define CFG_SYS_INIT_RAM_ADDR_PHYS \
	70	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	71	CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
	72	#define CFG_SYS_INIT_RAM_SIZE 0x00004000
0b2e13d9	73
65cc0e2a	74	#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
0b2e13d9	75
0b2e13d9 CL	76	/* Serial Port - controlled on board with jumper J8
	77	* open - index 2
	78	* shorted - index 1
	79	*/
a325e7e8	80	#if !CONFIG_IS_ENABLED(DM_SERIAL)
91092132	81	#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
a325e7e8	82	#endif
0b2e13d9	83
65cc0e2a	84	#define CFG_SYS_BAUDRATE_TABLE \
0b2e13d9 CL	85	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
0b2e13d9 CL	86
65cc0e2a TR	87	#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
	88	#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
	89	#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
	90	#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
0b2e13d9	91
0b2e13d9	92	/* I2C */
e6bd72f8	93
0b2e13d9 CL	94	/*
	95	* General PCI
	96	* Memory space is mapped 1-1, but I/O space must start from 0.
	97	*/
	98
	99	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
ecc8d425 TR	100	#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
	101	#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
	102	#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
	103	#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
0b2e13d9 CL	104
0b2e13d9 CL	105	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
ecc8d425 TR	106	#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
	107	#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
	108	#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
	109	#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
0b2e13d9 CL	110
0b2e13d9 CL	111	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
ecc8d425 TR	112	#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
ecc8d425 TR	113	#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
0b2e13d9 CL	114
0b2e13d9 CL	115	/* controller 4, Base address 203000 */
ecc8d425 TR	116	#define CFG_SYS_PCIE4_MEM_BUS 0xe0000000
ecc8d425 TR	117	#define CFG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
0b2e13d9	118
0b2e13d9 CL	119	/*
	120	* Miscellaneous configurable options
	121	*/
0b2e13d9 CL	122
	123	/*
	124	* For booting Linux, the board info and command line data
	125	* have to be in the first 64 MB of memory, since this is
	126	* the maximum mapped by the Linux kernel during initialization.
	127	*/
65cc0e2a	128	#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
0b2e13d9	129
0b2e13d9 CL	130	/*
	131	* Environment Configuration
	132	*/
0b2e13d9	133
7ae1b080	134	#define HVBOOT \
0b2e13d9 CL	135	"setenv bootargs config-addr=0x60000000; " \
	136	"bootm 0x01000000 - 0x00f00000"
	137
0b2e13d9 CL	138	/*
	139	* DDR Setup
	140	*/
0b2e13d9 CL	141	#define SPD_EEPROM_ADDRESS1 0x52
	142	#define SPD_EEPROM_ADDRESS2 0x54
	143	#define SPD_EEPROM_ADDRESS3 0x56
	144	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
aa6e94de	145	#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
0b2e13d9 CL	146
	147	/*
	148	* IFC Definitions
	149	*/
65cc0e2a TR	150	#define CFG_SYS_NOR0_CSPR_EXT (0xf)
65cc0e2a TR	151	#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
0b2e13d9 CL	152	+ 0x8000000) \| \
	153	CSPR_PORT_SIZE_16 \| \
	154	CSPR_MSEL_NOR \| \
	155	CSPR_V)
65cc0e2a TR	156	#define CFG_SYS_NOR1_CSPR_EXT (0xf)
65cc0e2a TR	157	#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \| \
0b2e13d9 CL	158	CSPR_PORT_SIZE_16 \| \
	159	CSPR_MSEL_NOR \| \
	160	CSPR_V)
0ed384fd	161	#define CFG_SYS_NOR_AMASK IFC_AMASK(12810241024)
0b2e13d9	162	/* NOR Flash Timing Params */
0ed384fd	163	#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
0b2e13d9	164
0ed384fd	165	#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
0b2e13d9 CL	166	FTIM0_NOR_TEADC(0x5) \| \
0b2e13d9 CL	167	FTIM0_NOR_TEAHC(0x5))
0ed384fd	168	#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
0b2e13d9 CL	169	FTIM1_NOR_TRAD_NOR(0x1A) \|\
0b2e13d9 CL	170	FTIM1_NOR_TSEQRAD_NOR(0x13))
0ed384fd	171	#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
0b2e13d9 CL	172	FTIM2_NOR_TCH(0x4) \| \
	173	FTIM2_NOR_TWPH(0x0E) \| \
	174	FTIM2_NOR_TWP(0x1c))
0ed384fd	175	#define CFG_SYS_NOR_FTIM3 0x0
0b2e13d9	176
65cc0e2a TR	177	#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \
65cc0e2a TR	178	+ 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
0b2e13d9 CL	179
0b2e13d9 CL	180	/* NAND Flash on IFC */
4e590945 TR	181	#define CFG_SYS_NAND_BASE 0xff800000
4e590945 TR	182	#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull \| CFG_SYS_NAND_BASE)
0b2e13d9	183
4e590945 TR	184	#define CFG_SYS_NAND_CSPR_EXT (0xf)
4e590945 TR	185	#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
0b2e13d9 CL	186	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	187	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	188	\| CSPR_V)
4e590945	189	#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
0b2e13d9	190
4e590945	191	#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
0b2e13d9 CL	192	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	193	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	194	\| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
	195	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	196	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
	197	\| CSOR_NAND_PB(128)) /Page Per Block = 128/
	198
0b2e13d9	199	/* ONFI NAND Flash mode0 Timing Params */
4e590945	200	#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
0b2e13d9 CL	201	FTIM0_NAND_TWP(0x18) \| \
	202	FTIM0_NAND_TWCHT(0x07) \| \
	203	FTIM0_NAND_TWH(0x0a))
4e590945	204	#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
0b2e13d9 CL	205	FTIM1_NAND_TWBE(0x39) \| \
	206	FTIM1_NAND_TRR(0x0e) \| \
	207	FTIM1_NAND_TRP(0x18))
4e590945	208	#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
0b2e13d9 CL	209	FTIM2_NAND_TREH(0x0a) \| \
0b2e13d9 CL	210	FTIM2_NAND_TWHRE(0x1e))
4e590945	211	#define CFG_SYS_NAND_FTIM3 0x0
0b2e13d9	212
4e590945	213	#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
0b2e13d9	214
88718be3	215	#if defined(CONFIG_MTD_RAW_NAND)
65cc0e2a TR	216	#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
	217	#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
	218	#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
	219	#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
	220	#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
	221	#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
	222	#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
	223	#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
	224	#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT
	225	#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR
	226	#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
	227	#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
	228	#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
	229	#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
	230	#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
	231	#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
0b2e13d9	232	#else
65cc0e2a TR	233	#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
	234	#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
	235	#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
	236	#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
	237	#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
	238	#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
	239	#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
	240	#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
	241	#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
	242	#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
	243	#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
	244	#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
	245	#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
	246	#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
	247	#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
	248	#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
0b2e13d9	249	#endif
65cc0e2a TR	250	#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
	251	#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
	252	#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
	253	#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
	254	#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
	255	#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
	256	#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
	257	#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
0b2e13d9	258
ab06b236	259	/* CPLD on IFC */
65cc0e2a TR	260	#define CFG_SYS_CPLD_BASE 0xffdf0000
	261	#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull \| CFG_SYS_CPLD_BASE)
	262	#define CFG_SYS_CSPR3_EXT (0xf)
	263	#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
ab06b236 CL	264	\| CSPR_PORT_SIZE_8 \
	265	\| CSPR_MSEL_GPCM \
	266	\| CSPR_V)
	267
65cc0e2a TR	268	#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
65cc0e2a TR	269	#define CFG_SYS_CSOR3 0x0
ab06b236 CL	270
ab06b236 CL	271	/* CPLD Timing parameters for IFC CS3 */
65cc0e2a	272	#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
ab06b236 CL	273	FTIM0_GPCM_TEADC(0x0e) \| \
ab06b236 CL	274	FTIM0_GPCM_TEAHC(0x0e))
65cc0e2a	275	#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) \| \
ab06b236	276	FTIM1_GPCM_TRAD(0x1f))
65cc0e2a	277	#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) \| \
1b5c2b51	278	FTIM2_GPCM_TCH(0x8) \| \
ab06b236	279	FTIM2_GPCM_TWP(0x1f))
65cc0e2a	280	#define CFG_SYS_CS3_FTIM3 0x0
ab06b236	281
0b2e13d9	282	/* I2C */
0b2e13d9 CL	283	#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
	284	#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
	285
	286	#define I2C_MUX_CH_DEFAULT 0x8
	287	#define I2C_MUX_CH_VOL_MONITOR 0xa
	288	#define I2C_MUX_CH_VSC3316_FS 0xc
	289	#define I2C_MUX_CH_VSC3316_BS 0xd
	290
	291	/* Voltage monitor on channel 2*/
	292	#define I2C_VOL_MONITOR_ADDR 0x40
	293	#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
	294	#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
	295	#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
	296
2f66a828 YZ	297	/* The lowest and highest voltage allowed for T4240RDB */
	298	#define VDD_MV_MIN 819
	299	#define VDD_MV_MAX 1212
	300
0b2e13d9 CL	301	/*
	302	* eSPI - Enhanced SPI
	303	*/
0b2e13d9	304
0b2e13d9 CL	305	/* Qman/Bman */
0b2e13d9 CL	306	#ifndef CONFIG_NOBQFMAN
65cc0e2a TR	307	#define CFG_SYS_BMAN_NUM_PORTALS 50
	308	#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
	309	#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
	310	#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
	311	#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
	312	#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
	313	#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
	314	#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
	315	#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
	316	CFG_SYS_BMAN_CENA_SIZE)
	317	#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
	318	#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
	319	#define CFG_SYS_QMAN_NUM_PORTALS 50
	320	#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
	321	#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
	322	#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
	323	#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
	324	#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
	325	#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
	326	CFG_SYS_QMAN_CENA_SIZE)
	327	#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
	328	#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
0b2e13d9 CL	329	#endif /* CONFIG_NOBQFMAN */
	330
	331	#ifdef CONFIG_SYS_DPAA_FMAN
0b2e13d9 CL	332	#define SGMII_PHY_ADDR1 0x0
	333	#define SGMII_PHY_ADDR2 0x1
	334	#define SGMII_PHY_ADDR3 0x2
	335	#define SGMII_PHY_ADDR4 0x3
	336	#define SGMII_PHY_ADDR5 0x4
	337	#define SGMII_PHY_ADDR6 0x5
	338	#define SGMII_PHY_ADDR7 0x6
	339	#define SGMII_PHY_ADDR8 0x7
	340	#define FM1_10GEC1_PHY_ADDR 0x10
	341	#define FM1_10GEC2_PHY_ADDR 0x11
	342	#define FM2_10GEC1_PHY_ADDR 0x12
	343	#define FM2_10GEC2_PHY_ADDR 0x13
	344	#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
	345	#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
	346	#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
	347	#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
	348	#endif
	349
0b2e13d9 CL	350	/*
	351	* USB
	352	*/
0b2e13d9	353
0b2e13d9	354	#ifdef CONFIG_MMC
6cc04547	355	#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
0b2e13d9 CL	356	#endif
0b2e13d9 CL	357
0b2e13d9 CL	358
	359	#define __USB_PHY_TYPE utmi
	360
	361	/*
	362	* T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
	363	* 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
	364	* interleaving. It can be cacheline, page, bank, superbank.
	365	* See doc/README.fsl-ddr for details.
	366	*/
26bc57da	367	#ifdef CONFIG_ARCH_T4240
0b2e13d9	368	#define CTRL_INTLV_PREFERED 3way_4KB
1a344456 CL	369	#else
	370	#define CTRL_INTLV_PREFERED cacheline
	371	#endif
0b2e13d9	372
0613c36a	373	#define CFG_EXTRA_ENV_SETTINGS \
0b2e13d9 CL	374	"hwconfig=fsl_ddr:" \
	375	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
	376	"bank_intlv=auto;" \
	377	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
	378	"netdev=eth0\0" \
54f80dd2	379	"uboot=" CONFIG_UBOOTPATH "\0" \
98463903	380	"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
0b2e13d9 CL	381	"tftpflash=tftpboot $loadaddr $uboot && " \
	382	"protect off $ubootaddr +$filesize && " \
	383	"erase $ubootaddr +$filesize && " \
	384	"cp.b $loadaddr $ubootaddr $filesize && " \
	385	"protect on $ubootaddr +$filesize && " \
	386	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	387	"consoledev=ttyS0\0" \
	388	"ramdiskaddr=2000000\0" \
	389	"ramdiskfile=t4240rdb/ramdisk.uboot\0" \
b24a4f62	390	"fdtaddr=1e00000\0" \
0b2e13d9 CL	391	"fdtfile=t4240rdb/t4240rdb.dtb\0" \
	392	"bdev=sda3\0"
	393
7ae1b080	394	#define HVBOOT \
0b2e13d9 CL	395	"setenv bootargs config-addr=0x60000000; " \
	396	"bootm 0x01000000 - 0x00f00000"
	397
0b2e13d9 CL	398	#include <asm/fsl_secure_boot.h>
0b2e13d9 CL	399
0b2e13d9	400	#endif /* __CONFIG_H */