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b87dfd28 WD |
1 | /* |
2 | * (C) Copyright 2003-2006 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004-2006 | |
6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* | |
31 | * High Level Configuration Options | |
32 | * (easy to change) | |
33 | */ | |
34 | ||
35 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
36 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
37 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ | |
38 | #define CONFIG_TB5200 1 /* ... on a TB5200 base board */ | |
39 | ||
2ae18241 WD |
40 | /* |
41 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
42 | * 0xFC000000 boot low (standard configuration with room for | |
43 | * max 64 MByte Flash ROM) | |
44 | * 0xFFF00000 boot high (for a backup copy of U-Boot) | |
45 | * 0x00100000 boot from RAM (for testing only) | |
46 | */ | |
47 | #ifndef CONFIG_SYS_TEXT_BASE | |
48 | #define CONFIG_SYS_TEXT_BASE 0xFC000000 | |
49 | #endif | |
50 | ||
6d0f6bcf | 51 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
b87dfd28 | 52 | |
31d82672 BB |
53 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
54 | ||
b87dfd28 WD |
55 | /* |
56 | * Serial console configuration | |
57 | */ | |
58 | #define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */ | |
b87dfd28 WD |
59 | #define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */ |
60 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 61 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
b87dfd28 WD |
62 | |
63 | /* | |
64 | * Video console | |
65 | */ | |
66 | #if 1 | |
67 | #define CONFIG_VIDEO | |
68 | #define CONFIG_VIDEO_SM501 | |
69 | #define CONFIG_VIDEO_SM501_32BPP | |
70 | #define CONFIG_CFB_CONSOLE | |
71 | #define CONFIG_VIDEO_LOGO | |
72 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
73 | #define CONFIG_CONSOLE_EXTRA_INFO | |
74 | #define CONFIG_VIDEO_SW_CURSOR | |
75 | #define CONFIG_SPLASH_SCREEN | |
6d0f6bcf | 76 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
b87dfd28 WD |
77 | #endif |
78 | ||
b87dfd28 WD |
79 | /* Partitions */ |
80 | #define CONFIG_MAC_PARTITION | |
81 | #define CONFIG_DOS_PARTITION | |
82 | #define CONFIG_ISO_PARTITION | |
83 | ||
84 | /* USB */ | |
85 | #define CONFIG_USB_OHCI | |
b87dfd28 WD |
86 | #define CONFIG_USB_STORAGE |
87 | ||
88 | /* POST support */ | |
6d0f6bcf JCPV |
89 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
90 | CONFIG_SYS_POST_CPU | \ | |
91 | CONFIG_SYS_POST_I2C) | |
b87dfd28 WD |
92 | |
93 | #ifdef CONFIG_POST | |
b87dfd28 WD |
94 | /* preserve space for the post_word at end of on-chip SRAM */ |
95 | #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
b87dfd28 WD |
96 | #endif |
97 | ||
b87dfd28 | 98 | |
a1aa0bb5 JL |
99 | /* |
100 | * BOOTP options | |
101 | */ | |
102 | #define CONFIG_BOOTP_BOOTFILESIZE | |
103 | #define CONFIG_BOOTP_BOOTPATH | |
104 | #define CONFIG_BOOTP_GATEWAY | |
105 | #define CONFIG_BOOTP_HOSTNAME | |
106 | ||
107 | ||
b87dfd28 | 108 | /* |
d794cfef | 109 | * Command line configuration. |
b87dfd28 | 110 | */ |
d794cfef JL |
111 | #include <config_cmd_default.h> |
112 | ||
d794cfef JL |
113 | #define CONFIG_CMD_ASKENV |
114 | #define CONFIG_CMD_DATE | |
115 | #define CONFIG_CMD_DHCP | |
116 | #define CONFIG_CMD_ECHO | |
117 | #define CONFIG_CMD_EEPROM | |
118 | #define CONFIG_CMD_EXT2 | |
119 | #define CONFIG_CMD_FAT | |
120 | #define CONFIG_CMD_I2C | |
121 | #define CONFIG_CMD_IDE | |
122 | #define CONFIG_CMD_JFFS2 | |
123 | #define CONFIG_CMD_MII | |
124 | #define CONFIG_CMD_NFS | |
125 | #define CONFIG_CMD_PING | |
d794cfef JL |
126 | #define CONFIG_CMD_REGINFO |
127 | #define CONFIG_CMD_SNTP | |
128 | #define CONFIG_CMD_BSP | |
129 | #define CONFIG_CMD_USB | |
130 | ||
af075ee9 JL |
131 | #ifdef CONFIG_VIDEO |
132 | #define CONFIG_CMD_BMP | |
133 | #endif | |
134 | ||
135 | #ifdef CONFIG_POST | |
800eb096 | 136 | #define CONFIG_CMD_DIAG |
af075ee9 JL |
137 | #endif |
138 | ||
b87dfd28 WD |
139 | |
140 | #define CONFIG_TIMESTAMP /* display image timestamps */ | |
141 | ||
14d0a02a | 142 | #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */ |
6d0f6bcf | 143 | # define CONFIG_SYS_LOWBOOT 1 |
b87dfd28 WD |
144 | #endif |
145 | ||
146 | /* | |
147 | * Autobooting | |
148 | */ | |
149 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
150 | ||
151 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 152 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
b87dfd28 WD |
153 | "echo" |
154 | ||
155 | #undef CONFIG_BOOTARGS | |
156 | ||
45a212c4 WD |
157 | #if defined(CONFIG_TQM5200_B) |
158 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
159 | "netdev=eth0\0" \ | |
160 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
161 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
162 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
163 | "nfsroot=${serverip}:${rootpath}\0" \ | |
164 | "addip=setenv bootargs ${bootargs} " \ | |
165 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
166 | ":${hostname}:${netdev}:off panic=1\0" \ | |
167 | "flash_self=run ramargs addip;" \ | |
168 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
169 | "flash_nfs=run nfsargs addip;" \ | |
170 | "bootm ${kernel_addr}\0" \ | |
171 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
172 | "bootfile=/tftpboot/tqm5200/uImage\0" \ | |
173 | "load=tftp 200000 ${u-boot}\0" \ | |
174 | "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ | |
175 | "update=protect off FC000000 FC07FFFF;" \ | |
176 | "erase FC000000 FC07FFFF;" \ | |
177 | "cp.b 200000 FC000000 ${filesize};" \ | |
178 | "protect on FC000000 FC07FFFF\0" \ | |
179 | "" | |
180 | #else | |
b87dfd28 WD |
181 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
182 | "netdev=eth0\0" \ | |
183 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
184 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
185 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
186 | "nfsroot=${serverip}:${rootpath}\0" \ | |
187 | "addip=setenv bootargs ${bootargs} " \ | |
188 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
189 | ":${hostname}:${netdev}:off panic=1\0" \ | |
190 | "flash_self=run ramargs addip;" \ | |
191 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
192 | "flash_nfs=run nfsargs addip;" \ | |
193 | "bootm ${kernel_addr}\0" \ | |
194 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
195 | "bootfile=/tftpboot/tqm5200/uImage\0" \ | |
196 | "load=tftp 200000 $(u-boot)\0" \ | |
197 | "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ | |
198 | "update=protect off FC000000 FC05FFFF;" \ | |
199 | "erase FC000000 FC05FFFF;" \ | |
200 | "cp.b 200000 FC000000 ${filesize};" \ | |
201 | "protect on FC000000 FC05FFFF\0" \ | |
202 | "" | |
45a212c4 | 203 | #endif /* CONFIG_TQM5200_B */ |
b87dfd28 WD |
204 | |
205 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
206 | ||
207 | /* | |
208 | * IPB Bus clocking configuration. | |
209 | */ | |
6d0f6bcf | 210 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
b87dfd28 | 211 | |
6d0f6bcf | 212 | #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) |
b87dfd28 WD |
213 | /* |
214 | * PCI Bus clocking configuration | |
215 | * | |
216 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 217 | * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock |
c99512d6 | 218 | * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. |
b87dfd28 | 219 | */ |
6d0f6bcf | 220 | #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ |
b87dfd28 WD |
221 | #endif |
222 | ||
223 | /* | |
224 | * I2C configuration | |
225 | */ | |
226 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 227 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */ |
b87dfd28 WD |
228 | |
229 | /* | |
230 | * I2C clock frequency | |
231 | * | |
232 | * Please notice, that the resulting clock frequency could differ from the | |
233 | * configured value. This is because the I2C clock is derived from system | |
234 | * clock over a frequency divider with only a few divider values. U-boot | |
6d0f6bcf | 235 | * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated |
b87dfd28 WD |
236 | * approximation allways lies below the configured value, never above. |
237 | */ | |
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
239 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
b87dfd28 WD |
240 | |
241 | /* | |
242 | * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work | |
243 | * also). For other EEPROMs configuration should be verified. On Mini-FAP the | |
244 | * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the | |
245 | * same configuration could be used. | |
246 | */ | |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
248 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
249 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
250 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
b87dfd28 WD |
251 | |
252 | /* List of I2C addresses to be verified by POST */ | |
60aaaa07 PT |
253 | #undef CONFIG_SYS_POST_I2C_ADDRS |
254 | #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \ | |
255 | CONFIG_SYS_I2C_RTC_ADDR, \ | |
256 | CONFIG_SYS_I2C_SLAVE} | |
b87dfd28 WD |
257 | |
258 | /* | |
259 | * Flash configuration | |
260 | */ | |
14d0a02a | 261 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */ |
b87dfd28 | 262 | |
45a212c4 | 263 | /* use CFI flash driver */ |
6d0f6bcf | 264 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 265 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } |
267 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
268 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ | |
269 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
270 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
271 | ||
272 | #if !defined(CONFIG_SYS_LOWBOOT) | |
273 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) | |
274 | #else /* CONFIG_SYS_LOWBOOT */ | |
45a212c4 | 275 | #if defined(CONFIG_TQM5200_B) |
6d0f6bcf | 276 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000) |
45a212c4 | 277 | #else |
6d0f6bcf | 278 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) |
45a212c4 | 279 | #endif /* CONFIG_TQM5200_B */ |
6d0f6bcf JCPV |
280 | #endif /* CONFIG_SYS_LOWBOOT */ |
281 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks | |
b87dfd28 | 282 | (= chip selects) */ |
b87dfd28 WD |
283 | |
284 | /* Dynamic MTD partition support */ | |
68d7d651 | 285 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
286 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
287 | #define CONFIG_FLASH_CFI_MTD | |
b87dfd28 | 288 | #define MTDIDS_DEFAULT "nor0=TQM5200-0" |
45a212c4 WD |
289 | #if defined(CONFIG_TQM5200_B) |
290 | #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ | |
291 | "1280k(kernel)," \ | |
292 | "2m(initrd)," \ | |
293 | "4m(small-fs)," \ | |
294 | "16m(big-fs)," \ | |
295 | "8m(misc)" | |
296 | #else | |
b87dfd28 WD |
297 | #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ |
298 | "1408k(kernel)," \ | |
299 | "2m(initrd)," \ | |
300 | "4m(small-fs)," \ | |
301 | "16m(big-fs)," \ | |
302 | "8m(misc)" | |
45a212c4 | 303 | #endif /* CONFIG_TQM5200_B */ |
b87dfd28 WD |
304 | |
305 | /* | |
306 | * Environment settings | |
307 | */ | |
5a1aceb0 | 308 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 309 | #define CONFIG_ENV_SIZE 0x10000 |
45a212c4 | 310 | #if defined(CONFIG_TQM5200_B) |
0e8d1586 | 311 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
45a212c4 | 312 | #else |
0e8d1586 JCPV |
313 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
314 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
315 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
45a212c4 | 316 | #endif /* CONFIG_TQM5200_B */ |
b87dfd28 WD |
317 | |
318 | /* | |
319 | * Memory map | |
320 | */ | |
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_MBAR 0xF0000000 |
322 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
323 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
b87dfd28 WD |
324 | |
325 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 326 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
b87dfd28 WD |
327 | #ifdef CONFIG_POST |
328 | /* preserve space for the post_word at end of on-chip SRAM */ | |
553f0982 | 329 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
b87dfd28 | 330 | #else |
553f0982 | 331 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
b87dfd28 WD |
332 | #endif |
333 | ||
334 | ||
25ddd1fb | 335 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 336 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
b87dfd28 | 337 | |
14d0a02a | 338 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
339 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
340 | # define CONFIG_SYS_RAMBOOT 1 | |
b87dfd28 WD |
341 | #endif |
342 | ||
45a212c4 | 343 | #if defined(CONFIG_TQM5200_B) |
6d0f6bcf | 344 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
45a212c4 | 345 | #else |
6d0f6bcf | 346 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
45a212c4 | 347 | #endif /* CONFIG_TQM5200_B */ |
6d0f6bcf JCPV |
348 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ |
349 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
b87dfd28 WD |
350 | |
351 | /* | |
352 | * Ethernet configuration | |
353 | */ | |
354 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 355 | #define CONFIG_MPC5xxx_FEC_MII100 |
b87dfd28 | 356 | /* |
86321fc1 | 357 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
b87dfd28 | 358 | */ |
86321fc1 | 359 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
b87dfd28 WD |
360 | #define CONFIG_PHY_ADDR 0x00 |
361 | ||
362 | /* | |
363 | * GPIO configuration | |
364 | * | |
365 | * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): | |
366 | * Bit 0 (mask: 0x80000000): 1 | |
367 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): | |
368 | * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. | |
369 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. | |
370 | * Use for REV200 STK52XX boards. Do not use with REV100 modules | |
371 | * (because, there I2C1 is used as I2C bus) | |
372 | * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 | |
373 | * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) | |
374 | * 000 -> All PSC2 pins are GIOPs | |
375 | * 001 -> CAN1/2 on PSC2 pins | |
376 | * Use for REV100 STK52xx boards | |
377 | * use PSC3: Bits 20:23 (mask: 0x00000300): | |
378 | * 0001 -> USB2 | |
379 | * 0000 -> GPIO | |
380 | * use PSC6: | |
381 | * on STK52xx: | |
382 | * use as UART. Pins PSC6_0 to PSC6_3 are used. | |
383 | * Bits 9:11 (mask: 0x00700000): | |
384 | * 101 -> PSC6 : Extended POST test is not available | |
385 | * on MINI-FAP and TQM5200_IB: | |
386 | * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): | |
387 | * 000 -> PSC6 could not be used as UART, CODEC or IrDA | |
388 | * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST | |
389 | * tests. | |
390 | */ | |
6d0f6bcf | 391 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x81500114 |
b87dfd28 WD |
392 | |
393 | /* | |
394 | * RTC configuration | |
395 | */ | |
396 | #define CONFIG_RTC_M41T11 1 | |
6d0f6bcf JCPV |
397 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
398 | #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base | |
b87dfd28 WD |
399 | year */ |
400 | ||
401 | /* | |
402 | * Miscellaneous configurable options | |
403 | */ | |
6d0f6bcf JCPV |
404 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
405 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
33ed73bc | 406 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
d794cfef | 407 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 408 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
b87dfd28 | 409 | #else |
6d0f6bcf | 410 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
b87dfd28 | 411 | #endif |
6d0f6bcf JCPV |
412 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
413 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
414 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
b87dfd28 | 415 | |
6d0f6bcf | 416 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
d794cfef | 417 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 418 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
d794cfef JL |
419 | #endif |
420 | ||
b87dfd28 | 421 | /* Enable an alternate, more extensive memory test */ |
6d0f6bcf | 422 | #define CONFIG_SYS_ALT_MEMTEST |
b87dfd28 | 423 | |
6d0f6bcf JCPV |
424 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
425 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
b87dfd28 | 426 | |
6d0f6bcf | 427 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
b87dfd28 | 428 | |
6d0f6bcf | 429 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
b87dfd28 WD |
430 | |
431 | /* | |
a1aa0bb5 | 432 | * Enable loopw command. |
b87dfd28 WD |
433 | */ |
434 | #define CONFIG_LOOPW | |
435 | ||
436 | /* | |
437 | * Various low-level settings | |
438 | */ | |
6d0f6bcf JCPV |
439 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
440 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
b87dfd28 | 441 | |
6d0f6bcf JCPV |
442 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
443 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
444 | #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 | |
445 | #define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ | |
b87dfd28 | 446 | #else |
6d0f6bcf | 447 | #define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ |
b87dfd28 | 448 | #endif |
6d0f6bcf JCPV |
449 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
450 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
b87dfd28 | 451 | |
b87dfd28 | 452 | #define CONFIG_LAST_STAGE_INIT |
b87dfd28 WD |
453 | |
454 | /* | |
455 | * SRAM - Do not map below 2 GB in address space, because this area is used | |
456 | * for SDRAM autosizing. | |
457 | */ | |
6d0f6bcf JCPV |
458 | #define CONFIG_SYS_CS2_START 0xE5000000 |
459 | #define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ | |
460 | #define CONFIG_SYS_CS2_CFG 0x0004D930 | |
b87dfd28 WD |
461 | |
462 | /* | |
463 | * Grafic controller - Do not map below 2 GB in address space, because this | |
464 | * area is used for SDRAM autosizing. | |
465 | */ | |
b87dfd28 | 466 | #define SM501_FB_BASE 0xE0000000 |
6d0f6bcf JCPV |
467 | #define CONFIG_SYS_CS1_START (SM501_FB_BASE) |
468 | #define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ | |
469 | #define CONFIG_SYS_CS1_CFG 0x8F48FF70 | |
470 | #define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 | |
b87dfd28 | 471 | |
6d0f6bcf JCPV |
472 | #define CONFIG_SYS_CS_BURST 0x00000000 |
473 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ | |
b87dfd28 | 474 | |
6d0f6bcf | 475 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
b87dfd28 WD |
476 | |
477 | /*----------------------------------------------------------------------- | |
478 | * USB stuff | |
479 | *----------------------------------------------------------------------- | |
480 | */ | |
481 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
482 | #define CONFIG_USB_CONFIG 0x00001000 | |
483 | ||
484 | /*----------------------------------------------------------------------- | |
485 | * IDE/ATA stuff Supports IDE harddisk | |
486 | *----------------------------------------------------------------------- | |
487 | */ | |
488 | ||
489 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
490 | ||
491 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
492 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
493 | ||
494 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
495 | #define CONFIG_IDE_PREINIT | |
496 | ||
6d0f6bcf JCPV |
497 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
498 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
b87dfd28 | 499 | |
6d0f6bcf | 500 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
b87dfd28 | 501 | |
6d0f6bcf | 502 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
b87dfd28 WD |
503 | |
504 | /* Offset for data I/O */ | |
6d0f6bcf | 505 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
b87dfd28 WD |
506 | |
507 | /* Offset for normal register accesses */ | |
6d0f6bcf | 508 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
b87dfd28 WD |
509 | |
510 | /* Offset for alternate registers */ | |
6d0f6bcf | 511 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
b87dfd28 WD |
512 | |
513 | /* Interval between registers */ | |
6d0f6bcf | 514 | #define CONFIG_SYS_ATA_STRIDE 4 |
b87dfd28 WD |
515 | |
516 | #endif /* __CONFIG_H */ |