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b87dfd28 WD |
1 | /* |
2 | * (C) Copyright 2003-2006 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004-2006 | |
6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* | |
31 | * High Level Configuration Options | |
32 | * (easy to change) | |
33 | */ | |
34 | ||
35 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
36 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
37 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ | |
38 | #define CONFIG_TB5200 1 /* ... on a TB5200 base board */ | |
39 | ||
40 | #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ | |
41 | ||
42 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
43 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
44 | ||
31d82672 BB |
45 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
46 | ||
b87dfd28 WD |
47 | /* |
48 | * Serial console configuration | |
49 | */ | |
50 | #define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */ | |
51 | #define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */ | |
52 | #define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */ | |
53 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
54 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
55 | ||
56 | /* | |
57 | * Video console | |
58 | */ | |
59 | #if 1 | |
60 | #define CONFIG_VIDEO | |
61 | #define CONFIG_VIDEO_SM501 | |
62 | #define CONFIG_VIDEO_SM501_32BPP | |
63 | #define CONFIG_CFB_CONSOLE | |
64 | #define CONFIG_VIDEO_LOGO | |
65 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
66 | #define CONFIG_CONSOLE_EXTRA_INFO | |
67 | #define CONFIG_VIDEO_SW_CURSOR | |
68 | #define CONFIG_SPLASH_SCREEN | |
69 | #define CFG_CONSOLE_IS_IN_ENV | |
70 | #endif | |
71 | ||
b87dfd28 WD |
72 | /* Partitions */ |
73 | #define CONFIG_MAC_PARTITION | |
74 | #define CONFIG_DOS_PARTITION | |
75 | #define CONFIG_ISO_PARTITION | |
76 | ||
77 | /* USB */ | |
78 | #define CONFIG_USB_OHCI | |
b87dfd28 WD |
79 | #define CONFIG_USB_STORAGE |
80 | ||
81 | /* POST support */ | |
82 | #define CONFIG_POST (CFG_POST_MEMORY | \ | |
83 | CFG_POST_CPU | \ | |
84 | CFG_POST_I2C) | |
85 | ||
86 | #ifdef CONFIG_POST | |
b87dfd28 WD |
87 | /* preserve space for the post_word at end of on-chip SRAM */ |
88 | #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
b87dfd28 WD |
89 | #endif |
90 | ||
b87dfd28 | 91 | |
a1aa0bb5 JL |
92 | /* |
93 | * BOOTP options | |
94 | */ | |
95 | #define CONFIG_BOOTP_BOOTFILESIZE | |
96 | #define CONFIG_BOOTP_BOOTPATH | |
97 | #define CONFIG_BOOTP_GATEWAY | |
98 | #define CONFIG_BOOTP_HOSTNAME | |
99 | ||
100 | ||
b87dfd28 | 101 | /* |
d794cfef | 102 | * Command line configuration. |
b87dfd28 | 103 | */ |
d794cfef JL |
104 | #include <config_cmd_default.h> |
105 | ||
d794cfef JL |
106 | #define CONFIG_CMD_ASKENV |
107 | #define CONFIG_CMD_DATE | |
108 | #define CONFIG_CMD_DHCP | |
109 | #define CONFIG_CMD_ECHO | |
110 | #define CONFIG_CMD_EEPROM | |
111 | #define CONFIG_CMD_EXT2 | |
112 | #define CONFIG_CMD_FAT | |
113 | #define CONFIG_CMD_I2C | |
114 | #define CONFIG_CMD_IDE | |
115 | #define CONFIG_CMD_JFFS2 | |
116 | #define CONFIG_CMD_MII | |
117 | #define CONFIG_CMD_NFS | |
118 | #define CONFIG_CMD_PING | |
d794cfef JL |
119 | #define CONFIG_CMD_REGINFO |
120 | #define CONFIG_CMD_SNTP | |
121 | #define CONFIG_CMD_BSP | |
122 | #define CONFIG_CMD_USB | |
123 | ||
af075ee9 JL |
124 | #ifdef CONFIG_VIDEO |
125 | #define CONFIG_CMD_BMP | |
126 | #endif | |
127 | ||
128 | #ifdef CONFIG_POST | |
129 | #define CONFIG__CMD_DIAG | |
130 | #endif | |
131 | ||
b87dfd28 WD |
132 | |
133 | #define CONFIG_TIMESTAMP /* display image timestamps */ | |
134 | ||
135 | #if (TEXT_BASE == 0xFC000000) /* Boot low */ | |
136 | # define CFG_LOWBOOT 1 | |
137 | #endif | |
138 | ||
139 | /* | |
140 | * Autobooting | |
141 | */ | |
142 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
143 | ||
144 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 145 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
b87dfd28 WD |
146 | "echo" |
147 | ||
148 | #undef CONFIG_BOOTARGS | |
149 | ||
45a212c4 WD |
150 | #if defined(CONFIG_TQM5200_B) |
151 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
152 | "netdev=eth0\0" \ | |
153 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
154 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
155 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
156 | "nfsroot=${serverip}:${rootpath}\0" \ | |
157 | "addip=setenv bootargs ${bootargs} " \ | |
158 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
159 | ":${hostname}:${netdev}:off panic=1\0" \ | |
160 | "flash_self=run ramargs addip;" \ | |
161 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
162 | "flash_nfs=run nfsargs addip;" \ | |
163 | "bootm ${kernel_addr}\0" \ | |
164 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
165 | "bootfile=/tftpboot/tqm5200/uImage\0" \ | |
166 | "load=tftp 200000 ${u-boot}\0" \ | |
167 | "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ | |
168 | "update=protect off FC000000 FC07FFFF;" \ | |
169 | "erase FC000000 FC07FFFF;" \ | |
170 | "cp.b 200000 FC000000 ${filesize};" \ | |
171 | "protect on FC000000 FC07FFFF\0" \ | |
172 | "" | |
173 | #else | |
b87dfd28 WD |
174 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
175 | "netdev=eth0\0" \ | |
176 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
177 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
178 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
179 | "nfsroot=${serverip}:${rootpath}\0" \ | |
180 | "addip=setenv bootargs ${bootargs} " \ | |
181 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
182 | ":${hostname}:${netdev}:off panic=1\0" \ | |
183 | "flash_self=run ramargs addip;" \ | |
184 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
185 | "flash_nfs=run nfsargs addip;" \ | |
186 | "bootm ${kernel_addr}\0" \ | |
187 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
188 | "bootfile=/tftpboot/tqm5200/uImage\0" \ | |
189 | "load=tftp 200000 $(u-boot)\0" \ | |
190 | "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ | |
191 | "update=protect off FC000000 FC05FFFF;" \ | |
192 | "erase FC000000 FC05FFFF;" \ | |
193 | "cp.b 200000 FC000000 ${filesize};" \ | |
194 | "protect on FC000000 FC05FFFF\0" \ | |
195 | "" | |
45a212c4 | 196 | #endif /* CONFIG_TQM5200_B */ |
b87dfd28 WD |
197 | |
198 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
199 | ||
200 | /* | |
201 | * IPB Bus clocking configuration. | |
202 | */ | |
c99512d6 | 203 | #define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
b87dfd28 | 204 | |
c99512d6 | 205 | #if defined(CFG_IPBCLK_EQUALS_XLBCLK) |
b87dfd28 WD |
206 | /* |
207 | * PCI Bus clocking configuration | |
208 | * | |
209 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
725671cc | 210 | * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock |
c99512d6 | 211 | * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. |
b87dfd28 | 212 | */ |
c99512d6 | 213 | #define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ |
b87dfd28 WD |
214 | #endif |
215 | ||
216 | /* | |
217 | * I2C configuration | |
218 | */ | |
219 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
220 | #define CFG_I2C_MODULE 2 /* Select I2C module #2 */ | |
221 | ||
222 | /* | |
223 | * I2C clock frequency | |
224 | * | |
225 | * Please notice, that the resulting clock frequency could differ from the | |
226 | * configured value. This is because the I2C clock is derived from system | |
227 | * clock over a frequency divider with only a few divider values. U-boot | |
228 | * calculates the best approximation for CFG_I2C_SPEED. However the calculated | |
229 | * approximation allways lies below the configured value, never above. | |
230 | */ | |
231 | #define CFG_I2C_SPEED 100000 /* 100 kHz */ | |
232 | #define CFG_I2C_SLAVE 0x7F | |
233 | ||
234 | /* | |
235 | * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work | |
236 | * also). For other EEPROMs configuration should be verified. On Mini-FAP the | |
237 | * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the | |
238 | * same configuration could be used. | |
239 | */ | |
240 | #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ | |
241 | #define CFG_I2C_EEPROM_ADDR_LEN 2 | |
242 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
243 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
244 | ||
245 | /* List of I2C addresses to be verified by POST */ | |
246 | #undef I2C_ADDR_LIST | |
247 | #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ | |
248 | CFG_I2C_RTC_ADDR, \ | |
249 | CFG_I2C_SLAVE } | |
250 | ||
251 | /* | |
252 | * Flash configuration | |
253 | */ | |
254 | #define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ | |
255 | ||
45a212c4 | 256 | /* use CFI flash driver */ |
b87dfd28 | 257 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 258 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
b87dfd28 WD |
259 | #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } |
260 | #define CFG_FLASH_EMPTY_INFO | |
261 | #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ | |
262 | #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
89366010 | 263 | #define CFG_FLASH_USE_BUFFER_WRITE 1 |
b87dfd28 WD |
264 | |
265 | #if !defined(CFG_LOWBOOT) | |
0e8d1586 | 266 | #define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) |
b87dfd28 | 267 | #else /* CFG_LOWBOOT */ |
45a212c4 | 268 | #if defined(CONFIG_TQM5200_B) |
0e8d1586 | 269 | #define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000) |
45a212c4 | 270 | #else |
0e8d1586 | 271 | #define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) |
45a212c4 | 272 | #endif /* CONFIG_TQM5200_B */ |
b87dfd28 WD |
273 | #endif /* CFG_LOWBOOT */ |
274 | #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks | |
275 | (= chip selects) */ | |
b87dfd28 WD |
276 | |
277 | /* Dynamic MTD partition support */ | |
278 | #define CONFIG_JFFS2_CMDLINE | |
279 | #define MTDIDS_DEFAULT "nor0=TQM5200-0" | |
45a212c4 WD |
280 | #if defined(CONFIG_TQM5200_B) |
281 | #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ | |
282 | "1280k(kernel)," \ | |
283 | "2m(initrd)," \ | |
284 | "4m(small-fs)," \ | |
285 | "16m(big-fs)," \ | |
286 | "8m(misc)" | |
287 | #else | |
b87dfd28 WD |
288 | #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ |
289 | "1408k(kernel)," \ | |
290 | "2m(initrd)," \ | |
291 | "4m(small-fs)," \ | |
292 | "16m(big-fs)," \ | |
293 | "8m(misc)" | |
45a212c4 | 294 | #endif /* CONFIG_TQM5200_B */ |
b87dfd28 WD |
295 | |
296 | /* | |
297 | * Environment settings | |
298 | */ | |
5a1aceb0 | 299 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 300 | #define CONFIG_ENV_SIZE 0x10000 |
45a212c4 | 301 | #if defined(CONFIG_TQM5200_B) |
0e8d1586 | 302 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
45a212c4 | 303 | #else |
0e8d1586 JCPV |
304 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
305 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
306 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
45a212c4 | 307 | #endif /* CONFIG_TQM5200_B */ |
b87dfd28 WD |
308 | |
309 | /* | |
310 | * Memory map | |
311 | */ | |
312 | #define CFG_MBAR 0xF0000000 | |
313 | #define CFG_SDRAM_BASE 0x00000000 | |
314 | #define CFG_DEFAULT_MBAR 0x80000000 | |
315 | ||
316 | /* Use ON-Chip SRAM until RAM will be available */ | |
317 | #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM | |
318 | #ifdef CONFIG_POST | |
319 | /* preserve space for the post_word at end of on-chip SRAM */ | |
320 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE | |
321 | #else | |
322 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE | |
323 | #endif | |
324 | ||
325 | ||
326 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
327 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
328 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
329 | ||
330 | #define CFG_MONITOR_BASE TEXT_BASE | |
331 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
332 | # define CFG_RAMBOOT 1 | |
333 | #endif | |
334 | ||
45a212c4 WD |
335 | #if defined(CONFIG_TQM5200_B) |
336 | #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ | |
337 | #else | |
b87dfd28 | 338 | #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
45a212c4 | 339 | #endif /* CONFIG_TQM5200_B */ |
33ed73bc | 340 | #define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ |
b87dfd28 WD |
341 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
342 | ||
343 | /* | |
344 | * Ethernet configuration | |
345 | */ | |
346 | #define CONFIG_MPC5xxx_FEC 1 | |
347 | /* | |
348 | * Define CONFIG_FEC_10MBIT to force FEC at 10Mb | |
349 | */ | |
350 | /* #define CONFIG_FEC_10MBIT 1 */ | |
351 | #define CONFIG_PHY_ADDR 0x00 | |
352 | ||
353 | /* | |
354 | * GPIO configuration | |
355 | * | |
356 | * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): | |
357 | * Bit 0 (mask: 0x80000000): 1 | |
358 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): | |
359 | * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. | |
360 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. | |
361 | * Use for REV200 STK52XX boards. Do not use with REV100 modules | |
362 | * (because, there I2C1 is used as I2C bus) | |
363 | * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 | |
364 | * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) | |
365 | * 000 -> All PSC2 pins are GIOPs | |
366 | * 001 -> CAN1/2 on PSC2 pins | |
367 | * Use for REV100 STK52xx boards | |
368 | * use PSC3: Bits 20:23 (mask: 0x00000300): | |
369 | * 0001 -> USB2 | |
370 | * 0000 -> GPIO | |
371 | * use PSC6: | |
372 | * on STK52xx: | |
373 | * use as UART. Pins PSC6_0 to PSC6_3 are used. | |
374 | * Bits 9:11 (mask: 0x00700000): | |
375 | * 101 -> PSC6 : Extended POST test is not available | |
376 | * on MINI-FAP and TQM5200_IB: | |
377 | * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): | |
378 | * 000 -> PSC6 could not be used as UART, CODEC or IrDA | |
379 | * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST | |
380 | * tests. | |
381 | */ | |
382 | #define CFG_GPS_PORT_CONFIG 0x81500114 | |
383 | ||
384 | /* | |
385 | * RTC configuration | |
386 | */ | |
387 | #define CONFIG_RTC_M41T11 1 | |
388 | #define CFG_I2C_RTC_ADDR 0x68 | |
389 | #define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base | |
390 | year */ | |
391 | ||
392 | /* | |
393 | * Miscellaneous configurable options | |
394 | */ | |
395 | #define CFG_LONGHELP /* undef to save memory */ | |
396 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
33ed73bc | 397 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
d794cfef | 398 | #if defined(CONFIG_CMD_KGDB) |
b87dfd28 WD |
399 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
400 | #else | |
401 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
402 | #endif | |
403 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
404 | #define CFG_MAXARGS 16 /* max number of command args */ | |
405 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
406 | ||
d794cfef JL |
407 | #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
408 | #if defined(CONFIG_CMD_KGDB) | |
409 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
410 | #endif | |
411 | ||
b87dfd28 WD |
412 | /* Enable an alternate, more extensive memory test */ |
413 | #define CFG_ALT_MEMTEST | |
414 | ||
415 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
416 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
417 | ||
418 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
419 | ||
420 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
421 | ||
422 | /* | |
a1aa0bb5 | 423 | * Enable loopw command. |
b87dfd28 WD |
424 | */ |
425 | #define CONFIG_LOOPW | |
426 | ||
427 | /* | |
428 | * Various low-level settings | |
429 | */ | |
430 | #if defined(CONFIG_MPC5200) | |
431 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI | |
432 | #define CFG_HID0_FINAL HID0_ICE | |
433 | #else | |
434 | #define CFG_HID0_INIT 0 | |
435 | #define CFG_HID0_FINAL 0 | |
436 | #endif | |
437 | ||
438 | #define CFG_BOOTCS_START CFG_FLASH_BASE | |
439 | #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE | |
c99512d6 | 440 | #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 |
b87dfd28 WD |
441 | #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ |
442 | #else | |
443 | #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ | |
444 | #endif | |
445 | #define CFG_CS0_START CFG_FLASH_BASE | |
446 | #define CFG_CS0_SIZE CFG_FLASH_SIZE | |
447 | ||
b87dfd28 | 448 | #define CONFIG_LAST_STAGE_INIT |
b87dfd28 WD |
449 | |
450 | /* | |
451 | * SRAM - Do not map below 2 GB in address space, because this area is used | |
452 | * for SDRAM autosizing. | |
453 | */ | |
b87dfd28 WD |
454 | #define CFG_CS2_START 0xE5000000 |
455 | #define CFG_CS2_SIZE 0x100000 /* 1 MByte */ | |
456 | #define CFG_CS2_CFG 0x0004D930 | |
b87dfd28 WD |
457 | |
458 | /* | |
459 | * Grafic controller - Do not map below 2 GB in address space, because this | |
460 | * area is used for SDRAM autosizing. | |
461 | */ | |
b87dfd28 WD |
462 | #define SM501_FB_BASE 0xE0000000 |
463 | #define CFG_CS1_START (SM501_FB_BASE) | |
464 | #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ | |
465 | #define CFG_CS1_CFG 0x8F48FF70 | |
466 | #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 | |
b87dfd28 WD |
467 | |
468 | #define CFG_CS_BURST 0x00000000 | |
469 | #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ | |
470 | ||
471 | #define CFG_RESET_ADDRESS 0xff000000 | |
472 | ||
473 | /*----------------------------------------------------------------------- | |
474 | * USB stuff | |
475 | *----------------------------------------------------------------------- | |
476 | */ | |
477 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
478 | #define CONFIG_USB_CONFIG 0x00001000 | |
479 | ||
480 | /*----------------------------------------------------------------------- | |
481 | * IDE/ATA stuff Supports IDE harddisk | |
482 | *----------------------------------------------------------------------- | |
483 | */ | |
484 | ||
485 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
486 | ||
487 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
488 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
489 | ||
490 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
491 | #define CONFIG_IDE_PREINIT | |
492 | ||
493 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
494 | #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
495 | ||
496 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
497 | ||
498 | #define CFG_ATA_BASE_ADDR MPC5XXX_ATA | |
499 | ||
500 | /* Offset for data I/O */ | |
501 | #define CFG_ATA_DATA_OFFSET (0x0060) | |
502 | ||
503 | /* Offset for normal register accesses */ | |
504 | #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) | |
505 | ||
506 | /* Offset for alternate registers */ | |
507 | #define CFG_ATA_ALT_OFFSET (0x005C) | |
508 | ||
509 | /* Interval between registers */ | |
510 | #define CFG_ATA_STRIDE 4 | |
511 | ||
512 | #endif /* __CONFIG_H */ |