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efc6f447 GL |
1 | /* |
2 | * (C) Copyright 2000-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* | |
28 | * board/config.h - configuration options, board specific | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
34 | /* | |
35 | * High Level Configuration Options | |
36 | * (easy to change) | |
37 | */ | |
38 | ||
39 | #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ | |
40 | #define CONFIG_TQM885D 1 /* ...on a TQM88D module */ | |
41 | #define CONFIG_TK885D 1 /* ...in a TK885D base board */ | |
42 | ||
43 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ | |
6d0f6bcf JCPV |
44 | #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ |
45 | #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ | |
efc6f447 GL |
46 | #define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ |
47 | /* (it will be used if there is no */ | |
48 | /* 'cpuclk' variable with valid value) */ | |
49 | ||
50 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
3cb7a480 WD |
51 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
52 | #define CONFIG_SYS_MAXIDLE 10 | |
efc6f447 GL |
53 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
54 | ||
55 | #define CONFIG_BOOTCOUNT_LIMIT | |
56 | ||
57 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
58 | ||
59 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
60 | ||
61 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 62 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
efc6f447 GL |
63 | "echo" |
64 | ||
65 | #undef CONFIG_BOOTARGS | |
66 | ||
67 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
2b4f778f WD |
68 | "ethprime=FEC ETHERNET\0" \ |
69 | "ethact=FEC ETHERNET\0" \ | |
efc6f447 GL |
70 | "netdev=eth0\0" \ |
71 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
72 | "nfsroot=${serverip}:${rootpath}\0" \ | |
73 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
74 | "addip=setenv bootargs ${bootargs} " \ | |
75 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
76 | ":${hostname}:${netdev}:off panic=1\0" \ | |
77 | "flash_nfs=run nfsargs addip;" \ | |
78 | "bootm ${kernel_addr}\0" \ | |
79 | "flash_self=run ramargs addip;" \ | |
80 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
81 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
82 | "rootpath=/opt/eldk/ppc_8xx\0" \ | |
2b4f778f WD |
83 | "bootfile=/tftpboot/tk885d/uImage\0" \ |
84 | "u-boot=/tftpboot/tk885d/u-boot.bin\0" \ | |
efc6f447 GL |
85 | "kernel_addr=40080000\0" \ |
86 | "ramdisk_addr=40180000\0" \ | |
87 | "load=tftp 200000 ${u-boot}\0" \ | |
88 | "update=protect off 40000000 +${filesize};" \ | |
89 | "erase 40000000 +${filesize};" \ | |
90 | "cp.b 200000 40000000 ${filesize};" \ | |
91 | "protect on 40000000 +${filesize}\0" \ | |
92 | "" | |
93 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
94 | ||
95 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 96 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
efc6f447 GL |
97 | |
98 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
99 | ||
100 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
101 | ||
102 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
103 | ||
104 | /* enable I2C and select the hardware/software driver */ | |
105 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
106 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
107 | ||
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ |
109 | #define CONFIG_SYS_I2C_SLAVE 0xFE | |
efc6f447 GL |
110 | |
111 | #ifdef CONFIG_SOFT_I2C | |
112 | /* | |
113 | * Software (bit-bang) I2C driver configuration | |
114 | */ | |
115 | #define PB_SCL 0x00000020 /* PB 26 */ | |
116 | #define PB_SDA 0x00000010 /* PB 27 */ | |
117 | ||
118 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
119 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
120 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
121 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
122 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
123 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
124 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
125 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
126 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ | |
127 | #endif /* CONFIG_SOFT_I2C */ | |
128 | ||
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ |
130 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ | |
131 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
132 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
efc6f447 GL |
133 | |
134 | # define CONFIG_RTC_DS1337 1 | |
6d0f6bcf | 135 | # define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
efc6f447 GL |
136 | |
137 | /* | |
138 | * BOOTP options | |
139 | */ | |
140 | #define CONFIG_BOOTP_SUBNETMASK | |
141 | #define CONFIG_BOOTP_GATEWAY | |
142 | #define CONFIG_BOOTP_HOSTNAME | |
143 | #define CONFIG_BOOTP_BOOTPATH | |
144 | #define CONFIG_BOOTP_BOOTFILESIZE | |
145 | ||
146 | ||
147 | #define CONFIG_MAC_PARTITION | |
148 | #define CONFIG_DOS_PARTITION | |
149 | ||
150 | #undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ | |
151 | ||
152 | #define CONFIG_TIMESTAMP /* but print image timestmps */ | |
153 | ||
154 | ||
155 | /* | |
156 | * Command line configuration. | |
157 | */ | |
158 | #include <config_cmd_default.h> | |
159 | ||
160 | #define CONFIG_CMD_ASKENV | |
161 | #define CONFIG_CMD_DATE | |
162 | #define CONFIG_CMD_DHCP | |
163 | #define CONFIG_CMD_EEPROM | |
164 | #define CONFIG_CMD_I2C | |
165 | #define CONFIG_CMD_IDE | |
166 | #define CONFIG_CMD_MII | |
167 | #define CONFIG_CMD_NFS | |
168 | #define CONFIG_CMD_PING | |
169 | ||
170 | ||
171 | /* | |
172 | * Miscellaneous configurable options | |
173 | */ | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
175 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
efc6f447 GL |
176 | |
177 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
179 | #ifdef CONFIG_SYS_HUSH_PARSER | |
180 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
efc6f447 GL |
181 | #endif |
182 | ||
183 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 184 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
efc6f447 | 185 | #else |
6d0f6bcf | 186 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
efc6f447 | 187 | #endif |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
189 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
190 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
efc6f447 | 191 | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
193 | #define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ | |
194 | #define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive | |
efc6f447 GL |
195 | memory test.*/ |
196 | ||
6d0f6bcf | 197 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
efc6f447 | 198 | |
6d0f6bcf | 199 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
efc6f447 | 200 | |
6d0f6bcf | 201 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
efc6f447 GL |
202 | |
203 | /* | |
204 | * Enable loopw command. | |
205 | */ | |
206 | #define CONFIG_LOOPW | |
207 | ||
208 | /* | |
209 | * Low Level Configuration Settings | |
210 | * (address mappings, register initial values, etc.) | |
211 | * You should know what you are doing if you make changes here. | |
212 | */ | |
213 | /*----------------------------------------------------------------------- | |
214 | * Internal Memory Mapped Register | |
215 | */ | |
6d0f6bcf | 216 | #define CONFIG_SYS_IMMR 0xFFF00000 |
efc6f447 GL |
217 | |
218 | /*----------------------------------------------------------------------- | |
219 | * Definitions for initial stack pointer and data area (in DPRAM) | |
220 | */ | |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
222 | #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
223 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
224 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
225 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
efc6f447 GL |
226 | |
227 | /*----------------------------------------------------------------------- | |
228 | * Start addresses for the final memory configuration | |
229 | * (Set up by the startup code) | |
6d0f6bcf | 230 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
efc6f447 | 231 | */ |
6d0f6bcf JCPV |
232 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
233 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
234 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
235 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
236 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ | |
efc6f447 GL |
237 | |
238 | /* | |
239 | * For booting Linux, the board info and command line data | |
240 | * have to be in the first 8 MB of memory, since this is | |
241 | * the maximum mapped by the Linux kernel during initialization. | |
242 | */ | |
6d0f6bcf | 243 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
efc6f447 GL |
244 | |
245 | /*----------------------------------------------------------------------- | |
246 | * FLASH organization | |
247 | */ | |
248 | ||
249 | /* use CFI flash driver */ | |
6d0f6bcf | 250 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 251 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
253 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
254 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
255 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
256 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
efc6f447 | 257 | |
5a1aceb0 | 258 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
259 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
260 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ | |
261 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ | |
efc6f447 GL |
262 | |
263 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
264 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
265 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
efc6f447 GL |
266 | |
267 | /*----------------------------------------------------------------------- | |
268 | * Hardware Information Block | |
269 | */ | |
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
271 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
272 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
efc6f447 GL |
273 | |
274 | /*----------------------------------------------------------------------- | |
275 | * Cache Configuration | |
276 | */ | |
6d0f6bcf | 277 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
efc6f447 | 278 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 279 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
efc6f447 GL |
280 | #endif |
281 | ||
282 | /*----------------------------------------------------------------------- | |
283 | * SYPCR - System Protection Control 11-9 | |
284 | * SYPCR can only be written once after reset! | |
285 | *----------------------------------------------------------------------- | |
286 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
287 | */ | |
288 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 289 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
efc6f447 GL |
290 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
291 | #else | |
6d0f6bcf | 292 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
efc6f447 GL |
293 | #endif |
294 | ||
295 | /*----------------------------------------------------------------------- | |
296 | * SIUMCR - SIU Module Configuration 11-6 | |
297 | *----------------------------------------------------------------------- | |
298 | * PCMCIA config., multi-function pin tri-state | |
299 | */ | |
300 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf | 301 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
efc6f447 | 302 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 303 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
efc6f447 GL |
304 | #endif /* CONFIG_CAN_DRIVER */ |
305 | ||
306 | /*----------------------------------------------------------------------- | |
307 | * TBSCR - Time Base Status and Control 11-26 | |
308 | *----------------------------------------------------------------------- | |
309 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
310 | */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
efc6f447 GL |
312 | |
313 | /*----------------------------------------------------------------------- | |
314 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
315 | *----------------------------------------------------------------------- | |
316 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
317 | */ | |
6d0f6bcf | 318 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
efc6f447 GL |
319 | |
320 | /*----------------------------------------------------------------------- | |
321 | * SCCR - System Clock and reset Control Register 15-27 | |
322 | *----------------------------------------------------------------------- | |
323 | * Set clock output, timebase and RTC source and divider, | |
324 | * power management and some other internal clocks | |
325 | */ | |
326 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 327 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
efc6f447 GL |
328 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
329 | SCCR_DFALCD00) | |
330 | ||
331 | /*----------------------------------------------------------------------- | |
332 | * PCMCIA stuff | |
333 | *----------------------------------------------------------------------- | |
334 | * | |
335 | */ | |
6d0f6bcf JCPV |
336 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
337 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
338 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
339 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
340 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
341 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
342 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
343 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
efc6f447 GL |
344 | |
345 | /*----------------------------------------------------------------------- | |
346 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
347 | *----------------------------------------------------------------------- | |
348 | */ | |
349 | ||
350 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
351 | ||
352 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
353 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
354 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
355 | ||
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
357 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
efc6f447 | 358 | |
6d0f6bcf | 359 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
efc6f447 | 360 | |
6d0f6bcf | 361 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
efc6f447 GL |
362 | |
363 | /* Offset for data I/O */ | |
6d0f6bcf | 364 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
efc6f447 GL |
365 | |
366 | /* Offset for normal register accesses */ | |
6d0f6bcf | 367 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
efc6f447 GL |
368 | |
369 | /* Offset for alternate registers */ | |
6d0f6bcf | 370 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
efc6f447 GL |
371 | |
372 | /*----------------------------------------------------------------------- | |
373 | * | |
374 | *----------------------------------------------------------------------- | |
375 | * | |
376 | */ | |
6d0f6bcf | 377 | #define CONFIG_SYS_DER 0 |
efc6f447 GL |
378 | |
379 | /* | |
380 | * Init Memory Controller: | |
381 | * | |
382 | * BR0/1 and OR0/1 (FLASH) | |
383 | */ | |
384 | ||
385 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
386 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
387 | ||
388 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
389 | * restrict access enough to keep SRAM working (if any) | |
390 | * but not too much to meddle with FLASH accesses | |
391 | */ | |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
393 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
efc6f447 GL |
394 | |
395 | /* | |
396 | * FLASH timing: Default value of OR0 after reset | |
397 | */ | |
6d0f6bcf | 398 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ |
efc6f447 GL |
399 | OR_SCY_6_CLK | OR_TRLX) |
400 | ||
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
402 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
403 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
efc6f447 | 404 | |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
406 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
407 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
efc6f447 GL |
408 | |
409 | /* | |
410 | * BR2/3 and OR2/3 (SDRAM) | |
411 | * | |
412 | */ | |
413 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
414 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
415 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ | |
416 | ||
417 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 418 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
efc6f447 | 419 | |
6d0f6bcf JCPV |
420 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
421 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
efc6f447 GL |
422 | |
423 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf JCPV |
424 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
425 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
efc6f447 | 426 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
6d0f6bcf JCPV |
427 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
428 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
429 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
430 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
efc6f447 GL |
431 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
432 | #endif /* CONFIG_CAN_DRIVER */ | |
433 | ||
434 | /* | |
435 | * 4096 Rows from SDRAM example configuration | |
436 | * 1000 factor s -> ms | |
437 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
438 | * 4 Number of refresh cycles per period | |
439 | * 64 Refresh cycle in ms per number of rows | |
440 | */ | |
6d0f6bcf | 441 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) |
efc6f447 GL |
442 | |
443 | /* | |
444 | * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) | |
445 | * | |
446 | * CPUclock(MHz) * 31.2 | |
6d0f6bcf | 447 | * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 |
efc6f447 GL |
448 | * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 |
449 | * | |
6d0f6bcf JCPV |
450 | * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us |
451 | * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us | |
452 | * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us | |
453 | * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us | |
efc6f447 GL |
454 | * |
455 | * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will | |
456 | * be met also in the default configuration, i.e. if environment variable | |
457 | * 'cpuclk' is not set. | |
458 | */ | |
6d0f6bcf | 459 | #define CONFIG_SYS_MAMR_PTA 128 |
efc6f447 GL |
460 | |
461 | /* | |
462 | * Memory Periodic Timer Prescaler Register (MPTPR) values. | |
463 | */ | |
464 | /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ | |
6d0f6bcf | 465 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 |
efc6f447 | 466 | /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ |
6d0f6bcf | 467 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 |
efc6f447 GL |
468 | |
469 | /* | |
470 | * MAMR settings for SDRAM | |
471 | */ | |
472 | ||
473 | /* 8 column SDRAM */ | |
6d0f6bcf | 474 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
efc6f447 GL |
475 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
476 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
477 | /* 9 column SDRAM */ | |
6d0f6bcf | 478 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
efc6f447 GL |
479 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
480 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
481 | /* 10 column SDRAM */ | |
6d0f6bcf | 482 | #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
efc6f447 GL |
483 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ |
484 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
485 | ||
486 | /* | |
487 | * Internal Definitions | |
488 | * | |
489 | * Boot Flags | |
490 | */ | |
491 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
492 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
493 | ||
494 | /* | |
495 | * Network configuration | |
496 | */ | |
497 | #define CONFIG_FEC_ENET /* enable ethernet on FEC */ | |
498 | #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ | |
499 | #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ | |
500 | ||
501 | #define CONFIG_LAST_STAGE_INIT 1 /* Have to configure PHYs for Linux */ | |
502 | ||
6d0f6bcf | 503 | /* CONFIG_SYS_DISCOVER_PHY only works with FEC if only one interface is enabled */ |
efc6f447 | 504 | #if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2)) |
6d0f6bcf | 505 | #define CONFIG_SYS_DISCOVER_PHY |
efc6f447 GL |
506 | #endif |
507 | ||
6d0f6bcf | 508 | #ifndef CONFIG_SYS_DISCOVER_PHY |
efc6f447 GL |
509 | /* PHY addresses - hard wired in hardware */ |
510 | #define CONFIG_FEC1_PHY 1 | |
511 | #define CONFIG_FEC2_PHY 2 | |
512 | #endif | |
513 | ||
0f3ba7e9 TL |
514 | #define CONFIG_MII_INIT 1 |
515 | ||
efc6f447 GL |
516 | #define CONFIG_NET_RETRY_COUNT 3 |
517 | #define CONFIG_ETHPRIME "FEC ETHERNET" | |
518 | ||
519 | #endif /* __CONFIG_H */ |