[people/ms/u-boot.git] / include / configs / TOP5200.h

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
 *
 * TOP5200 differences from IceCube:
 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
 *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
 * 1 SDRAM/DDRAM Bank up to 256 MB
 * local VPD I2C Bus is software driven and uses
 *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
 * FLASH is re-located at 0xff000000
 * Internal regs are at 0xf0000000
 * Reset jumps to 0x00000100
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
#define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */

/*
 * allowed and functional CONFIG_SYS_TEXT_BASE values:
 * 0xff000000	low boot at 0x00000100 (default board setting)
 * 0xfff00000	high boot at 0xfff00100 (board needs modification)
 * 0x00100000	RAM load and test
 */
#define	CONFIG_SYS_TEXT_BASE	0xff000000

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#  define CONFIG_PCI		1
#  define CONFIG_PCI_PNP		1
#  define CONFIG_PCI_SCAN_SHOW	1
#  define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#  define CONFIG_PCI_MEM_BUS	0x40000000
#  define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#  define CONFIG_PCI_MEM_SIZE	0x10000000

#  define CONFIG_PCI_IO_BUS	0x50000000
#  define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#  define CONFIG_PCI_IO_SIZE	0x01000000

#endif

/* USB */
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)

#  define CONFIG_USB_OHCI
#  define CONFIG_USB_CLOCK	0x0001bbbb
#  if defined (CONFIG_EVAL5200)
#    define CONFIG_USB_CONFIG	0x00005100
#  else
#    define CONFIG_USB_CONFIG	0x00001000
#  endif
#  define CONFIG_DOS_PARTITION
#  define CONFIG_USB_STORAGE

#endif

/* IDE */
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
#  define CONFIG_DOS_PARTITION
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_REGINFO

#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_USB
#define CONFIG_CMD_PCI
#endif


/*
 * MUST be low boot - HIGHBOOT is not supported anymore
 */
#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
#   define CONFIG_SYS_LOWBOOT		1
#   define CONFIG_SYS_LOWBOOT16	1
#else
#   error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
/*
 * EEPROM configuration
 */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_SIZE 0x2000

#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R

#undef	CONFIG_HARD_I2C			/* I2C with hardware support */
#define	CONFIG_SOFT_I2C		1	/* I2C with softwate support */

#if defined (CONFIG_SOFT_I2C)
#  define SDA0			0x40
#  define SCL0			0x80
#  define GPIOE0		*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
#  define DDR0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
#  define DVO0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
#  define DVI0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
#  define ODE0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
#  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
#  define I2C_READ		((DVI0&SDA0)?1:0)
#  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
#  define I2C_SCL(x)	{if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
#  define I2C_DELAY		{udelay(5);}
#  define I2C_ACTIVE	{DDR0|=SDA0;}
#  define I2C_TRISTATE	{DDR0&=~SDA0;}
#  define CONFIG_SYS_I2C_SPEED		100000
#  define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_FACT_ADDR	0x57
#endif

#if defined (CONFIG_HARD_I2C)
#  define CONFIG_SYS_I2C_MODULE	2		/* Select I2C module #1 or #2 */
#  define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
#  define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_FACT_ADDR	0x54
#endif

/*
 * Flash configuration, expect one 16 Megabyte Bank at most
 */
#define CONFIG_SYS_FLASH_BASE		0xff000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0)

#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */

/*
 * DRAM configuration - will be read from VPD later... TODO!
 */
#if 0
/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
#define	CONFIG_SYS_DRAM_DDR		0
#define CONFIG_SYS_DRAM_EMODE		0
#define CONFIG_SYS_DRAM_MODE		0x008D
#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
#define CONFIG_SYS_DRAM_CONFIG1	0xC2233A00
#define CONFIG_SYS_DRAM_CONFIG2	0x88B70004
#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
#endif
#if 1
/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
#define	CONFIG_SYS_DRAM_DDR		0
#define CONFIG_SYS_DRAM_EMODE		0
#define CONFIG_SYS_DRAM_MODE		0x00CD
#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
#define CONFIG_SYS_DRAM_CONFIG1	0xD2333A00
#define CONFIG_SYS_DRAM_CONFIG2	0x8AD70004
#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
#endif

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
#define CONFIG_ENV_OFFSET		0x1000
#define CONFIG_ENV_SIZE		0x0700

/*
 * VPD settings
 */
#define CONFIG_SYS_FACT_OFFSET		0x1800
#define CONFIG_SYS_FACT_SIZE		0x0800

/*
 * Memory map
 *
 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
 */
#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII10	/* Workaround for FEC 100Mbit problem */
#define	CONFIG_PHY_ADDR		0x1f
#define	CONFIG_PHY_TYPE		0x79c874
/*
 * GPIO configuration:
 * PSC1,2,3 predefined as UART
 * PCI disabled
 * Ethernet 100 with MD
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif


#ifdef CONFIG_EVAL5200		/* M48T08 is available with the Evaluation board only */
  #define CONFIG_RTC_MK48T59	1	/* use M48T08 on EVAL5200 */
  #define RTC(reg)		(0xf0010000+reg)
  /* setup CS2 for M48T08. Must MAP 64kB */
  #define CONFIG_SYS_CS2_START	RTC(0)
  #define CONFIG_SYS_CS2_SIZE	0x10000
  /* setup CS2 configuration register: */
  /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
  /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
  #define CONFIG_SYS_CS2_CFG	0x00047800
#else
  #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0x7f000000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define CONFIG_IDE_RESET	1
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005c)

/* Interval between registers                                                */
#define CONFIG_SYS_ATA_STRIDE          4

#endif /* __CONFIG_H */
Commit	Line	Data
c1896004 WD	1	/*
c1896004 WD	2	* (C) Copyright 2003
d4ca31c4 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
	6	*
	7	* TOP5200 differences from IceCube:
	8	* 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
	9	* bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
	10	* 1 SDRAM/DDRAM Bank up to 256 MB
	11	* local VPD I2C Bus is software driven and uses
	12	* GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
	13	* FLASH is re-located at 0xff000000
	14	* Internal regs are at 0xf0000000
c1896004 WD	15	* Reset jumps to 0x00000100
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
	43
cbd8a35c	44	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
c1896004 WD	45	#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
	46	#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
	47
2ae18241 WD	48	/*
	49	* allowed and functional CONFIG_SYS_TEXT_BASE values:
	50	* 0xff000000 low boot at 0x00000100 (default board setting)
	51	* 0xfff00000 high boot at 0xfff00100 (board needs modification)
	52	* 0x00100000 RAM load and test
	53	*/
	54	#define CONFIG_SYS_TEXT_BASE 0xff000000
	55
6d0f6bcf	56	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
c1896004	57
31d82672 BB	58	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	59
c1896004 WD	60	/*
	61	* Serial console configuration
	62	*/
	63	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	64	#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
6d0f6bcf	65	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
c1896004 WD	66
c1896004 WD	67
4d13cbad	68	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
c1896004 WD	69	/*
	70	* PCI Mapping:
	71	* 0x40000000 - 0x4fffffff - PCI Memory
	72	* 0x50000000 - 0x50ffffff - PCI IO Space
	73	*/
	74	# define CONFIG_PCI 1
	75	# define CONFIG_PCI_PNP 1
	76	# define CONFIG_PCI_SCAN_SHOW 1
f33fca22	77	# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
c1896004 WD	78
	79	# define CONFIG_PCI_MEM_BUS 0x40000000
	80	# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	81	# define CONFIG_PCI_MEM_SIZE 0x10000000
	82
	83	# define CONFIG_PCI_IO_BUS 0x50000000
	84	# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	85	# define CONFIG_PCI_IO_SIZE 0x01000000
	86
c1896004 WD	87	#endif
c1896004 WD	88
4d13cbad WD	89	/* USB */
	90	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
	91
	92	# define CONFIG_USB_OHCI
	93	# define CONFIG_USB_CLOCK 0x0001bbbb
498b8db7 WD	94	# if defined (CONFIG_EVAL5200)
	95	# define CONFIG_USB_CONFIG 0x00005100
	96	# else
	97	# define CONFIG_USB_CONFIG 0x00001000
	98	# endif
4d13cbad WD	99	# define CONFIG_DOS_PARTITION
	100	# define CONFIG_USB_STORAGE
	101
4d13cbad WD	102	#endif
	103
	104	/* IDE */
	105	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
4d13cbad	106	# define CONFIG_DOS_PARTITION
d794cfef	107	#endif
4d13cbad	108
4d13cbad	109
a1aa0bb5 JL	110	/*
	111	* BOOTP options
	112	*/
	113	#define CONFIG_BOOTP_BOOTFILESIZE
	114	#define CONFIG_BOOTP_BOOTPATH
	115	#define CONFIG_BOOTP_GATEWAY
	116	#define CONFIG_BOOTP_HOSTNAME
	117
	118
d794cfef JL	119	/*
	120	* Command line configuration.
	121	*/
	122	#include <config_cmd_default.h>
	123
	124	#define CONFIG_CMD_ASKENV
	125	#define CONFIG_CMD_BEDBUG
	126	#define CONFIG_CMD_DATE
	127	#define CONFIG_CMD_DHCP
	128	#define CONFIG_CMD_EEPROM
	129	#define CONFIG_CMD_ELF
	130	#define CONFIG_CMD_I2C
	131	#define CONFIG_CMD_IMMAP
	132	#define CONFIG_CMD_MII
	133	#define CONFIG_CMD_REGINFO
4d13cbad	134
d794cfef JL	135	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
	136	#define CONFIG_CMD_FAT
	137	#define CONFIG_CMD_IDE
	138	#define CONFIG_CMD_USB
	139	#define CONFIG_CMD_PCI
4d13cbad WD	140	#endif
4d13cbad WD	141
c1896004	142
d4ca31c4	143	/*
4d13cbad	144	* MUST be low boot - HIGHBOOT is not supported anymore
d4ca31c4	145	*/
14d0a02a	146	#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
6d0f6bcf JCPV	147	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	148	# define CONFIG_SYS_LOWBOOT16 1
4d13cbad	149	#else
14d0a02a	150	# error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
d4ca31c4 WD	151	#endif
d4ca31c4 WD	152
c1896004 WD	153	/*
	154	* Autobooting
	155	*/
	156	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
d4ca31c4 WD	157
d4ca31c4 WD	158	#define CONFIG_PREBOOT "echo;" \
32bf3d14	159	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
d4ca31c4 WD	160	"echo"
	161
	162	#undef CONFIG_BOOTARGS
	163
	164	#define CONFIG_EXTRA_ENV_SETTINGS \
	165	"netdev=eth0\0" \
	166	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	167	"nfsroot=${serverip}:${rootpath}\0" \
d4ca31c4	168	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	169	"addip=setenv bootargs ${bootargs} " \
	170	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	171	":${hostname}:${netdev}:off panic=1\0" \
d4ca31c4	172	"flash_nfs=run nfsargs addip;" \
fe126d8b	173	"bootm ${kernel_addr}\0" \
d4ca31c4	174	"flash_self=run ramargs addip;" \
fe126d8b WD	175	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	176	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
d4ca31c4 WD	177	"rootpath=/opt/eldk/ppc_82xx\0" \
	178	"bootfile=/tftpboot/MPC5200/uImage\0" \
	179	""
	180
	181	#define CONFIG_BOOTCOMMAND "run flash_self"
c1896004 WD	182
	183	/*
	184	* IPB Bus clocking configuration.
	185	*/
6d0f6bcf	186	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
d4ca31c4	187
c1896004 WD	188	/*
	189	* I2C configuration
	190	*/
	191	/*
	192	* EEPROM configuration
	193	*/
6d0f6bcf JCPV	194	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
6d0f6bcf JCPV	195	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
c1896004	196
6d0f6bcf JCPV	197	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
6d0f6bcf JCPV	198	#define CONFIG_SYS_EEPROM_SIZE 0x2000
d4ca31c4	199
c1896004 WD	200	#define CONFIG_ENV_OVERWRITE
c1896004 WD	201	#define CONFIG_MISC_INIT_R
d4ca31c4	202
c1896004	203	#undef CONFIG_HARD_I2C /* I2C with hardware support */
4d13cbad	204	#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */
d4ca31c4	205
c1896004 WD	206	#if defined (CONFIG_SOFT_I2C)
	207	# define SDA0 0x40
	208	# define SCL0 0x80
6d0f6bcf JCPV	209	# define GPIOE0 ((volatile uchar)(CONFIG_SYS_MBAR+0x0c00))
	210	# define DDR0 ((volatile uchar)(CONFIG_SYS_MBAR+0x0c08))
	211	# define DVO0 ((volatile uchar)(CONFIG_SYS_MBAR+0x0c0c))
	212	# define DVI0 ((volatile uchar)(CONFIG_SYS_MBAR+0x0c20))
	213	# define ODE0 ((volatile uchar)(CONFIG_SYS_MBAR+0x0c04))
c1896004 WD	214	# define I2C_INIT {GPIOE0\|=(SDA0\|SCL0);ODE0\|=(SDA0\|SCL0);DVO0\|=(SDA0\|SCL0);DDR0\|=(SDA0\|SCL0);}
	215	# define I2C_READ ((DVI0&SDA0)?1:0)
	216	# define I2C_SDA(x) {if(x)DVO0\|=SDA0;else DVO0&=~SDA0;}
	217	# define I2C_SCL(x) {if(x)DVO0\|=SCL0;else DVO0&=~SCL0;}
	218	# define I2C_DELAY {udelay(5);}
	219	# define I2C_ACTIVE {DDR0\|=SDA0;}
	220	# define I2C_TRISTATE {DDR0&=~SDA0;}
6d0f6bcf JCPV	221	# define CONFIG_SYS_I2C_SPEED 100000
	222	# define CONFIG_SYS_I2C_SLAVE 0x7F
	223	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	224	#define CONFIG_SYS_I2C_FACT_ADDR 0x57
c1896004	225	#endif
d4ca31c4 WD	226
d4ca31c4 WD	227	#if defined (CONFIG_HARD_I2C)
6d0f6bcf JCPV	228	# define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	229	# define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
	230	# define CONFIG_SYS_I2C_SLAVE 0x7F
	231	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
	232	#define CONFIG_SYS_I2C_FACT_ADDR 0x54
d4ca31c4	233	#endif
c1896004 WD	234
	235	/*
	236	* Flash configuration, expect one 16 Megabyte Bank at most
	237	*/
6d0f6bcf JCPV	238	#define CONFIG_SYS_FLASH_BASE 0xff000000
	239	#define CONFIG_SYS_FLASH_SIZE 0x01000000
	240	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	241	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0)
c1896004	242
6d0f6bcf	243	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
c1896004	244
6d0f6bcf JCPV	245	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	246	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
c1896004 WD	247
	248	#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
	249
d4ca31c4 WD	250	/*
	251	* DRAM configuration - will be read from VPD later... TODO!
	252	*/
	253	#if 0
	254	/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
6d0f6bcf JCPV	255	#define CONFIG_SYS_DRAM_DDR 0
	256	#define CONFIG_SYS_DRAM_EMODE 0
	257	#define CONFIG_SYS_DRAM_MODE 0x008D
	258	#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
	259	#define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00
	260	#define CONFIG_SYS_DRAM_CONFIG2 0x88B70004
	261	#define CONFIG_SYS_DRAM_TAP_DEL 0x08
	262	#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
d4ca31c4 WD	263	#endif
	264	#if 1
	265	/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
6d0f6bcf JCPV	266	#define CONFIG_SYS_DRAM_DDR 0
	267	#define CONFIG_SYS_DRAM_EMODE 0
	268	#define CONFIG_SYS_DRAM_MODE 0x00CD
	269	#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
	270	#define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00
	271	#define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004
	272	#define CONFIG_SYS_DRAM_TAP_DEL 0x08
	273	#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
d4ca31c4 WD	274	#endif
d4ca31c4 WD	275
c1896004 WD	276	/*
	277	* Environment settings
	278	*/
bb1f8b4f	279	#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
0e8d1586 JCPV	280	#define CONFIG_ENV_OFFSET 0x1000
0e8d1586 JCPV	281	#define CONFIG_ENV_SIZE 0x0700
c1896004	282
d4ca31c4 WD	283	/*
	284	* VPD settings
	285	*/
6d0f6bcf JCPV	286	#define CONFIG_SYS_FACT_OFFSET 0x1800
6d0f6bcf JCPV	287	#define CONFIG_SYS_FACT_SIZE 0x0800
d4ca31c4	288
c1896004	289	/*
d4ca31c4 WD	290	* Memory map
	291	*
	292	* Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
c1896004	293	*/
6d0f6bcf JCPV	294	#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
	295	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	296	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
c1896004 WD	297
c1896004 WD	298	/* Use SRAM until RAM will be available */
6d0f6bcf	299	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	300	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
c1896004 WD	301
c1896004 WD	302
25ddd1fb	303	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	304	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c1896004	305
14d0a02a	306	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	307	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	308	# define CONFIG_SYS_RAMBOOT 1
c1896004 WD	309	#endif
c1896004 WD	310
6d0f6bcf JCPV	311	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	312	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	313	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c1896004 WD	314
	315	/*
	316	* Ethernet configuration
	317	*/
cbd8a35c	318	#define CONFIG_MPC5xxx_FEC 1
86321fc1	319	#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */
d4ca31c4	320	#define CONFIG_PHY_ADDR 0x1f
c1896004 WD	321	#define CONFIG_PHY_TYPE 0x79c874
c1896004 WD	322	/*
d4ca31c4 WD	323	* GPIO configuration:
	324	* PSC1,2,3 predefined as UART
	325	* PCI disabled
c1896004 WD	326	* Ethernet 100 with MD
c1896004 WD	327	*/
6d0f6bcf	328	#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044
c1896004 WD	329
	330	/*
	331	* Miscellaneous configurable options
	332	*/
6d0f6bcf JCPV	333	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	334	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
d794cfef	335	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	336	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c1896004	337	#else
6d0f6bcf	338	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c1896004	339	#endif
6d0f6bcf JCPV	340	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	341	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	342	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c1896004	343
6d0f6bcf JCPV	344	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	345	#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
c1896004	346
6d0f6bcf	347	#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
c1896004	348
6d0f6bcf	349	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c1896004	350
6d0f6bcf	351	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
d794cfef	352	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	353	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
d794cfef JL	354	#endif
	355
	356
63e73c9a WD	357	#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
	358	#define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
	359	#define RTC(reg) (0xf0010000+reg)
	360	/* setup CS2 for M48T08. Must MAP 64kB */
6d0f6bcf JCPV	361	#define CONFIG_SYS_CS2_START RTC(0)
6d0f6bcf JCPV	362	#define CONFIG_SYS_CS2_SIZE 0x10000
63e73c9a WD	363	/* setup CS2 configuration register: */
	364	/* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
	365	/* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
6d0f6bcf	366	#define CONFIG_SYS_CS2_CFG 0x00047800
63e73c9a WD	367	#else
	368	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
	369	#endif
1c43771b	370
c1896004 WD	371	/*
	372	* Various low-level settings
	373	*/
6d0f6bcf JCPV	374	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	375	#define CONFIG_SYS_HID0_FINAL HID0_ICE
c1896004	376
6d0f6bcf JCPV	377	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	378	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	379	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	380	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	381	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
c1896004	382
6d0f6bcf JCPV	383	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	384	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
c1896004	385
6d0f6bcf	386	#define CONFIG_SYS_RESET_ADDRESS 0x7f000000
c1896004	387
4d13cbad WD	388	/*-----------------------------------------------------------------------
	389	* IDE/ATA stuff Supports IDE harddisk
	390	*-----------------------------------------------------------------------
	391	*/
	392
	393	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	394
	395	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	396	#undef CONFIG_IDE_LED /* LED for ide not supported */
	397
	398	#define CONFIG_IDE_RESET 1
	399	#define CONFIG_IDE_PREINIT
	400
6d0f6bcf JCPV	401	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	402	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
4d13cbad	403
6d0f6bcf	404	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
4d13cbad	405
6d0f6bcf	406	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
4d13cbad WD	407
4d13cbad WD	408	/* Offset for data I/O */
6d0f6bcf	409	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
4d13cbad WD	410
4d13cbad WD	411	/* Offset for normal register accesses */
6d0f6bcf	412	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
4d13cbad WD	413
4d13cbad WD	414	/* Offset for alternate registers */
6d0f6bcf	415	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005c)
4d13cbad WD	416
4d13cbad WD	417	/* Interval between registers */
6d0f6bcf	418	#define CONFIG_SYS_ATA_STRIDE 4
4d13cbad	419
c1896004	420	#endif /* __CONFIG_H */