[people/ms/u-boot.git] / include / configs / TOP5200.h

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
 *
 * TOP5200 differences from IceCube:
 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
 *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
 * 1 SDRAM/DDRAM Bank up to 256 MB
 * local VPD I2C Bus is software driven and uses
 *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
 * FLASH is re-located at 0xff000000
 * Internal regs are at 0xf0000000
 * Reset jumps to 0x00000100
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
#define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */

/*
 * allowed and functional CONFIG_SYS_TEXT_BASE values:
 * 0xff000000	low boot at 0x00000100 (default board setting)
 * 0xfff00000	high boot at 0xfff00100 (board needs modification)
 * 0x00100000	RAM load and test
 */
#define	CONFIG_SYS_TEXT_BASE	0xff000000

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#  define CONFIG_PCI		1
#  define CONFIG_PCI_PNP		1
#  define CONFIG_PCI_SCAN_SHOW	1
#  define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#  define CONFIG_PCI_MEM_BUS	0x40000000
#  define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#  define CONFIG_PCI_MEM_SIZE	0x10000000

#  define CONFIG_PCI_IO_BUS	0x50000000
#  define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#  define CONFIG_PCI_IO_SIZE	0x01000000

#endif

/* USB */
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)

#  define CONFIG_USB_OHCI
#  define CONFIG_USB_CLOCK	0x0001bbbb
#  if defined (CONFIG_EVAL5200)
#    define CONFIG_USB_CONFIG	0x00005100
#  else
#    define CONFIG_USB_CONFIG	0x00001000
#  endif
#  define CONFIG_DOS_PARTITION
#  define CONFIG_USB_STORAGE

#endif

/* IDE */
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
#  define CONFIG_DOS_PARTITION
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_REGINFO

#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_USB
#define CONFIG_CMD_PCI
#endif


/*
 * MUST be low boot - HIGHBOOT is not supported anymore
 */
#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
#   define CONFIG_SYS_LOWBOOT		1
#   define CONFIG_SYS_LOWBOOT16	1
#else
#   error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
/*
 * EEPROM configuration
 */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_SIZE 0x2000

#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */

#if defined(CONFIG_SYS_I2C_SOFT)
#  define CONFIG_SYS_I2C
#  define CONFIG_SYS_I2C_SOFT_SPEED	100000
#  define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
/**/
#  define SDA0			0x40
#  define SCL0			0x80
#  define GPIOE0		*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
#  define DDR0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
#  define DVO0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
#  define DVI0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
#  define ODE0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
#  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
#  define I2C_READ		((DVI0&SDA0)?1:0)
#  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
#  define I2C_SCL(x)	{if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
#  define I2C_DELAY		{udelay(5);}
#  define I2C_ACTIVE	{DDR0|=SDA0;}
#  define I2C_TRISTATE	{DDR0&=~SDA0;}

#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_FACT_ADDR	0x57
#endif

#if defined (CONFIG_HARD_I2C)
#  define CONFIG_SYS_I2C_MODULE	2		/* Select I2C module #1 or #2 */
#  define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
#  define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_FACT_ADDR	0x54
#endif

/*
 * Flash configuration, expect one 16 Megabyte Bank at most
 */
#define CONFIG_SYS_FLASH_BASE		0xff000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0)

#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */

/*
 * DRAM configuration - will be read from VPD later... TODO!
 */
#if 0
/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
#define	CONFIG_SYS_DRAM_DDR		0
#define CONFIG_SYS_DRAM_EMODE		0
#define CONFIG_SYS_DRAM_MODE		0x008D
#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
#define CONFIG_SYS_DRAM_CONFIG1	0xC2233A00
#define CONFIG_SYS_DRAM_CONFIG2	0x88B70004
#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
#endif
#if 1
/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
#define	CONFIG_SYS_DRAM_DDR		0
#define CONFIG_SYS_DRAM_EMODE		0
#define CONFIG_SYS_DRAM_MODE		0x00CD
#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
#define CONFIG_SYS_DRAM_CONFIG1	0xD2333A00
#define CONFIG_SYS_DRAM_CONFIG2	0x8AD70004
#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
#endif

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
#define CONFIG_ENV_OFFSET		0x1000
#define CONFIG_ENV_SIZE		0x0700

/*
 * VPD settings
 */
#define CONFIG_SYS_FACT_OFFSET		0x1800
#define CONFIG_SYS_FACT_SIZE		0x0800

/*
 * Memory map
 *
 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
 */
#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII10	/* Workaround for FEC 100Mbit problem */
#define	CONFIG_PHY_ADDR		0x1f
#define	CONFIG_PHY_TYPE		0x79c874
/*
 * GPIO configuration:
 * PSC1,2,3 predefined as UART
 * PCI disabled
 * Ethernet 100 with MD
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif


#ifdef CONFIG_EVAL5200		/* M48T08 is available with the Evaluation board only */
  #define CONFIG_RTC_MK48T59	1	/* use M48T08 on EVAL5200 */
  #define RTC(reg)		(0xf0010000+reg)
  /* setup CS2 for M48T08. Must MAP 64kB */
  #define CONFIG_SYS_CS2_START	RTC(0)
  #define CONFIG_SYS_CS2_SIZE	0x10000
  /* setup CS2 configuration register: */
  /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
  /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
  #define CONFIG_SYS_CS2_CFG	0x00047800
#else
  #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0x7f000000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define CONFIG_IDE_RESET	1
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005c)

/* Interval between registers                                                */
#define CONFIG_SYS_ATA_STRIDE          4

#endif /* __CONFIG_H */
Commit	Line	Data
c1896004 WD	1	/*
c1896004 WD	2	* (C) Copyright 2003
d4ca31c4 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
	6	*
	7	* TOP5200 differences from IceCube:
	8	* 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
	9	* bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
	10	* 1 SDRAM/DDRAM Bank up to 256 MB
	11	* local VPD I2C Bus is software driven and uses
	12	* GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
	13	* FLASH is re-located at 0xff000000
	14	* Internal regs are at 0xf0000000
c1896004 WD	15	* Reset jumps to 0x00000100
c1896004 WD	16	*
3765b3e7	17	* SPDX-License-Identifier: GPL-2.0+
c1896004 WD	18	*/
	19
	20	#ifndef __CONFIG_H
	21	#define __CONFIG_H
	22
	23	/*
	24	* High Level Configuration Options
	25	* (easy to change)
	26	*/
	27
cbd8a35c	28	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
c1896004 WD	29	#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
	30	#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
	31
2ae18241 WD	32	/*
	33	* allowed and functional CONFIG_SYS_TEXT_BASE values:
	34	* 0xff000000 low boot at 0x00000100 (default board setting)
	35	* 0xfff00000 high boot at 0xfff00100 (board needs modification)
	36	* 0x00100000 RAM load and test
	37	*/
	38	#define CONFIG_SYS_TEXT_BASE 0xff000000
	39
6d0f6bcf	40	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
c1896004	41
31d82672 BB	42	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	43
c1896004 WD	44	/*
	45	* Serial console configuration
	46	*/
	47	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	48	#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
6d0f6bcf	49	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
c1896004 WD	50
c1896004 WD	51
4d13cbad	52	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
c1896004 WD	53	/*
	54	* PCI Mapping:
	55	* 0x40000000 - 0x4fffffff - PCI Memory
	56	* 0x50000000 - 0x50ffffff - PCI IO Space
	57	*/
	58	# define CONFIG_PCI 1
	59	# define CONFIG_PCI_PNP 1
	60	# define CONFIG_PCI_SCAN_SHOW 1
f33fca22	61	# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
c1896004 WD	62
	63	# define CONFIG_PCI_MEM_BUS 0x40000000
	64	# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	65	# define CONFIG_PCI_MEM_SIZE 0x10000000
	66
	67	# define CONFIG_PCI_IO_BUS 0x50000000
	68	# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	69	# define CONFIG_PCI_IO_SIZE 0x01000000
	70
c1896004 WD	71	#endif
c1896004 WD	72
4d13cbad WD	73	/* USB */
	74	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
	75
	76	# define CONFIG_USB_OHCI
	77	# define CONFIG_USB_CLOCK 0x0001bbbb
498b8db7 WD	78	# if defined (CONFIG_EVAL5200)
	79	# define CONFIG_USB_CONFIG 0x00005100
	80	# else
	81	# define CONFIG_USB_CONFIG 0x00001000
	82	# endif
4d13cbad WD	83	# define CONFIG_DOS_PARTITION
	84	# define CONFIG_USB_STORAGE
	85
4d13cbad WD	86	#endif
	87
	88	/* IDE */
	89	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
4d13cbad	90	# define CONFIG_DOS_PARTITION
d794cfef	91	#endif
4d13cbad	92
4d13cbad	93
a1aa0bb5 JL	94	/*
	95	* BOOTP options
	96	*/
	97	#define CONFIG_BOOTP_BOOTFILESIZE
	98	#define CONFIG_BOOTP_BOOTPATH
	99	#define CONFIG_BOOTP_GATEWAY
	100	#define CONFIG_BOOTP_HOSTNAME
	101
	102
d794cfef JL	103	/*
	104	* Command line configuration.
	105	*/
	106	#include <config_cmd_default.h>
	107
	108	#define CONFIG_CMD_ASKENV
	109	#define CONFIG_CMD_BEDBUG
	110	#define CONFIG_CMD_DATE
	111	#define CONFIG_CMD_DHCP
	112	#define CONFIG_CMD_EEPROM
	113	#define CONFIG_CMD_ELF
	114	#define CONFIG_CMD_I2C
	115	#define CONFIG_CMD_IMMAP
	116	#define CONFIG_CMD_MII
	117	#define CONFIG_CMD_REGINFO
4d13cbad	118
d794cfef JL	119	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
	120	#define CONFIG_CMD_FAT
	121	#define CONFIG_CMD_IDE
	122	#define CONFIG_CMD_USB
	123	#define CONFIG_CMD_PCI
4d13cbad WD	124	#endif
4d13cbad WD	125
c1896004	126
d4ca31c4	127	/*
4d13cbad	128	* MUST be low boot - HIGHBOOT is not supported anymore
d4ca31c4	129	*/
14d0a02a	130	#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
6d0f6bcf JCPV	131	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	132	# define CONFIG_SYS_LOWBOOT16 1
4d13cbad	133	#else
14d0a02a	134	# error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
d4ca31c4 WD	135	#endif
d4ca31c4 WD	136
c1896004 WD	137	/*
	138	* Autobooting
	139	*/
	140	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
d4ca31c4 WD	141
d4ca31c4 WD	142	#define CONFIG_PREBOOT "echo;" \
32bf3d14	143	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
d4ca31c4 WD	144	"echo"
	145
	146	#undef CONFIG_BOOTARGS
	147
	148	#define CONFIG_EXTRA_ENV_SETTINGS \
	149	"netdev=eth0\0" \
	150	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	151	"nfsroot=${serverip}:${rootpath}\0" \
d4ca31c4	152	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	153	"addip=setenv bootargs ${bootargs} " \
	154	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	155	":${hostname}:${netdev}:off panic=1\0" \
d4ca31c4	156	"flash_nfs=run nfsargs addip;" \
fe126d8b	157	"bootm ${kernel_addr}\0" \
d4ca31c4	158	"flash_self=run ramargs addip;" \
fe126d8b WD	159	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	160	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
d4ca31c4 WD	161	"rootpath=/opt/eldk/ppc_82xx\0" \
	162	"bootfile=/tftpboot/MPC5200/uImage\0" \
	163	""
	164
	165	#define CONFIG_BOOTCOMMAND "run flash_self"
c1896004 WD	166
	167	/*
	168	* IPB Bus clocking configuration.
	169	*/
6d0f6bcf	170	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
d4ca31c4	171
c1896004 WD	172	/*
	173	* I2C configuration
	174	*/
	175	/*
	176	* EEPROM configuration
	177	*/
6d0f6bcf JCPV	178	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
6d0f6bcf JCPV	179	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
c1896004	180
6d0f6bcf JCPV	181	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
6d0f6bcf JCPV	182	#define CONFIG_SYS_EEPROM_SIZE 0x2000
d4ca31c4	183
c1896004 WD	184	#define CONFIG_ENV_OVERWRITE
c1896004 WD	185	#define CONFIG_MISC_INIT_R
d4ca31c4	186
ea818dbb	187	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
d4ca31c4	188
ea818dbb HS	189	#if defined(CONFIG_SYS_I2C_SOFT)
	190	# define CONFIG_SYS_I2C
	191	# define CONFIG_SYS_I2C_SOFT_SPEED 100000
	192	# define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
	193	/**/
c1896004 WD	194	# define SDA0 0x40
c1896004 WD	195	# define SCL0 0x80
6d0f6bcf JCPV	196	# define GPIOE0 ((volatile uchar)(CONFIG_SYS_MBAR+0x0c00))
	197	# define DDR0 ((volatile uchar)(CONFIG_SYS_MBAR+0x0c08))
	198	# define DVO0 ((volatile uchar)(CONFIG_SYS_MBAR+0x0c0c))
	199	# define DVI0 ((volatile uchar)(CONFIG_SYS_MBAR+0x0c20))
	200	# define ODE0 ((volatile uchar)(CONFIG_SYS_MBAR+0x0c04))
c1896004 WD	201	# define I2C_INIT {GPIOE0\|=(SDA0\|SCL0);ODE0\|=(SDA0\|SCL0);DVO0\|=(SDA0\|SCL0);DDR0\|=(SDA0\|SCL0);}
	202	# define I2C_READ ((DVI0&SDA0)?1:0)
	203	# define I2C_SDA(x) {if(x)DVO0\|=SDA0;else DVO0&=~SDA0;}
	204	# define I2C_SCL(x) {if(x)DVO0\|=SCL0;else DVO0&=~SCL0;}
	205	# define I2C_DELAY {udelay(5);}
	206	# define I2C_ACTIVE {DDR0\|=SDA0;}
	207	# define I2C_TRISTATE {DDR0&=~SDA0;}
ea818dbb	208
6d0f6bcf JCPV	209	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
6d0f6bcf JCPV	210	#define CONFIG_SYS_I2C_FACT_ADDR 0x57
c1896004	211	#endif
d4ca31c4 WD	212
d4ca31c4 WD	213	#if defined (CONFIG_HARD_I2C)
6d0f6bcf JCPV	214	# define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	215	# define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
	216	# define CONFIG_SYS_I2C_SLAVE 0x7F
	217	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
	218	#define CONFIG_SYS_I2C_FACT_ADDR 0x54
d4ca31c4	219	#endif
c1896004 WD	220
	221	/*
	222	* Flash configuration, expect one 16 Megabyte Bank at most
	223	*/
6d0f6bcf JCPV	224	#define CONFIG_SYS_FLASH_BASE 0xff000000
	225	#define CONFIG_SYS_FLASH_SIZE 0x01000000
	226	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	227	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0)
c1896004	228
6d0f6bcf	229	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
c1896004	230
6d0f6bcf JCPV	231	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	232	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
c1896004 WD	233
	234	#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
	235
d4ca31c4 WD	236	/*
	237	* DRAM configuration - will be read from VPD later... TODO!
	238	*/
	239	#if 0
	240	/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
6d0f6bcf JCPV	241	#define CONFIG_SYS_DRAM_DDR 0
	242	#define CONFIG_SYS_DRAM_EMODE 0
	243	#define CONFIG_SYS_DRAM_MODE 0x008D
	244	#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
	245	#define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00
	246	#define CONFIG_SYS_DRAM_CONFIG2 0x88B70004
	247	#define CONFIG_SYS_DRAM_TAP_DEL 0x08
	248	#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
d4ca31c4 WD	249	#endif
	250	#if 1
	251	/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
6d0f6bcf JCPV	252	#define CONFIG_SYS_DRAM_DDR 0
	253	#define CONFIG_SYS_DRAM_EMODE 0
	254	#define CONFIG_SYS_DRAM_MODE 0x00CD
	255	#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
	256	#define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00
	257	#define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004
	258	#define CONFIG_SYS_DRAM_TAP_DEL 0x08
	259	#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
d4ca31c4 WD	260	#endif
d4ca31c4 WD	261
c1896004 WD	262	/*
	263	* Environment settings
	264	*/
bb1f8b4f	265	#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
0e8d1586 JCPV	266	#define CONFIG_ENV_OFFSET 0x1000
0e8d1586 JCPV	267	#define CONFIG_ENV_SIZE 0x0700
c1896004	268
d4ca31c4 WD	269	/*
	270	* VPD settings
	271	*/
6d0f6bcf JCPV	272	#define CONFIG_SYS_FACT_OFFSET 0x1800
6d0f6bcf JCPV	273	#define CONFIG_SYS_FACT_SIZE 0x0800
d4ca31c4	274
c1896004	275	/*
d4ca31c4 WD	276	* Memory map
	277	*
	278	* Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
c1896004	279	*/
6d0f6bcf JCPV	280	#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
	281	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	282	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
c1896004 WD	283
c1896004 WD	284	/* Use SRAM until RAM will be available */
6d0f6bcf	285	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	286	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
c1896004 WD	287
c1896004 WD	288
25ddd1fb	289	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	290	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c1896004	291
14d0a02a	292	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	293	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	294	# define CONFIG_SYS_RAMBOOT 1
c1896004 WD	295	#endif
c1896004 WD	296
6d0f6bcf JCPV	297	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	298	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	299	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c1896004 WD	300
	301	/*
	302	* Ethernet configuration
	303	*/
cbd8a35c	304	#define CONFIG_MPC5xxx_FEC 1
86321fc1	305	#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */
d4ca31c4	306	#define CONFIG_PHY_ADDR 0x1f
c1896004 WD	307	#define CONFIG_PHY_TYPE 0x79c874
c1896004 WD	308	/*
d4ca31c4 WD	309	* GPIO configuration:
	310	* PSC1,2,3 predefined as UART
	311	* PCI disabled
c1896004 WD	312	* Ethernet 100 with MD
c1896004 WD	313	*/
6d0f6bcf	314	#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044
c1896004 WD	315
	316	/*
	317	* Miscellaneous configurable options
	318	*/
6d0f6bcf	319	#define CONFIG_SYS_LONGHELP /* undef to save memory */
d794cfef	320	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	321	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c1896004	322	#else
6d0f6bcf	323	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c1896004	324	#endif
6d0f6bcf JCPV	325	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	326	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	327	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c1896004	328
6d0f6bcf JCPV	329	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	330	#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
c1896004	331
6d0f6bcf	332	#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
c1896004	333
6d0f6bcf	334	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
d794cfef	335	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	336	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
d794cfef JL	337	#endif
	338
	339
63e73c9a WD	340	#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
	341	#define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
	342	#define RTC(reg) (0xf0010000+reg)
	343	/* setup CS2 for M48T08. Must MAP 64kB */
6d0f6bcf JCPV	344	#define CONFIG_SYS_CS2_START RTC(0)
6d0f6bcf JCPV	345	#define CONFIG_SYS_CS2_SIZE 0x10000
63e73c9a WD	346	/* setup CS2 configuration register: */
	347	/* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
	348	/* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
6d0f6bcf	349	#define CONFIG_SYS_CS2_CFG 0x00047800
63e73c9a WD	350	#else
	351	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
	352	#endif
1c43771b	353
c1896004 WD	354	/*
	355	* Various low-level settings
	356	*/
6d0f6bcf JCPV	357	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	358	#define CONFIG_SYS_HID0_FINAL HID0_ICE
c1896004	359
6d0f6bcf JCPV	360	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	361	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	362	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	363	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	364	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
c1896004	365
6d0f6bcf JCPV	366	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	367	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
c1896004	368
6d0f6bcf	369	#define CONFIG_SYS_RESET_ADDRESS 0x7f000000
c1896004	370
4d13cbad WD	371	/*-----------------------------------------------------------------------
	372	* IDE/ATA stuff Supports IDE harddisk
	373	*-----------------------------------------------------------------------
	374	*/
	375
	376	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	377
	378	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	379	#undef CONFIG_IDE_LED /* LED for ide not supported */
	380
	381	#define CONFIG_IDE_RESET 1
	382	#define CONFIG_IDE_PREINIT
	383
6d0f6bcf JCPV	384	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	385	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
4d13cbad	386
6d0f6bcf	387	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
4d13cbad	388
6d0f6bcf	389	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
4d13cbad WD	390
4d13cbad WD	391	/* Offset for data I/O */
6d0f6bcf	392	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
4d13cbad WD	393
4d13cbad WD	394	/* Offset for normal register accesses */
6d0f6bcf	395	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
4d13cbad WD	396
4d13cbad WD	397	/* Offset for alternate registers */
6d0f6bcf	398	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005c)
4d13cbad WD	399
4d13cbad WD	400	/* Interval between registers */
6d0f6bcf	401	#define CONFIG_SYS_ATA_STRIDE 4
4d13cbad	402
c1896004	403	#endif /* __CONFIG_H */