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Commit | Line | Data |
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c1896004 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
d4ca31c4 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de | |
6 | * | |
7 | * TOP5200 differences from IceCube: | |
8 | * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks | |
9 | * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins | |
10 | * 1 SDRAM/DDRAM Bank up to 256 MB | |
11 | * local VPD I2C Bus is software driven and uses | |
12 | * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL | |
13 | * FLASH is re-located at 0xff000000 | |
14 | * Internal regs are at 0xf0000000 | |
c1896004 WD |
15 | * Reset jumps to 0x00000100 |
16 | * | |
3765b3e7 | 17 | * SPDX-License-Identifier: GPL-2.0+ |
c1896004 WD |
18 | */ |
19 | ||
20 | #ifndef __CONFIG_H | |
21 | #define __CONFIG_H | |
22 | ||
23 | /* | |
24 | * High Level Configuration Options | |
25 | * (easy to change) | |
26 | */ | |
27 | ||
b2a6dfe4 | 28 | #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ |
c1896004 WD |
29 | #define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */ |
30 | ||
2ae18241 WD |
31 | /* |
32 | * allowed and functional CONFIG_SYS_TEXT_BASE values: | |
33 | * 0xff000000 low boot at 0x00000100 (default board setting) | |
34 | * 0xfff00000 high boot at 0xfff00100 (board needs modification) | |
35 | * 0x00100000 RAM load and test | |
36 | */ | |
37 | #define CONFIG_SYS_TEXT_BASE 0xff000000 | |
38 | ||
6d0f6bcf | 39 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
c1896004 | 40 | |
31d82672 BB |
41 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
42 | ||
c1896004 WD |
43 | /* |
44 | * Serial console configuration | |
45 | */ | |
46 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
47 | #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ | |
6d0f6bcf | 48 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
c1896004 WD |
49 | |
50 | ||
4d13cbad | 51 | #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) |
c1896004 WD |
52 | /* |
53 | * PCI Mapping: | |
54 | * 0x40000000 - 0x4fffffff - PCI Memory | |
55 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
56 | */ | |
57 | # define CONFIG_PCI 1 | |
58 | # define CONFIG_PCI_PNP 1 | |
59 | # define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 60 | # define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
c1896004 WD |
61 | |
62 | # define CONFIG_PCI_MEM_BUS 0x40000000 | |
63 | # define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
64 | # define CONFIG_PCI_MEM_SIZE 0x10000000 | |
65 | ||
66 | # define CONFIG_PCI_IO_BUS 0x50000000 | |
67 | # define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
68 | # define CONFIG_PCI_IO_SIZE 0x01000000 | |
69 | ||
c1896004 WD |
70 | #endif |
71 | ||
4d13cbad WD |
72 | /* USB */ |
73 | #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) | |
74 | ||
75 | # define CONFIG_USB_OHCI | |
76 | # define CONFIG_USB_CLOCK 0x0001bbbb | |
498b8db7 WD |
77 | # if defined (CONFIG_EVAL5200) |
78 | # define CONFIG_USB_CONFIG 0x00005100 | |
79 | # else | |
80 | # define CONFIG_USB_CONFIG 0x00001000 | |
81 | # endif | |
4d13cbad WD |
82 | # define CONFIG_DOS_PARTITION |
83 | # define CONFIG_USB_STORAGE | |
84 | ||
4d13cbad WD |
85 | #endif |
86 | ||
87 | /* IDE */ | |
88 | #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) | |
4d13cbad | 89 | # define CONFIG_DOS_PARTITION |
d794cfef | 90 | #endif |
4d13cbad | 91 | |
4d13cbad | 92 | |
a1aa0bb5 JL |
93 | /* |
94 | * BOOTP options | |
95 | */ | |
96 | #define CONFIG_BOOTP_BOOTFILESIZE | |
97 | #define CONFIG_BOOTP_BOOTPATH | |
98 | #define CONFIG_BOOTP_GATEWAY | |
99 | #define CONFIG_BOOTP_HOSTNAME | |
100 | ||
101 | ||
d794cfef JL |
102 | /* |
103 | * Command line configuration. | |
104 | */ | |
105 | #include <config_cmd_default.h> | |
106 | ||
107 | #define CONFIG_CMD_ASKENV | |
108 | #define CONFIG_CMD_BEDBUG | |
109 | #define CONFIG_CMD_DATE | |
110 | #define CONFIG_CMD_DHCP | |
111 | #define CONFIG_CMD_EEPROM | |
112 | #define CONFIG_CMD_ELF | |
113 | #define CONFIG_CMD_I2C | |
114 | #define CONFIG_CMD_IMMAP | |
115 | #define CONFIG_CMD_MII | |
116 | #define CONFIG_CMD_REGINFO | |
4d13cbad | 117 | |
d794cfef JL |
118 | #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) |
119 | #define CONFIG_CMD_FAT | |
120 | #define CONFIG_CMD_IDE | |
121 | #define CONFIG_CMD_USB | |
122 | #define CONFIG_CMD_PCI | |
4d13cbad WD |
123 | #endif |
124 | ||
c1896004 | 125 | |
d4ca31c4 | 126 | /* |
4d13cbad | 127 | * MUST be low boot - HIGHBOOT is not supported anymore |
d4ca31c4 | 128 | */ |
14d0a02a | 129 | #if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ |
6d0f6bcf JCPV |
130 | # define CONFIG_SYS_LOWBOOT 1 |
131 | # define CONFIG_SYS_LOWBOOT16 1 | |
4d13cbad | 132 | #else |
14d0a02a | 133 | # error "CONFIG_SYS_TEXT_BASE must be 0xff000000" |
d4ca31c4 WD |
134 | #endif |
135 | ||
c1896004 WD |
136 | /* |
137 | * Autobooting | |
138 | */ | |
139 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
d4ca31c4 WD |
140 | |
141 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 142 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
d4ca31c4 WD |
143 | "echo" |
144 | ||
145 | #undef CONFIG_BOOTARGS | |
146 | ||
147 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
148 | "netdev=eth0\0" \ | |
149 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 150 | "nfsroot=${serverip}:${rootpath}\0" \ |
d4ca31c4 | 151 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
152 | "addip=setenv bootargs ${bootargs} " \ |
153 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
154 | ":${hostname}:${netdev}:off panic=1\0" \ | |
d4ca31c4 | 155 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 156 | "bootm ${kernel_addr}\0" \ |
d4ca31c4 | 157 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
158 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
159 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
d4ca31c4 WD |
160 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
161 | "bootfile=/tftpboot/MPC5200/uImage\0" \ | |
162 | "" | |
163 | ||
164 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
c1896004 WD |
165 | |
166 | /* | |
167 | * IPB Bus clocking configuration. | |
168 | */ | |
6d0f6bcf | 169 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
d4ca31c4 | 170 | |
c1896004 WD |
171 | /* |
172 | * I2C configuration | |
173 | */ | |
174 | /* | |
175 | * EEPROM configuration | |
176 | */ | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
178 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
c1896004 | 179 | |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
181 | #define CONFIG_SYS_EEPROM_SIZE 0x2000 | |
d4ca31c4 | 182 | |
c1896004 WD |
183 | #define CONFIG_ENV_OVERWRITE |
184 | #define CONFIG_MISC_INIT_R | |
d4ca31c4 | 185 | |
ea818dbb | 186 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
d4ca31c4 | 187 | |
ea818dbb HS |
188 | #if defined(CONFIG_SYS_I2C_SOFT) |
189 | # define CONFIG_SYS_I2C | |
190 | # define CONFIG_SYS_I2C_SOFT_SPEED 100000 | |
191 | # define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F | |
192 | /**/ | |
c1896004 WD |
193 | # define SDA0 0x40 |
194 | # define SCL0 0x80 | |
6d0f6bcf JCPV |
195 | # define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00)) |
196 | # define DDR0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08)) | |
197 | # define DVO0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c)) | |
198 | # define DVI0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20)) | |
199 | # define ODE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04)) | |
c1896004 WD |
200 | # define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);} |
201 | # define I2C_READ ((DVI0&SDA0)?1:0) | |
202 | # define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;} | |
203 | # define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;} | |
204 | # define I2C_DELAY {udelay(5);} | |
205 | # define I2C_ACTIVE {DDR0|=SDA0;} | |
206 | # define I2C_TRISTATE {DDR0&=~SDA0;} | |
ea818dbb | 207 | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
209 | #define CONFIG_SYS_I2C_FACT_ADDR 0x57 | |
c1896004 | 210 | #endif |
d4ca31c4 WD |
211 | |
212 | #if defined (CONFIG_HARD_I2C) | |
6d0f6bcf JCPV |
213 | # define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
214 | # define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ | |
215 | # define CONFIG_SYS_I2C_SLAVE 0x7F | |
216 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 | |
217 | #define CONFIG_SYS_I2C_FACT_ADDR 0x54 | |
d4ca31c4 | 218 | #endif |
c1896004 WD |
219 | |
220 | /* | |
221 | * Flash configuration, expect one 16 Megabyte Bank at most | |
222 | */ | |
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_FLASH_BASE 0xff000000 |
224 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
225 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
226 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0) | |
c1896004 | 227 | |
6d0f6bcf | 228 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ |
c1896004 | 229 | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
231 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
c1896004 WD |
232 | |
233 | #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ | |
234 | ||
d4ca31c4 WD |
235 | /* |
236 | * DRAM configuration - will be read from VPD later... TODO! | |
237 | */ | |
238 | #if 0 | |
239 | /* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */ | |
6d0f6bcf JCPV |
240 | #define CONFIG_SYS_DRAM_DDR 0 |
241 | #define CONFIG_SYS_DRAM_EMODE 0 | |
242 | #define CONFIG_SYS_DRAM_MODE 0x008D | |
243 | #define CONFIG_SYS_DRAM_CONTROL 0x514F0000 | |
244 | #define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00 | |
245 | #define CONFIG_SYS_DRAM_CONFIG2 0x88B70004 | |
246 | #define CONFIG_SYS_DRAM_TAP_DEL 0x08 | |
247 | #define CONFIG_SYS_DRAM_RAM_SIZE 0x19 | |
d4ca31c4 WD |
248 | #endif |
249 | #if 1 | |
250 | /* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */ | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_DRAM_DDR 0 |
252 | #define CONFIG_SYS_DRAM_EMODE 0 | |
253 | #define CONFIG_SYS_DRAM_MODE 0x00CD | |
254 | #define CONFIG_SYS_DRAM_CONTROL 0x514F0000 | |
255 | #define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00 | |
256 | #define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004 | |
257 | #define CONFIG_SYS_DRAM_TAP_DEL 0x08 | |
258 | #define CONFIG_SYS_DRAM_RAM_SIZE 0x19 | |
d4ca31c4 WD |
259 | #endif |
260 | ||
c1896004 WD |
261 | /* |
262 | * Environment settings | |
263 | */ | |
bb1f8b4f | 264 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ |
0e8d1586 JCPV |
265 | #define CONFIG_ENV_OFFSET 0x1000 |
266 | #define CONFIG_ENV_SIZE 0x0700 | |
c1896004 | 267 | |
d4ca31c4 WD |
268 | /* |
269 | * VPD settings | |
270 | */ | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_FACT_OFFSET 0x1800 |
272 | #define CONFIG_SYS_FACT_SIZE 0x0800 | |
d4ca31c4 | 273 | |
c1896004 | 274 | /* |
d4ca31c4 WD |
275 | * Memory map |
276 | * | |
277 | * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 | |
c1896004 | 278 | */ |
6d0f6bcf JCPV |
279 | #define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */ |
280 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
281 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
c1896004 WD |
282 | |
283 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 284 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 285 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
c1896004 WD |
286 | |
287 | ||
25ddd1fb | 288 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 289 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c1896004 | 290 | |
14d0a02a | 291 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
292 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
293 | # define CONFIG_SYS_RAMBOOT 1 | |
c1896004 WD |
294 | #endif |
295 | ||
6d0f6bcf JCPV |
296 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
297 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
298 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
c1896004 WD |
299 | |
300 | /* | |
301 | * Ethernet configuration | |
302 | */ | |
cbd8a35c | 303 | #define CONFIG_MPC5xxx_FEC 1 |
86321fc1 | 304 | #define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */ |
d4ca31c4 | 305 | #define CONFIG_PHY_ADDR 0x1f |
c1896004 WD |
306 | #define CONFIG_PHY_TYPE 0x79c874 |
307 | /* | |
d4ca31c4 WD |
308 | * GPIO configuration: |
309 | * PSC1,2,3 predefined as UART | |
310 | * PCI disabled | |
c1896004 WD |
311 | * Ethernet 100 with MD |
312 | */ | |
6d0f6bcf | 313 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 |
c1896004 WD |
314 | |
315 | /* | |
316 | * Miscellaneous configurable options | |
317 | */ | |
6d0f6bcf | 318 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
d794cfef | 319 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 320 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
c1896004 | 321 | #else |
6d0f6bcf | 322 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c1896004 | 323 | #endif |
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
325 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
326 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
c1896004 | 327 | |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
329 | #define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ | |
c1896004 | 330 | |
6d0f6bcf | 331 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
c1896004 | 332 | |
6d0f6bcf | 333 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
d794cfef | 334 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 335 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
d794cfef JL |
336 | #endif |
337 | ||
338 | ||
63e73c9a WD |
339 | #ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */ |
340 | #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */ | |
341 | #define RTC(reg) (0xf0010000+reg) | |
342 | /* setup CS2 for M48T08. Must MAP 64kB */ | |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_CS2_START RTC(0) |
344 | #define CONFIG_SYS_CS2_SIZE 0x10000 | |
63e73c9a WD |
345 | /* setup CS2 configuration register: */ |
346 | /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */ | |
347 | /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */ | |
6d0f6bcf | 348 | #define CONFIG_SYS_CS2_CFG 0x00047800 |
63e73c9a WD |
349 | #else |
350 | #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
351 | #endif | |
1c43771b | 352 | |
c1896004 WD |
353 | /* |
354 | * Various low-level settings | |
355 | */ | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
357 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
c1896004 | 358 | |
6d0f6bcf JCPV |
359 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
360 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
361 | #define CONFIG_SYS_BOOTCS_CFG 0x00047801 | |
362 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
363 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
c1896004 | 364 | |
6d0f6bcf JCPV |
365 | #define CONFIG_SYS_CS_BURST 0x00000000 |
366 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
c1896004 | 367 | |
6d0f6bcf | 368 | #define CONFIG_SYS_RESET_ADDRESS 0x7f000000 |
c1896004 | 369 | |
4d13cbad WD |
370 | /*----------------------------------------------------------------------- |
371 | * IDE/ATA stuff Supports IDE harddisk | |
372 | *----------------------------------------------------------------------- | |
373 | */ | |
374 | ||
375 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
376 | ||
377 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
378 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
379 | ||
380 | #define CONFIG_IDE_RESET 1 | |
381 | #define CONFIG_IDE_PREINIT | |
382 | ||
6d0f6bcf JCPV |
383 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
384 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
4d13cbad | 385 | |
6d0f6bcf | 386 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
4d13cbad | 387 | |
6d0f6bcf | 388 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
4d13cbad WD |
389 | |
390 | /* Offset for data I/O */ | |
6d0f6bcf | 391 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
4d13cbad WD |
392 | |
393 | /* Offset for normal register accesses */ | |
6d0f6bcf | 394 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
4d13cbad WD |
395 | |
396 | /* Offset for alternate registers */ | |
6d0f6bcf | 397 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005c) |
4d13cbad WD |
398 | |
399 | /* Interval between registers */ | |
6d0f6bcf | 400 | #define CONFIG_SYS_ATA_STRIDE 4 |
4d13cbad | 401 | |
c1896004 | 402 | #endif /* __CONFIG_H */ |