[people/ms/u-boot.git] / include / configs / TOP5200.h

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
 *
 * TOP5200 differences from IceCube:
 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
 *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
 * 1 SDRAM/DDRAM Bank up to 256 MB
 * local VPD I2C Bus is software driven and uses
 *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
 * FLASH is re-located at 0xff000000
 * Internal regs are at 0xf0000000
 * Reset jumps to 0x00000100
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
#define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#  define CONFIG_PCI		1
#  define CONFIG_PCI_PNP		1
#  define CONFIG_PCI_SCAN_SHOW	1
#  define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#  define CONFIG_PCI_MEM_BUS	0x40000000
#  define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#  define CONFIG_PCI_MEM_SIZE	0x10000000

#  define CONFIG_PCI_IO_BUS	0x50000000
#  define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#  define CONFIG_PCI_IO_SIZE	0x01000000

#endif

/* USB */
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)

#  define CONFIG_USB_OHCI
#  define CONFIG_USB_CLOCK	0x0001bbbb
#  if defined (CONFIG_EVAL5200)
#    define CONFIG_USB_CONFIG	0x00005100
#  else
#    define CONFIG_USB_CONFIG	0x00001000
#  endif
#  define CONFIG_DOS_PARTITION
#  define CONFIG_USB_STORAGE

#endif

/* IDE */
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
#  define CONFIG_DOS_PARTITION
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_REGINFO

#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_USB
#define CONFIG_CMD_PCI
#endif


/*
 * MUST be low boot - HIGHBOOT is not supported anymore
 */
#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
#   define CFG_LOWBOOT		1
#   define CFG_LOWBOOT16	1
#else
#   error "TEXT_BASE must be 0xff000000"
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
/*
 * EEPROM configuration
 */
#define CFG_EEPROM_PAGE_WRITE_BITS	3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70

#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_SIZE 0x2000

#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R

#undef	CONFIG_HARD_I2C			/* I2C with hardware support */
#define	CONFIG_SOFT_I2C		1	/* I2C with softwate support */

#if defined (CONFIG_SOFT_I2C)
#  define SDA0			0x40
#  define SCL0			0x80
#  define GPIOE0		*((volatile uchar*)(CFG_MBAR+0x0c00))
#  define DDR0			*((volatile uchar*)(CFG_MBAR+0x0c08))
#  define DVO0			*((volatile uchar*)(CFG_MBAR+0x0c0c))
#  define DVI0			*((volatile uchar*)(CFG_MBAR+0x0c20))
#  define ODE0			*((volatile uchar*)(CFG_MBAR+0x0c04))
#  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
#  define I2C_READ		((DVI0&SDA0)?1:0)
#  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
#  define I2C_SCL(x)	{if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
#  define I2C_DELAY		{udelay(5);}
#  define I2C_ACTIVE	{DDR0|=SDA0;}
#  define I2C_TRISTATE	{DDR0&=~SDA0;}
#  define CFG_I2C_SPEED		100000
#  define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_FACT_ADDR	0x57
#endif

#if defined (CONFIG_HARD_I2C)
#  define CFG_I2C_MODULE	2		/* Select I2C module #1 or #2 */
#  define CFG_I2C_SPEED		100000	/* 100 kHz */
#  define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_EEPROM_ADDR 0x54
#define CFG_I2C_FACT_ADDR	0x54
#endif

/*
 * Flash configuration, expect one 16 Megabyte Bank at most
 */
#define CFG_FLASH_BASE		0xff000000
#define CFG_FLASH_SIZE		0x01000000
#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0)

#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */

/*
 * DRAM configuration - will be read from VPD later... TODO!
 */
#if 0
/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
#define	CFG_DRAM_DDR		0
#define CFG_DRAM_EMODE		0
#define CFG_DRAM_MODE		0x008D
#define CFG_DRAM_CONTROL	0x514F0000
#define CFG_DRAM_CONFIG1	0xC2233A00
#define CFG_DRAM_CONFIG2	0x88B70004
#define	CFG_DRAM_TAP_DEL	0x08
#define CFG_DRAM_RAM_SIZE	0x19
#endif
#if 1
/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
#define	CFG_DRAM_DDR		0
#define CFG_DRAM_EMODE		0
#define CFG_DRAM_MODE		0x00CD
#define CFG_DRAM_CONTROL	0x514F0000
#define CFG_DRAM_CONFIG1	0xD2333A00
#define CFG_DRAM_CONFIG2	0x8AD70004
#define	CFG_DRAM_TAP_DEL	0x08
#define CFG_DRAM_RAM_SIZE	0x19
#endif

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
#define CONFIG_ENV_OFFSET		0x1000
#define CONFIG_ENV_SIZE		0x0700

/*
 * VPD settings
 */
#define CFG_FACT_OFFSET		0x1800
#define CFG_FACT_SIZE		0x0800

/*
 * Memory map
 *
 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
 */
#define CFG_MBAR			0xf0000000	/* DO NOT CHANGE this */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_FEC_10MBIT	1		/* Workaround for FEC 100Mbit problem */
#define	CONFIG_PHY_ADDR		0x1f
#define	CONFIG_PHY_TYPE		0x79c874
/*
 * GPIO configuration:
 * PSC1,2,3 predefined as UART
 * PCI disabled
 * Ethernet 100 with MD
 */
#define CFG_GPS_PORT_CONFIG	0x00058044

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#  define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x200000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif


#ifdef CONFIG_EVAL5200		/* M48T08 is available with the Evaluation board only */
  #define CONFIG_RTC_MK48T59	1	/* use M48T08 on EVAL5200 */
  #define RTC(reg)		(0xf0010000+reg)
  /* setup CS2 for M48T08. Must MAP 64kB */
  #define CFG_CS2_START	RTC(0)
  #define CFG_CS2_SIZE	0x10000
  /* setup CS2 configuration register: */
  /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
  /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
  #define CFG_CS2_CFG	0x00047800
#else
  #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
#endif

/*
 * Various low-level settings
 */
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x00047801
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#define CFG_RESET_ADDRESS	0x7f000000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define CONFIG_IDE_RESET	1
#define CONFIG_IDE_PREINIT

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(0x005c)

/* Interval between registers                                                */
#define CFG_ATA_STRIDE          4

#endif /* __CONFIG_H */
Commit	Line	Data
c1896004 WD	1	/*
c1896004 WD	2	* (C) Copyright 2003
d4ca31c4 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
	6	*
	7	* TOP5200 differences from IceCube:
	8	* 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
	9	* bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
	10	* 1 SDRAM/DDRAM Bank up to 256 MB
	11	* local VPD I2C Bus is software driven and uses
	12	* GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
	13	* FLASH is re-located at 0xff000000
	14	* Internal regs are at 0xf0000000
c1896004 WD	15	* Reset jumps to 0x00000100
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
	43
cbd8a35c	44	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
c1896004 WD	45	#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
	46	#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
	47
d4ca31c4	48	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
c1896004 WD	49
	50	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	51	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	52
31d82672 BB	53	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	54
c1896004 WD	55	/*
	56	* Serial console configuration
	57	*/
	58	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	59	#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
	60	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	61
	62
4d13cbad	63	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
c1896004 WD	64	/*
	65	* PCI Mapping:
	66	* 0x40000000 - 0x4fffffff - PCI Memory
	67	* 0x50000000 - 0x50ffffff - PCI IO Space
	68	*/
	69	# define CONFIG_PCI 1
	70	# define CONFIG_PCI_PNP 1
	71	# define CONFIG_PCI_SCAN_SHOW 1
f33fca22	72	# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
c1896004 WD	73
	74	# define CONFIG_PCI_MEM_BUS 0x40000000
	75	# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	76	# define CONFIG_PCI_MEM_SIZE 0x10000000
	77
	78	# define CONFIG_PCI_IO_BUS 0x50000000
	79	# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	80	# define CONFIG_PCI_IO_SIZE 0x01000000
	81
c1896004 WD	82	#endif
c1896004 WD	83
4d13cbad WD	84	/* USB */
	85	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
	86
	87	# define CONFIG_USB_OHCI
	88	# define CONFIG_USB_CLOCK 0x0001bbbb
498b8db7 WD	89	# if defined (CONFIG_EVAL5200)
	90	# define CONFIG_USB_CONFIG 0x00005100
	91	# else
	92	# define CONFIG_USB_CONFIG 0x00001000
	93	# endif
4d13cbad WD	94	# define CONFIG_DOS_PARTITION
	95	# define CONFIG_USB_STORAGE
	96
4d13cbad WD	97	#endif
	98
	99	/* IDE */
	100	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
4d13cbad	101	# define CONFIG_DOS_PARTITION
d794cfef	102	#endif
4d13cbad	103
4d13cbad	104
a1aa0bb5 JL	105	/*
	106	* BOOTP options
	107	*/
	108	#define CONFIG_BOOTP_BOOTFILESIZE
	109	#define CONFIG_BOOTP_BOOTPATH
	110	#define CONFIG_BOOTP_GATEWAY
	111	#define CONFIG_BOOTP_HOSTNAME
	112
	113
d794cfef JL	114	/*
	115	* Command line configuration.
	116	*/
	117	#include <config_cmd_default.h>
	118
	119	#define CONFIG_CMD_ASKENV
	120	#define CONFIG_CMD_BEDBUG
	121	#define CONFIG_CMD_DATE
	122	#define CONFIG_CMD_DHCP
	123	#define CONFIG_CMD_EEPROM
	124	#define CONFIG_CMD_ELF
	125	#define CONFIG_CMD_I2C
	126	#define CONFIG_CMD_IMMAP
	127	#define CONFIG_CMD_MII
	128	#define CONFIG_CMD_REGINFO
4d13cbad	129
d794cfef JL	130	#if defined (CONFIG_EVAL5200) \|\| defined (CONFIG_LITE5200)
	131	#define CONFIG_CMD_FAT
	132	#define CONFIG_CMD_IDE
	133	#define CONFIG_CMD_USB
	134	#define CONFIG_CMD_PCI
4d13cbad WD	135	#endif
4d13cbad WD	136
c1896004	137
d4ca31c4	138	/*
4d13cbad	139	* MUST be low boot - HIGHBOOT is not supported anymore
d4ca31c4 WD	140	*/
	141	#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
	142	# define CFG_LOWBOOT 1
	143	# define CFG_LOWBOOT16 1
4d13cbad WD	144	#else
4d13cbad WD	145	# error "TEXT_BASE must be 0xff000000"
d4ca31c4 WD	146	#endif
d4ca31c4 WD	147
c1896004 WD	148	/*
	149	* Autobooting
	150	*/
	151	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
d4ca31c4 WD	152
d4ca31c4 WD	153	#define CONFIG_PREBOOT "echo;" \
32bf3d14	154	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
d4ca31c4 WD	155	"echo"
	156
	157	#undef CONFIG_BOOTARGS
	158
	159	#define CONFIG_EXTRA_ENV_SETTINGS \
	160	"netdev=eth0\0" \
	161	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	162	"nfsroot=${serverip}:${rootpath}\0" \
d4ca31c4	163	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	164	"addip=setenv bootargs ${bootargs} " \
	165	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	166	":${hostname}:${netdev}:off panic=1\0" \
d4ca31c4	167	"flash_nfs=run nfsargs addip;" \
fe126d8b	168	"bootm ${kernel_addr}\0" \
d4ca31c4	169	"flash_self=run ramargs addip;" \
fe126d8b WD	170	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	171	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
d4ca31c4 WD	172	"rootpath=/opt/eldk/ppc_82xx\0" \
	173	"bootfile=/tftpboot/MPC5200/uImage\0" \
	174	""
	175
	176	#define CONFIG_BOOTCOMMAND "run flash_self"
c1896004 WD	177
	178	/*
	179	* IPB Bus clocking configuration.
	180	*/
53677ef1	181	#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
d4ca31c4	182
c1896004 WD	183	/*
	184	* I2C configuration
	185	*/
	186	/*
	187	* EEPROM configuration
	188	*/
	189	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	190	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
	191
	192	#define CFG_I2C_EEPROM_ADDR_LEN 2
	193	#define CFG_EEPROM_SIZE 0x2000
d4ca31c4	194
c1896004 WD	195	#define CONFIG_ENV_OVERWRITE
c1896004 WD	196	#define CONFIG_MISC_INIT_R
d4ca31c4	197
c1896004	198	#undef CONFIG_HARD_I2C /* I2C with hardware support */
4d13cbad	199	#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */
d4ca31c4	200
c1896004 WD	201	#if defined (CONFIG_SOFT_I2C)
	202	# define SDA0 0x40
	203	# define SCL0 0x80
d4ca31c4 WD	204	# define GPIOE0 ((volatile uchar)(CFG_MBAR+0x0c00))
	205	# define DDR0 ((volatile uchar)(CFG_MBAR+0x0c08))
	206	# define DVO0 ((volatile uchar)(CFG_MBAR+0x0c0c))
	207	# define DVI0 ((volatile uchar)(CFG_MBAR+0x0c20))
	208	# define ODE0 ((volatile uchar)(CFG_MBAR+0x0c04))
c1896004 WD	209	# define I2C_INIT {GPIOE0\|=(SDA0\|SCL0);ODE0\|=(SDA0\|SCL0);DVO0\|=(SDA0\|SCL0);DDR0\|=(SDA0\|SCL0);}
	210	# define I2C_READ ((DVI0&SDA0)?1:0)
	211	# define I2C_SDA(x) {if(x)DVO0\|=SDA0;else DVO0&=~SDA0;}
	212	# define I2C_SCL(x) {if(x)DVO0\|=SCL0;else DVO0&=~SCL0;}
	213	# define I2C_DELAY {udelay(5);}
	214	# define I2C_ACTIVE {DDR0\|=SDA0;}
	215	# define I2C_TRISTATE {DDR0&=~SDA0;}
	216	# define CFG_I2C_SPEED 100000
	217	# define CFG_I2C_SLAVE 0x7F
4d13cbad WD	218	#define CFG_I2C_EEPROM_ADDR 0x57
4d13cbad WD	219	#define CFG_I2C_FACT_ADDR 0x57
c1896004	220	#endif
d4ca31c4 WD	221
d4ca31c4 WD	222	#if defined (CONFIG_HARD_I2C)
c1896004 WD	223	# define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	224	# define CFG_I2C_SPEED 100000 /* 100 kHz */
	225	# define CFG_I2C_SLAVE 0x7F
4d13cbad WD	226	#define CFG_I2C_EEPROM_ADDR 0x54
4d13cbad WD	227	#define CFG_I2C_FACT_ADDR 0x54
d4ca31c4	228	#endif
c1896004 WD	229
	230	/*
	231	* Flash configuration, expect one 16 Megabyte Bank at most
	232	*/
	233	#define CFG_FLASH_BASE 0xff000000
	234	#define CFG_FLASH_SIZE 0x01000000
	235	#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
0e8d1586	236	#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0)
c1896004 WD	237
	238	#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
	239
	240	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	241	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	242
	243	#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
	244
d4ca31c4 WD	245	/*
	246	* DRAM configuration - will be read from VPD later... TODO!
	247	*/
	248	#if 0
	249	/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
	250	#define CFG_DRAM_DDR 0
	251	#define CFG_DRAM_EMODE 0
	252	#define CFG_DRAM_MODE 0x008D
	253	#define CFG_DRAM_CONTROL 0x514F0000
	254	#define CFG_DRAM_CONFIG1 0xC2233A00
	255	#define CFG_DRAM_CONFIG2 0x88B70004
	256	#define CFG_DRAM_TAP_DEL 0x08
	257	#define CFG_DRAM_RAM_SIZE 0x19
	258	#endif
	259	#if 1
	260	/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
	261	#define CFG_DRAM_DDR 0
	262	#define CFG_DRAM_EMODE 0
	263	#define CFG_DRAM_MODE 0x00CD
	264	#define CFG_DRAM_CONTROL 0x514F0000
	265	#define CFG_DRAM_CONFIG1 0xD2333A00
	266	#define CFG_DRAM_CONFIG2 0x8AD70004
	267	#define CFG_DRAM_TAP_DEL 0x08
	268	#define CFG_DRAM_RAM_SIZE 0x19
	269	#endif
	270
c1896004 WD	271	/*
	272	* Environment settings
	273	*/
bb1f8b4f	274	#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
0e8d1586 JCPV	275	#define CONFIG_ENV_OFFSET 0x1000
0e8d1586 JCPV	276	#define CONFIG_ENV_SIZE 0x0700
c1896004	277
d4ca31c4 WD	278	/*
	279	* VPD settings
	280	*/
c1896004 WD	281	#define CFG_FACT_OFFSET 0x1800
c1896004 WD	282	#define CFG_FACT_SIZE 0x0800
d4ca31c4	283
c1896004	284	/*
d4ca31c4 WD	285	* Memory map
	286	*
	287	* Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
c1896004 WD	288	*/
	289	#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
	290	#define CFG_SDRAM_BASE 0x00000000
	291	#define CFG_DEFAULT_MBAR 0x80000000
	292
	293	/* Use SRAM until RAM will be available */
	294	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	295	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
	296
	297
	298	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	299	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	300	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	301
	302	#define CFG_MONITOR_BASE TEXT_BASE
	303	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	304	# define CFG_RAMBOOT 1
	305	#endif
	306
	307	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	308	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	309	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	310
	311	/*
	312	* Ethernet configuration
	313	*/
cbd8a35c	314	#define CONFIG_MPC5xxx_FEC 1
c1896004	315	#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
d4ca31c4	316	#define CONFIG_PHY_ADDR 0x1f
c1896004 WD	317	#define CONFIG_PHY_TYPE 0x79c874
c1896004 WD	318	/*
d4ca31c4 WD	319	* GPIO configuration:
	320	* PSC1,2,3 predefined as UART
	321	* PCI disabled
c1896004 WD	322	* Ethernet 100 with MD
c1896004 WD	323	*/
498b8db7	324	#define CFG_GPS_PORT_CONFIG 0x00058044
c1896004 WD	325
	326	/*
	327	* Miscellaneous configurable options
	328	*/
	329	#define CFG_LONGHELP /* undef to save memory */
	330	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
d794cfef	331	#if defined(CONFIG_CMD_KGDB)
c1896004 WD	332	# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	333	#else
	334	# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	335	#endif
	336	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	337	#define CFG_MAXARGS 16 /* max number of command args */
	338	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	339
	340	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	341	#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
	342
4d13cbad	343	#define CFG_LOAD_ADDR 0x200000 /* default load address */
c1896004 WD	344
	345	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	346
d794cfef JL	347	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	348	#if defined(CONFIG_CMD_KGDB)
	349	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	350	#endif
	351
	352
63e73c9a WD	353	#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
	354	#define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
	355	#define RTC(reg) (0xf0010000+reg)
	356	/* setup CS2 for M48T08. Must MAP 64kB */
	357	#define CFG_CS2_START RTC(0)
	358	#define CFG_CS2_SIZE 0x10000
	359	/* setup CS2 configuration register: */
	360	/* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
	361	/* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
	362	#define CFG_CS2_CFG 0x00047800
	363	#else
	364	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
	365	#endif
1c43771b	366
c1896004 WD	367	/*
	368	* Various low-level settings
	369	*/
	370	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	371	#define CFG_HID0_FINAL HID0_ICE
	372
	373	#define CFG_BOOTCS_START CFG_FLASH_BASE
	374	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	375	#define CFG_BOOTCS_CFG 0x00047801
	376	#define CFG_CS0_START CFG_FLASH_BASE
	377	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	378
	379	#define CFG_CS_BURST 0x00000000
	380	#define CFG_CS_DEADCYCLE 0x33333333
	381
	382	#define CFG_RESET_ADDRESS 0x7f000000
	383
4d13cbad WD	384	/*-----------------------------------------------------------------------
	385	* IDE/ATA stuff Supports IDE harddisk
	386	*-----------------------------------------------------------------------
	387	*/
	388
	389	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	390
	391	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	392	#undef CONFIG_IDE_LED /* LED for ide not supported */
	393
	394	#define CONFIG_IDE_RESET 1
	395	#define CONFIG_IDE_PREINIT
	396
	397	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	398	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	399
	400	#define CFG_ATA_IDE0_OFFSET 0x0000
	401
	402	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
	403
	404	/* Offset for data I/O */
	405	#define CFG_ATA_DATA_OFFSET (0x0060)
	406
	407	/* Offset for normal register accesses */
	408	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
	409
	410	/* Offset for alternate registers */
	411	#define CFG_ATA_ALT_OFFSET (0x005c)
	412
	413	/* Interval between registers */
	414	#define CFG_ATA_STRIDE 4
	415
c1896004	416	#endif /* __CONFIG_H */