[people/ms/u-boot.git] / include / configs / TOP5200.h

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
 *
 * TOP5200 differences from IceCube:
 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
 *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
 * 1 SDRAM/DDRAM Bank up to 256 MB
 * local VPD I2C Bus is software driven and uses
 *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
 * FLASH is re-located at 0xff000000
 * Internal regs are at 0xf0000000
 * Reset jumps to 0x00000100
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5XXX		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
#define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


#ifdef CONFIG_EVAL5200		/* PCI is supported with Evaluation board only */
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#  define CONFIG_PCI		1
#  define CONFIG_PCI_PNP		1
#  define CONFIG_PCI_SCAN_SHOW	1

#  define CONFIG_PCI_MEM_BUS	0x40000000
#  define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#  define CONFIG_PCI_MEM_SIZE	0x10000000

#  define CONFIG_PCI_IO_BUS	0x50000000
#  define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#  define CONFIG_PCI_IO_SIZE	0x01000000

#  define ADD_PCI_CMD 		CFG_CMD_PCI

#else	/* no Evaluation board */

#  define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */

#endif

/*
 * Supported commands
 */
#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | ADD_PCI_CMD | \
				 CFG_CMD_I2C | CFG_CMD_EEPROM)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * low boot
 */
#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
#   define CFG_LOWBOOT		1
#   define CFG_LOWBOOT16	1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */

/*
 * I2C configuration
 */
/*
 * EEPROM configuration
 */
#define CFG_EEPROM_PAGE_WRITE_BITS	3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70

#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_SIZE 0x2000

#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R

#undef	CONFIG_HARD_I2C			/* I2C with hardware support */
#define	CONFIG_SOFT_I2C		1

#if defined (CONFIG_SOFT_I2C)
#  define SDA0			0x40
#  define SCL0			0x80
#  define GPIOE0		*((volatile uchar*)(CFG_MBAR+0x0c00))
#  define DDR0			*((volatile uchar*)(CFG_MBAR+0x0c08))
#  define DVO0			*((volatile uchar*)(CFG_MBAR+0x0c0c))
#  define DVI0			*((volatile uchar*)(CFG_MBAR+0x0c20))
#  define ODE0			*((volatile uchar*)(CFG_MBAR+0x0c04))
#  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
#  define I2C_READ		((DVI0&SDA0)?1:0)
#  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
#  define I2C_SCL(x)	{if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
#  define I2C_DELAY		{udelay(5);}
#  define I2C_ACTIVE	{DDR0|=SDA0;}
#  define I2C_TRISTATE	{DDR0&=~SDA0;}
#  define CFG_I2C_SPEED		100000
#  define CFG_I2C_SLAVE		0x7F
#endif

#if defined (CONFIG_HARD_I2C)
#  define CFG_I2C_MODULE	2		/* Select I2C module #1 or #2 */
#  define CFG_I2C_SPEED		100000	/* 100 kHz */
#  define CFG_I2C_SLAVE		0x7F
#endif

/*
 * Flash configuration, expect one 16 Megabyte Bank at most
 */
#define CFG_FLASH_BASE		0xff000000
#define CFG_FLASH_SIZE		0x01000000
#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0)

#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */

/*
 * DRAM configuration - will be read from VPD later... TODO!
 */
#if 0
/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
#define	CFG_DRAM_DDR		0
#define CFG_DRAM_EMODE		0
#define CFG_DRAM_MODE		0x008D
#define CFG_DRAM_CONTROL	0x514F0000
#define CFG_DRAM_CONFIG1	0xC2233A00
#define CFG_DRAM_CONFIG2	0x88B70004
#define	CFG_DRAM_TAP_DEL	0x08
#define CFG_DRAM_RAM_SIZE	0x19
#endif
#if 1
/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
#define	CFG_DRAM_DDR		0
#define CFG_DRAM_EMODE		0
#define CFG_DRAM_MODE		0x00CD
#define CFG_DRAM_CONTROL	0x514F0000
#define CFG_DRAM_CONFIG1	0xD2333A00
#define CFG_DRAM_CONFIG2	0x8AD70004
#define	CFG_DRAM_TAP_DEL	0x08
#define CFG_DRAM_RAM_SIZE	0x19
#endif

/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
#define CFG_ENV_OFFSET		0x1000
#define CFG_ENV_SIZE		0x0700
#define CFG_I2C_EEPROM_ADDR 0x57

/*
 * VPD settings
 */
#define CFG_FACT_OFFSET		0x1800
#define CFG_FACT_SIZE		0x0800
#define CFG_I2C_FACT_ADDR	0x57

/*
 * Memory map
 *
 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
 */
#define CFG_MBAR			0xf0000000	/* DO NOT CHANGE this */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5XXX_FEC	1
#define CONFIG_FEC_10MBIT	1		/* Workaround for FEC 100Mbit problem */
#define	CONFIG_PHY_ADDR		0x1f
#define	CONFIG_PHY_TYPE		0x79c874
/*
 * GPIO configuration:
 * PSC1,2,3 predefined as UART
 * PCI disabled
 * Ethernet 100 with MD
 */
#define CFG_GPS_PORT_CONFIG	0x00058444

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#  define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Various low-level settings
 */
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x00047801
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#define CFG_RESET_ADDRESS	0x7f000000

#endif /* __CONFIG_H */
Commit	Line	Data
c1896004 WD	1	/*
c1896004 WD	2	* (C) Copyright 2003
d4ca31c4 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
	6	*
	7	* TOP5200 differences from IceCube:
	8	* 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
	9	* bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
	10	* 1 SDRAM/DDRAM Bank up to 256 MB
	11	* local VPD I2C Bus is software driven and uses
	12	* GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
	13	* FLASH is re-located at 0xff000000
	14	* Internal regs are at 0xf0000000
c1896004 WD	15	* Reset jumps to 0x00000100
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
	43
	44	#define CONFIG_MPC5XXX 1 /* This is an MPC5xxx CPU */
	45	#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
	46	#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
	47
d4ca31c4	48	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
c1896004 WD	49
	50	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	51	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	52
	53	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	54	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	55	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	56	#endif
	57
	58	/*
	59	* Serial console configuration
	60	*/
	61	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	62	#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
	63	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	64
	65
	66	#ifdef CONFIG_EVAL5200 /* PCI is supported with Evaluation board only */
	67	/*
	68	* PCI Mapping:
	69	* 0x40000000 - 0x4fffffff - PCI Memory
	70	* 0x50000000 - 0x50ffffff - PCI IO Space
	71	*/
	72	# define CONFIG_PCI 1
	73	# define CONFIG_PCI_PNP 1
	74	# define CONFIG_PCI_SCAN_SHOW 1
	75
	76	# define CONFIG_PCI_MEM_BUS 0x40000000
	77	# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	78	# define CONFIG_PCI_MEM_SIZE 0x10000000
	79
	80	# define CONFIG_PCI_IO_BUS 0x50000000
	81	# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	82	# define CONFIG_PCI_IO_SIZE 0x01000000
	83
	84	# define ADD_PCI_CMD CFG_CMD_PCI
	85
	86	#else /* no Evaluation board */
	87
	88	# define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
	89
	90	#endif
	91
	92	/*
	93	* Supported commands
	94	*/
	95	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| ADD_PCI_CMD \| \
	96	CFG_CMD_I2C \| CFG_CMD_EEPROM)
	97
	98	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	99	#include <cmd_confdefs.h>
	100
d4ca31c4 WD	101	/*
	102	* low boot
	103	*/
	104	#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
	105	# define CFG_LOWBOOT 1
	106	# define CFG_LOWBOOT16 1
	107	#endif
	108
c1896004 WD	109	/*
	110	* Autobooting
	111	*/
	112	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
d4ca31c4 WD	113
	114	#define CONFIG_PREBOOT "echo;" \
	115	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	116	"echo"
	117
	118	#undef CONFIG_BOOTARGS
	119
	120	#define CONFIG_EXTRA_ENV_SETTINGS \
	121	"netdev=eth0\0" \
	122	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	123	"nfsroot=$(serverip):$(rootpath)\0" \
	124	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	125	"addip=setenv bootargs $(bootargs) " \
	126	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	127	":$(hostname):$(netdev):off panic=1\0" \
	128	"flash_nfs=run nfsargs addip;" \
	129	"bootm $(kernel_addr)\0" \
	130	"flash_self=run ramargs addip;" \
	131	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	132	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	133	"rootpath=/opt/eldk/ppc_82xx\0" \
	134	"bootfile=/tftpboot/MPC5200/uImage\0" \
	135	""
	136
	137	#define CONFIG_BOOTCOMMAND "run flash_self"
c1896004 WD	138
	139	/*
	140	* IPB Bus clocking configuration.
	141	*/
	142	#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
d4ca31c4	143
c1896004 WD	144	/*
	145	* I2C configuration
	146	*/
	147	/*
	148	* EEPROM configuration
	149	*/
	150	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	151	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
	152
	153	#define CFG_I2C_EEPROM_ADDR_LEN 2
	154	#define CFG_EEPROM_SIZE 0x2000
d4ca31c4	155
c1896004 WD	156	#define CONFIG_ENV_OVERWRITE
c1896004 WD	157	#define CONFIG_MISC_INIT_R
d4ca31c4	158
c1896004 WD	159	#undef CONFIG_HARD_I2C /* I2C with hardware support */
c1896004 WD	160	#define CONFIG_SOFT_I2C 1
d4ca31c4	161
c1896004 WD	162	#if defined (CONFIG_SOFT_I2C)
	163	# define SDA0 0x40
	164	# define SCL0 0x80
d4ca31c4 WD	165	# define GPIOE0 ((volatile uchar)(CFG_MBAR+0x0c00))
	166	# define DDR0 ((volatile uchar)(CFG_MBAR+0x0c08))
	167	# define DVO0 ((volatile uchar)(CFG_MBAR+0x0c0c))
	168	# define DVI0 ((volatile uchar)(CFG_MBAR+0x0c20))
	169	# define ODE0 ((volatile uchar)(CFG_MBAR+0x0c04))
c1896004 WD	170	# define I2C_INIT {GPIOE0\|=(SDA0\|SCL0);ODE0\|=(SDA0\|SCL0);DVO0\|=(SDA0\|SCL0);DDR0\|=(SDA0\|SCL0);}
	171	# define I2C_READ ((DVI0&SDA0)?1:0)
	172	# define I2C_SDA(x) {if(x)DVO0\|=SDA0;else DVO0&=~SDA0;}
	173	# define I2C_SCL(x) {if(x)DVO0\|=SCL0;else DVO0&=~SCL0;}
	174	# define I2C_DELAY {udelay(5);}
	175	# define I2C_ACTIVE {DDR0\|=SDA0;}
	176	# define I2C_TRISTATE {DDR0&=~SDA0;}
	177	# define CFG_I2C_SPEED 100000
	178	# define CFG_I2C_SLAVE 0x7F
	179	#endif
d4ca31c4 WD	180
d4ca31c4 WD	181	#if defined (CONFIG_HARD_I2C)
c1896004 WD	182	# define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	183	# define CFG_I2C_SPEED 100000 /* 100 kHz */
	184	# define CFG_I2C_SLAVE 0x7F
d4ca31c4	185	#endif
c1896004 WD	186
	187	/*
	188	* Flash configuration, expect one 16 Megabyte Bank at most
	189	*/
	190	#define CFG_FLASH_BASE 0xff000000
	191	#define CFG_FLASH_SIZE 0x01000000
	192	#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
d4ca31c4	193	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0)
c1896004 WD	194
	195	#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
	196
	197	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	198	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	199
	200	#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
	201
d4ca31c4 WD	202	/*
	203	* DRAM configuration - will be read from VPD later... TODO!
	204	*/
	205	#if 0
	206	/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
	207	#define CFG_DRAM_DDR 0
	208	#define CFG_DRAM_EMODE 0
	209	#define CFG_DRAM_MODE 0x008D
	210	#define CFG_DRAM_CONTROL 0x514F0000
	211	#define CFG_DRAM_CONFIG1 0xC2233A00
	212	#define CFG_DRAM_CONFIG2 0x88B70004
	213	#define CFG_DRAM_TAP_DEL 0x08
	214	#define CFG_DRAM_RAM_SIZE 0x19
	215	#endif
	216	#if 1
	217	/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
	218	#define CFG_DRAM_DDR 0
	219	#define CFG_DRAM_EMODE 0
	220	#define CFG_DRAM_MODE 0x00CD
	221	#define CFG_DRAM_CONTROL 0x514F0000
	222	#define CFG_DRAM_CONFIG1 0xD2333A00
	223	#define CFG_DRAM_CONFIG2 0x8AD70004
	224	#define CFG_DRAM_TAP_DEL 0x08
	225	#define CFG_DRAM_RAM_SIZE 0x19
	226	#endif
	227
c1896004 WD	228	/*
	229	* Environment settings
	230	*/
	231	#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
	232	#define CFG_ENV_OFFSET 0x1000
	233	#define CFG_ENV_SIZE 0x0700
	234	#define CFG_I2C_EEPROM_ADDR 0x57
	235
d4ca31c4 WD	236	/*
	237	* VPD settings
	238	*/
c1896004 WD	239	#define CFG_FACT_OFFSET 0x1800
	240	#define CFG_FACT_SIZE 0x0800
	241	#define CFG_I2C_FACT_ADDR 0x57
d4ca31c4	242
c1896004	243	/*
d4ca31c4 WD	244	* Memory map
	245	*
	246	* Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
c1896004 WD	247	*/
	248	#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
	249	#define CFG_SDRAM_BASE 0x00000000
	250	#define CFG_DEFAULT_MBAR 0x80000000
	251
	252	/* Use SRAM until RAM will be available */
	253	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	254	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
	255
	256
	257	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	258	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	259	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	260
	261	#define CFG_MONITOR_BASE TEXT_BASE
	262	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	263	# define CFG_RAMBOOT 1
	264	#endif
	265
	266	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	267	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	268	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	269
	270	/*
	271	* Ethernet configuration
	272	*/
	273	#define CONFIG_MPC5XXX_FEC 1
	274	#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
d4ca31c4	275	#define CONFIG_PHY_ADDR 0x1f
c1896004 WD	276	#define CONFIG_PHY_TYPE 0x79c874
c1896004 WD	277	/*
d4ca31c4 WD	278	* GPIO configuration:
	279	* PSC1,2,3 predefined as UART
	280	* PCI disabled
c1896004 WD	281	* Ethernet 100 with MD
	282	*/
	283	#define CFG_GPS_PORT_CONFIG 0x00058444
	284
	285	/*
	286	* Miscellaneous configurable options
	287	*/
	288	#define CFG_LONGHELP /* undef to save memory */
	289	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	290	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	291	# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	292	#else
	293	# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	294	#endif
	295	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	296	#define CFG_MAXARGS 16 /* max number of command args */
	297	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	298
	299	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	300	#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
	301
	302	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	303
	304	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	305
	306	/*
	307	* Various low-level settings
	308	*/
	309	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	310	#define CFG_HID0_FINAL HID0_ICE
	311
	312	#define CFG_BOOTCS_START CFG_FLASH_BASE
	313	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	314	#define CFG_BOOTCS_CFG 0x00047801
	315	#define CFG_CS0_START CFG_FLASH_BASE
	316	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	317
	318	#define CFG_CS_BURST 0x00000000
	319	#define CFG_CS_DEADCYCLE 0x33333333
	320
	321	#define CFG_RESET_ADDRESS 0x7f000000
	322
	323	#endif /* __CONFIG_H */