[people/ms/u-boot.git] / include / configs / TQM5200.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define DEBUG 1

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
#define CONFIG_TQM5200		1	/* ... on TQM5200 module */

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		0
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
#define CONFIG_EEPRO100		1
#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1

#define ADD_PCI_CMD		0 /* CFG_CMD_PCI */

#else	/* MPC5100 */

#define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */

#endif

/* Partitions */
#undef CONFIG_MAC_PARTITION
#if defined (CONFIG_MINIFAP)
#define CONFIG_DOS_PARTITION
#endif

/* USB */
#if 0
#define CONFIG_USB_OHCI
#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#else
#define ADD_USB_CMD		0
#endif

/* POST support */
#define CONFIG_POST		(CFG_POST_MEMORY   | \
				 CFG_POST_CPU	   | \
				 CFG_POST_I2C)

#ifdef CONFIG_POST
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#else
#define CFG_CMD_POST_DIAG 0
#endif

/* IDE */
#if defined (CONFIG_MINIFAP)
#define ADD_IDE_CMD		CFG_CMD_IDE | CFG_CMD_FAT
#else
#define ADD_IDE_CMD		0
#endif

/*
 * Supported commands
 */
#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_I2C	| \
				ADD_PCI_CMD	| \
				ADD_USB_CMD	| \
				CFG_CMD_POST_DIAG | \
				CFG_CMD_DATE	| \
				CFG_CMD_REGINFO | \
				CFG_CMD_MII	| \
				CFG_CMD_PING	| \
				ADD_IDE_CMD)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#if (TEXT_BASE == 0xFC000000)		/* Boot low */
#   define CFG_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#if defined (CONFIG_TQM5200_AA)
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0"				\
	"bootfile=uImage_tqm5200_mkr\0"					\
	"load=tftp 200000 $(loadfile)\0"				\
	"load133=tftp 200000 $(loadfile133)\0"				\
	"loadfile=u-boot_tqm5200_aa_mkr.bin\0"				\
	"loadfile133=u-boot_tqm5200_aa_133_mkr.bin\0"			\
	"update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0"		\
	"serverip=172.20.5.13\0"					\
	""
#else
#if defined (CONFIG_TQM5200_AB)
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0"				\
	"bootfile=uImage_tqm5200_mkr\0"					\
	"load=tftp 200000 $(loadfile)\0"				\
	"load133=tftp 200000 $(loadfile133)\0"				\
	"loadfile=u-boot_tqm5200_ab_mkr.bin\0"				\
	"loadfile133=u-boot_tqm5200_ab_133_mkr.bin\0"			\
	"update=protect off 1:0-1; erase 1:0-1; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-1\0"		\
	"serverip=172.20.5.13\0"					\
	""
#else
#if defined (CONFIG_TQM5200_AC)
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0"				\
	"bootfile=uImage_tqm5200_mkr\0"					\
	"load=tftp 200000 $(loadfile)\0"				\
	"load133=tftp 200000 $(loadfile133)\0"				\
	"loadfile=u-boot_tqm5200_ac_mkr.bin\0"				\
	"loadfile133=u-boot_tqm5200_ac_133_mkr.bin\0"			\
	"update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0"		\
	"serverip=172.20.5.13\0"					\
	""
#endif
#endif
#endif

#define CONFIG_BOOTCOMMAND	"run net_nfs"

/*
 * IPB Bus clocking configuration.
 */
#define CFG_IPBSPEED_133		/* define for 133MHz speed */

#if defined(CFG_IPBSPEED_133)
/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
 * been tested with a IPB Bus Clock of 66 MHz.
 */
#define CFG_PCISPEED_66			/* define for 66MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#if defined (CONFIG_MINIFAP)
#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
#else
#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
#endif

/*
 * I2C clock frequency
 *
 * Please notice, that the resulting clock frequency could differ from the
 * configured value. This is because the I2C clock is derived from system
 * clock over a frequency divider with only a few divider values. U-boot
 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 * approximation allways lies below the configured value, never above.
 */
#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 * same configuration could be used.
 */
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN		2
#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20

/*
 * HW-Monitor configuration on Mini-FAP
 */
#if defined (CONFIG_MINIFAP)
#define CFG_I2C_HWMON_ADDR		0x2C
#endif

/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
				CFG_I2C_SLAVE }
#elif defined (CONFIG_TQM5200_AC)
#define I2C_ADDR_LIST	{	CFG_I2C_SLAVE }
#endif

#if defined (CONFIG_MINIFAP)
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
				CFG_I2C_HWMON_ADDR,	\
				CFG_I2C_SLAVE }
#endif

/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */

#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AC)
#define CFG_FLASH_SIZE		0x00400000 /* 4 MByte */
#define CFG_MAX_FLASH_SECT	35	/* max num of sects on one chip */
#else
#ifdef CONFIG_TQM5200_AB
#define CFG_FLASH_SIZE		0x02000000 /* 32 MByte */
#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
#endif
#endif

#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00740000 + 0x00800000)
#else	/* CFG_LOWBOOT */
#if defined(CONFIG_TQM5200_AA) ||  defined(CONFIG_TQM5200_AB) || \
    defined (CONFIG_TQM5200_AC)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
#endif
#endif	/* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/


/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE		0x10000
#define CFG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 *
 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 *	Bit 0 (mask: 0x80000000): 1
 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
 *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 *	      EEPROM
 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
 *	011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 * tests.
 */
#if defined (CONFIG_MINIFAP)
#define CFG_GPS_PORT_CONFIG	0x93000004
#else
#define CFG_GPS_PORT_CONFIG	0x83000004
#endif

/*
 * RTC configuration
 */
#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 * which is normally part of the default commands (CFV_CMD_DFL)
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
#else
#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
#endif
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

/*
 * SRAM - Do not map below 2 GB in address space, because this area is used
 * for SDRAM autosizing.
 */
#ifdef CONFIG_TQM5200_AB
#define CFG_CS2_START		0xE5000000
#define CFG_CS2_SIZE		0x80000		/* 512 kByte */
#define CFG_CS2_CFG		0x0004D930
#endif

/*
 * Grafic controller - Do not map below 2 GB in address space, because this
 * area is used for SDRAM autosizing.
 */
#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC)
#define CFG_CS1_START		0xE0000000
#define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
#define CFG_CS1_CFG		0x0148FF70
#define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
#endif

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#define CFG_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/

#define CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers						     */
#define CFG_ATA_STRIDE		4

#endif /* __CONFIG_H */
Commit	Line	Data
56523f12 WD	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	#define DEBUG 1
	31
	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
	36
	37	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	38	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	39	#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
	40
	41	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	42
	43	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	44	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	45
	46	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	47	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	48	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	49	#endif
	50
	51	/*
	52	* Serial console configuration
	53	*/
	54	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	55	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	56	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	57
	58
	59	#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
	60	/*
	61	* PCI Mapping:
	62	* 0x40000000 - 0x4fffffff - PCI Memory
	63	* 0x50000000 - 0x50ffffff - PCI IO Space
	64	*/
65	#define CONFIG_PCI 0
66	#define CONFIG_PCI_PNP 1
67	#define CONFIG_PCI_SCAN_SHOW 1
68
69	#define CONFIG_PCI_MEM_BUS 0x40000000
70	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
71	#define CONFIG_PCI_MEM_SIZE 0x10000000
72
73	#define CONFIG_PCI_IO_BUS 0x50000000
74	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
75	#define CONFIG_PCI_IO_SIZE 0x01000000
76
77	#define CONFIG_NET_MULTI 1
78	#define CONFIG_EEPRO100 1
79	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
80	#define CONFIG_NS8382X 1
81
81050926	82	#define ADD_PCI_CMD 0 /* CFG_CMD_PCI */
56523f12 WD	83
	84	#else /* MPC5100 */
	85
	86	#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
	87
	88	#endif
	89
	90	/* Partitions */
	91	#undef CONFIG_MAC_PARTITION
	92	#if defined (CONFIG_MINIFAP)
	93	#define CONFIG_DOS_PARTITION
	94	#endif
	95
	96	/* USB */
	97	#if 0
	98	#define CONFIG_USB_OHCI
81050926	99	#define ADD_USB_CMD CFG_CMD_USB \| CFG_CMD_FAT
56523f12 WD	100	#define CONFIG_USB_STORAGE
56523f12 WD	101	#else
81050926	102	#define ADD_USB_CMD 0
56523f12 WD	103	#endif
	104
	105	/* POST support */
	106	#define CONFIG_POST (CFG_POST_MEMORY \| \
	107	CFG_POST_CPU \| \
	108	CFG_POST_I2C)
	109
	110	#ifdef CONFIG_POST
	111	#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
	112	/* preserve space for the post_word at end of on-chip SRAM */
	113	#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
	114	#else
	115	#define CFG_CMD_POST_DIAG 0
	116	#endif
	117
	118	/* IDE */
	119	#if defined (CONFIG_MINIFAP)
	120	#define ADD_IDE_CMD CFG_CMD_IDE \| CFG_CMD_FAT
	121	#else
	122	#define ADD_IDE_CMD 0
	123	#endif
	124
	125	/*
	126	* Supported commands
	127	*/
	128	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	129	CFG_CMD_EEPROM \| \
	130	CFG_CMD_I2C \| \
	131	ADD_PCI_CMD \| \
	132	ADD_USB_CMD \| \
	133	CFG_CMD_POST_DIAG \| \
	134	CFG_CMD_DATE \| \
81050926	135	CFG_CMD_REGINFO \| \
56523f12 WD	136	CFG_CMD_MII \| \
	137	CFG_CMD_PING \| \
	138	ADD_IDE_CMD)
	139
	140	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	141	#include <cmd_confdefs.h>
	142
	143	#if (TEXT_BASE == 0xFC000000) /* Boot low */
81050926	144	# define CFG_LOWBOOT 1
56523f12 WD	145	#endif
	146
	147	/*
	148	* Autobooting
	149	*/
	150	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	151
81050926	152	#define CONFIG_PREBOOT "echo;" \
56523f12 WD	153	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	154	"echo"
	155
	156	#undef CONFIG_BOOTARGS
	157
	158	#if defined (CONFIG_TQM5200_AA)
81050926	159	#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 WD	160	"netdev=eth0\0" \
	161	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	162	"nfsroot=$(serverip):$(rootpath)\0" \
	163	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	164	"addip=setenv bootargs $(bootargs) " \
	165	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	166	":$(hostname):$(netdev):off panic=1\0" \
	167	"flash_nfs=run nfsargs addip;" \
	168	"bootm $(kernel_addr)\0" \
	169	"flash_self=run ramargs addip;" \
	170	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	171	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	172	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
	173	"bootfile=uImage_tqm5200_mkr\0" \
	174	"load=tftp 200000 $(loadfile)\0" \
	175	"load133=tftp 200000 $(loadfile133)\0" \
	176	"loadfile=u-boot_tqm5200_aa_mkr.bin\0" \
81050926	177	"loadfile133=u-boot_tqm5200_aa_133_mkr.bin\0" \
56523f12 WD	178	"update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \
	179	"serverip=172.20.5.13\0" \
	180	""
	181	#else
	182	#if defined (CONFIG_TQM5200_AB)
81050926	183	#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 WD	184	"netdev=eth0\0" \
	185	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	186	"nfsroot=$(serverip):$(rootpath)\0" \
	187	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	188	"addip=setenv bootargs $(bootargs) " \
	189	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	190	":$(hostname):$(netdev):off panic=1\0" \
	191	"flash_nfs=run nfsargs addip;" \
	192	"bootm $(kernel_addr)\0" \
	193	"flash_self=run ramargs addip;" \
	194	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	195	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	196	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
	197	"bootfile=uImage_tqm5200_mkr\0" \
	198	"load=tftp 200000 $(loadfile)\0" \
	199	"load133=tftp 200000 $(loadfile133)\0" \
	200	"loadfile=u-boot_tqm5200_ab_mkr.bin\0" \
81050926	201	"loadfile133=u-boot_tqm5200_ab_133_mkr.bin\0" \
56523f12 WD	202	"update=protect off 1:0-1; erase 1:0-1; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-1\0" \
	203	"serverip=172.20.5.13\0" \
	204	""
	205	#else
	206	#if defined (CONFIG_TQM5200_AC)
81050926	207	#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 WD	208	"netdev=eth0\0" \
	209	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	210	"nfsroot=$(serverip):$(rootpath)\0" \
	211	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	212	"addip=setenv bootargs $(bootargs) " \
	213	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	214	":$(hostname):$(netdev):off panic=1\0" \
	215	"flash_nfs=run nfsargs addip;" \
	216	"bootm $(kernel_addr)\0" \
	217	"flash_self=run ramargs addip;" \
	218	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	219	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	220	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
	221	"bootfile=uImage_tqm5200_mkr\0" \
	222	"load=tftp 200000 $(loadfile)\0" \
	223	"load133=tftp 200000 $(loadfile133)\0" \
	224	"loadfile=u-boot_tqm5200_ac_mkr.bin\0" \
81050926	225	"loadfile133=u-boot_tqm5200_ac_133_mkr.bin\0" \
56523f12 WD	226	"update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \
	227	"serverip=172.20.5.13\0" \
	228	""
	229	#endif
	230	#endif
	231	#endif
	232
	233	#define CONFIG_BOOTCOMMAND "run net_nfs"
	234
	235	/*
	236	* IPB Bus clocking configuration.
	237	*/
81050926	238	#define CFG_IPBSPEED_133 /* define for 133MHz speed */
56523f12 WD	239
	240	#if defined(CFG_IPBSPEED_133)
	241	/*
	242	* PCI Bus clocking configuration
	243	*
	244	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
	245	* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
	246	* been tested with a IPB Bus Clock of 66 MHz.
	247	*/
	248	#define CFG_PCISPEED_66 /* define for 66MHz speed */
	249	#endif
	250
	251	/*
	252	* I2C configuration
	253	*/
	254	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	255	#if defined (CONFIG_MINIFAP)
	256	#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	257	#else
	258	#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
	259	#endif
	260
	261	/*
	262	* I2C clock frequency
	263	*
	264	* Please notice, that the resulting clock frequency could differ from the
	265	* configured value. This is because the I2C clock is derived from system
	266	* clock over a frequency divider with only a few divider values. U-boot
	267	* calculates the best approximation for CFG_I2C_SPEED. However the calculated
	268	* approximation allways lies below the configured value, never above.
	269	*/
	270	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	271	#define CFG_I2C_SLAVE 0x7F
	272
	273	/*
	274	* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
	275	* also). For other EEPROMs configuration should be verified. On Mini-FAP the
	276	* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
	277	* same configuration could be used.
	278	*/
	279	#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	280	#define CFG_I2C_EEPROM_ADDR_LEN 2
	281	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	282	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
	283
	284	/*
	285	* HW-Monitor configuration on Mini-FAP
	286	*/
	287	#if defined (CONFIG_MINIFAP)
	288	#define CFG_I2C_HWMON_ADDR 0x2C
	289	#endif
	290
	291	/* List of I2C addresses to be verified by POST */
	292	#if defined (CONFIG_TQM5200_AA) \|\| defined (CONFIG_TQM5200_AB)
	293	#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
	294	CFG_I2C_SLAVE }
	295	#elif defined (CONFIG_TQM5200_AC)
	296	#define I2C_ADDR_LIST { CFG_I2C_SLAVE }
	297	#endif
	298
	299	#if defined (CONFIG_MINIFAP)
	300	#undef I2C_ADDR_LIST
	301	#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
	302	CFG_I2C_HWMON_ADDR, \
303	CFG_I2C_SLAVE }
304	#endif
305
306	/*
307	* Flash configuration
308	*/
309	#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
310
311	#if defined (CONFIG_TQM5200_AA) \|\| defined (CONFIG_TQM5200_AC)
312	#define CFG_FLASH_SIZE 0x00400000 /* 4 MByte */
313	#define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */
314	#else
315	#ifdef CONFIG_TQM5200_AB
316	#define CFG_FLASH_SIZE 0x02000000 /* 32 MByte */
317	#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
318	#endif
319	#endif
320
321	#if !defined(CFG_LOWBOOT)
322	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
323	#else /* CFG_LOWBOOT */
324	#if defined(CONFIG_TQM5200_AA) \|\| defined(CONFIG_TQM5200_AB) \|\| \
325	defined (CONFIG_TQM5200_AC)
326	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
327	#endif
328	#endif /* CFG_LOWBOOT */
329	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
330	(= chip selects) */
81050926 WD	331	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
81050926 WD	332	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
56523f12 WD	333
	334
	335	/*
	336	* Environment settings
	337	*/
	338	#define CFG_ENV_IS_IN_FLASH 1
	339	#define CFG_ENV_SIZE 0x10000
	340	#define CFG_ENV_SECT_SIZE 0x20000
	341	#define CONFIG_ENV_OVERWRITE 1
	342
	343	/*
	344	* Memory map
	345	*/
	346	#define CFG_MBAR 0xF0000000
	347	#define CFG_SDRAM_BASE 0x00000000
	348	#define CFG_DEFAULT_MBAR 0x80000000
	349
	350	/* Use ON-Chip SRAM until RAM will be available */
	351	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	352	#ifdef CONFIG_POST
	353	/* preserve space for the post_word at end of on-chip SRAM */
	354	#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
	355	#else
	356	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
	357	#endif
	358
	359
	360	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	361	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	362	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	363
	364	#define CFG_MONITOR_BASE TEXT_BASE
	365	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	366	# define CFG_RAMBOOT 1
	367	#endif
	368
	369	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	370	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	371	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	372
	373	/*
	374	* Ethernet configuration
	375	*/
	376	#define CONFIG_MPC5xxx_FEC 1
	377	/*
	378	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	379	*/
	380	/* #define CONFIG_FEC_10MBIT 1 */
	381	#define CONFIG_PHY_ADDR 0x00
	382
	383	/*
	384	* GPIO configuration
	385	*
	386	* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
	387	* Bit 0 (mask: 0x80000000): 1
	388	* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
	389	* 00 -> No Alternatives, I2C1 is used for onboard EEPROM
81050926 WD	390	* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
81050926 WD	391	* EEPROM
56523f12 WD	392	* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
	393	* use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
	394	* 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
	395	* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
	396	* tests.
	397	*/
	398	#if defined (CONFIG_MINIFAP)
	399	#define CFG_GPS_PORT_CONFIG 0x93000004
	400	#else
	401	#define CFG_GPS_PORT_CONFIG 0x83000004
	402	#endif
	403
	404	/*
	405	* RTC configuration
	406	*/
	407	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
	408
	409	/*
	410	* Miscellaneous configurable options
	411	*/
	412	#define CFG_LONGHELP /* undef to save memory */
	413	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	414	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	415	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	416	#else
	417	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	418	#endif
	419	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	420	#define CFG_MAXARGS 16 /* max number of command args */
	421	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	422
	423	/* Enable an alternate, more extensive memory test */
	424	#define CFG_ALT_MEMTEST
	425
	426	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	427	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	428
	429	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	430
	431	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	432
	433	/*
	434	* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
	435	* which is normally part of the default commands (CFV_CMD_DFL)
	436	*/
	437	#define CONFIG_LOOPW
	438
	439	/*
	440	* Various low-level settings
	441	*/
	442	#if defined(CONFIG_MPC5200)
	443	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	444	#define CFG_HID0_FINAL HID0_ICE
	445	#else
	446	#define CFG_HID0_INIT 0
	447	#define CFG_HID0_FINAL 0
	448	#endif
	449
	450	#define CFG_BOOTCS_START CFG_FLASH_BASE
	451	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	452	#ifdef CFG_PCISPEED_66
	453	#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
	454	#else
	455	#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
456	#endif
457	#define CFG_CS0_START CFG_FLASH_BASE
458	#define CFG_CS0_SIZE CFG_FLASH_SIZE
459
460	/*
461	* SRAM - Do not map below 2 GB in address space, because this area is used
462	* for SDRAM autosizing.
463	*/
464	#ifdef CONFIG_TQM5200_AB
465	#define CFG_CS2_START 0xE5000000
466	#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
467	#define CFG_CS2_CFG 0x0004D930
468	#endif
469
470	/*
471	* Grafic controller - Do not map below 2 GB in address space, because this
472	* area is used for SDRAM autosizing.
473	*/
474	#if defined (CONFIG_TQM5200_AB) \|\| defined (CONFIG_TQM5200_AC)
475	#define CFG_CS1_START 0xE0000000
476	#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
477	#define CFG_CS1_CFG 0x0148FF70
478	#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
479	#endif
480
481	#define CFG_CS_BURST 0x00000000
482	#define CFG_CS_DEADCYCLE 0x33333333
483
484	#define CFG_RESET_ADDRESS 0xff000000
485
486	/*-----------------------------------------------------------------------
487	* USB stuff
488	*-----------------------------------------------------------------------
489	*/
490	#define CONFIG_USB_CLOCK 0x0001BBBB
491	#define CONFIG_USB_CONFIG 0x00001000
492
493	/*-----------------------------------------------------------------------
494	* IDE/ATA stuff Supports IDE harddisk
495	*-----------------------------------------------------------------------
496	*/
497
81050926	498	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12	499
81050926 WD	500	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
81050926 WD	501	#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12	502
81050926	503	#define CONFIG_IDE_RESET /* reset for ide supported */
56523f12 WD	504	#define CONFIG_IDE_PREINIT
	505
	506	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	507	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	508
	509	#define CFG_ATA_IDE0_OFFSET 0x0000
	510
	511	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
	512
	513	/* Offset for data I/O */
	514	#define CFG_ATA_DATA_OFFSET (0x0060)
	515
	516	/* Offset for normal register accesses */
	517	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
	518
	519	/* Offset for alternate registers */
	520	#define CFG_ATA_ALT_OFFSET (0x005C)
	521
81050926 WD	522	/* Interval between registers */
81050926 WD	523	#define CFG_ATA_STRIDE 4
56523f12 WD	524
56523f12 WD	525	#endif /* __CONFIG_H */