projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0f8c9768 | 1 | /* |
| 414eec35 | 2 | * (C) Copyright 2001-2005 |
| 0f8c9768 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | /* | |
| 32 | * Imported from global configuration: | |
| 27b207fd WD |
33 | * CONFIG_MPC8255 |
| 34 | * CONFIG_MPC8265 | |
| 35 | * CONFIG_200MHz | |
| 0f8c9768 WD |
36 | * CONFIG_266MHz |
| 37 | * CONFIG_300MHz | |
| 27b207fd WD |
38 | * CONFIG_L2_CACHE |
| 39 | * CONFIG_BUSMODE_60x | |
| 0f8c9768 WD |
40 | */ |
| 41 | ||
| 42 | /* | |
| 43 | * High Level Configuration Options | |
| 44 | * (easy to change) | |
| 45 | */ | |
| 46 | ||
| 2ae18241 WD |
47 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
| 48 | ||
| 0f8c9768 WD |
49 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ |
| 50 | ||
| 51 | #if 0 | |
| 52 | #define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ | |
| 53 | #else | |
| 54 | #define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ | |
| 55 | #endif | |
| 56 | ||
| 9c4c5ae3 JL |
57 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
| 58 | ||
| 0f8c9768 WD |
59 | #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ |
| 60 | ||
| 61 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 62 | ||
| ae3af05e WD |
63 | #define CONFIG_BOOTCOUNT_LIMIT |
| 64 | ||
| 055b12f2 | 65 | #define CONFIG_BAUDRATE 115200 |
| 0f8c9768 | 66 | |
| 32bf3d14 | 67 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
| 0f8c9768 WD |
68 | |
| 69 | #undef CONFIG_BOOTARGS | |
| 506f0441 WD |
70 | |
| 71 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| ae3af05e | 72 | "netdev=eth0\0" \ |
| 506f0441 | 73 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| fe126d8b | 74 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 506f0441 | 75 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| fe126d8b WD |
76 | "addip=setenv bootargs ${bootargs} " \ |
| 77 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 78 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 506f0441 | 79 | "flash_nfs=run nfsargs addip;" \ |
| fe126d8b | 80 | "bootm ${kernel_addr}\0" \ |
| 506f0441 | 81 | "flash_self=run ramargs addip;" \ |
| fe126d8b WD |
82 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 83 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
| 055b12f2 WD |
84 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
| 85 | "bootfile=tqm8260/uImage\0" \ | |
| 86b4bafd WD |
86 | "kernel_addr=400C0000\0" \ |
| 87 | "ramdisk_addr=40240000\0" \ | |
| 506f0441 WD |
88 | "" |
| 89 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 0f8c9768 WD |
90 | |
| 91 | /* enable I2C and select the hardware/software driver */ | |
| ea818dbb HS |
92 | #define CONFIG_SYS_I2C |
| 93 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
| 94 | #define CONFIG_SYS_I2C_SOFT_SPEED 400000 | |
| 95 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F | |
| 0f8c9768 WD |
96 | |
| 97 | /* | |
| 98 | * Software (bit-bang) I2C driver configuration | |
| 99 | */ | |
| 100 | ||
| 101 | /* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */ | |
| 102 | #if (CONFIG_TQM8260 <= 100) | |
| 103 | ||
| 104 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
| 105 | #define I2C_ACTIVE (iop->pdir |= 0x00020000) | |
| 106 | #define I2C_TRISTATE (iop->pdir &= ~0x00020000) | |
| 107 | #define I2C_READ ((iop->pdat & 0x00020000) != 0) | |
| 108 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \ | |
| 109 | else iop->pdat &= ~0x00020000 | |
| 110 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \ | |
| 111 | else iop->pdat &= ~0x00010000 | |
| 112 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
| 113 | ||
| 114 | #else | |
| 115 | ||
| 116 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
| 117 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
| 118 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
| 119 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
| 120 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
| 121 | else iop->pdat &= ~0x00010000 | |
| 122 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
| 123 | else iop->pdat &= ~0x00020000 | |
| 124 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
| 125 | #endif | |
| 126 | ||
| 6d0f6bcf JCPV |
127 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
| 128 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
| 129 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
| 130 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
| 0f8c9768 WD |
131 | |
| 132 | #define CONFIG_I2C_X | |
| 133 | ||
| 134 | /* | |
| 135 | * select serial console configuration | |
| 136 | * | |
| 137 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
| 138 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
| 139 | * for SCC). | |
| 140 | * | |
| 141 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
| 142 | * defined elsewhere (for example, on the cogent platform, there are serial | |
| 143 | * ports on the motherboard which are used for the serial console - see | |
| 144 | * cogent/cma101/serial.[ch]). | |
| 145 | */ | |
| 146 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
| 147 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
| 148 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
| 149 | #ifdef CONFIG_82xx_CONS_SMC1 | |
| 150 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
| 151 | #endif | |
| 152 | #ifdef CONFIG_82xx_CONS_SMC2 | |
| 153 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
| 154 | #endif | |
| 155 | ||
| 156 | #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ | |
| 157 | #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ | |
| 158 | #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ | |
| 159 | ||
| 160 | /* | |
| 161 | * select ethernet configuration | |
| 162 | * | |
| 163 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
| 164 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
| 165 | * for FCC) | |
| 166 | * | |
| 167 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
| 639221c7 | 168 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
| 0f8c9768 WD |
169 | * |
| 170 | * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the | |
| 171 | * X.29 connector, and FCC2 is hardwired to the X.1 connector) | |
| 172 | */ | |
| 173 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
| 174 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
| 175 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
| 176 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
| 177 | ||
| 178 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) | |
| 179 | ||
| 180 | /* | |
| 181 | * - RX clk is CLK11 | |
| 182 | * - TX clk is CLK12 | |
| 183 | */ | |
| d4590da4 | 184 | # define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) |
| 0f8c9768 WD |
185 | |
| 186 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
| 187 | ||
| 188 | /* | |
| 189 | * - Rx-CLK is CLK13 | |
| 190 | * - Tx-CLK is CLK14 | |
| 191 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
| 192 | * - Enable Full Duplex in FSMR | |
| 193 | */ | |
| d4590da4 MF |
194 | # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
| 195 | # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
| 6d0f6bcf JCPV |
196 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
| 197 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
| 0f8c9768 WD |
198 | |
| 199 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
| 200 | ||
| 201 | ||
| 202 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
| 27b207fd | 203 | #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) |
| 7aa78614 | 204 | # define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
| 27b207fd | 205 | #else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */ |
| 7aa78614 WD |
206 | # ifndef CONFIG_300MHz |
| 207 | # define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
| 208 | # else | |
| 209 | # define CONFIG_8260_CLKIN 83333000 /* in Hz */ | |
| 210 | # endif | |
| 211 | #endif /* CONFIG_MPC8255 */ | |
| 0f8c9768 | 212 | |
| 0f8c9768 | 213 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 6d0f6bcf | 214 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| 0f8c9768 WD |
215 | |
| 216 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 217 | ||
| 414eec35 WD |
218 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
| 219 | ||
| 37d4bb70 JL |
220 | |
| 221 | /* | |
| 222 | * BOOTP options | |
| 223 | */ | |
| 224 | #define CONFIG_BOOTP_SUBNETMASK | |
| 225 | #define CONFIG_BOOTP_GATEWAY | |
| 226 | #define CONFIG_BOOTP_HOSTNAME | |
| 227 | #define CONFIG_BOOTP_BOOTPATH | |
| 228 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 0f8c9768 | 229 | |
| 0f8c9768 | 230 | |
| 2694690e JL |
231 | /* |
| 232 | * Command line configuration. | |
| 233 | */ | |
| 234 | #include <config_cmd_default.h> | |
| 235 | ||
| 236 | #define CONFIG_CMD_DHCP | |
| 237 | #define CONFIG_CMD_I2C | |
| 238 | #define CONFIG_CMD_EEPROM | |
| 239 | #define CONFIG_CMD_NFS | |
| 240 | #define CONFIG_CMD_SNTP | |
| 241 | ||
| 0f8c9768 WD |
242 | |
| 243 | /* | |
| 244 | * Miscellaneous configurable options | |
| 245 | */ | |
| 6d0f6bcf JCPV |
246 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 247 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 2751a95a WD |
248 | |
| 249 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
| 6d0f6bcf | 250 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
| 2751a95a | 251 | |
| 2694690e | 252 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 253 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 0f8c9768 | 254 | #else |
| 6d0f6bcf | 255 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 0f8c9768 | 256 | #endif |
| 6d0f6bcf JCPV |
257 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 258 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 259 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 0f8c9768 | 260 | |
| 6d0f6bcf JCPV |
261 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 262 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 0f8c9768 | 263 | |
| 6d0f6bcf | 264 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 0f8c9768 | 265 | |
| 6d0f6bcf | 266 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 0f8c9768 | 267 | |
| 6d0f6bcf | 268 | #define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ |
| 0f8c9768 WD |
269 | |
| 270 | /* | |
| 271 | * For booting Linux, the board info and command line data | |
| 272 | * have to be in the first 8 MB of memory, since this is | |
| 273 | * the maximum mapped by the Linux kernel during initialization. | |
| 274 | */ | |
| 6d0f6bcf | 275 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 0f8c9768 WD |
276 | |
| 277 | ||
| 278 | /* What should the base address of the main FLASH be and how big is | |
| 14d0a02a | 279 | * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk |
| 0f8c9768 WD |
280 | * The main FLASH is whichever is connected to *CS0. |
| 281 | */ | |
| 6d0f6bcf JCPV |
282 | #define CONFIG_SYS_FLASH0_BASE 0x40000000 |
| 283 | #define CONFIG_SYS_FLASH1_BASE 0x60000000 | |
| 284 | #define CONFIG_SYS_FLASH0_SIZE 32 | |
| 285 | #define CONFIG_SYS_FLASH1_SIZE 32 | |
| 0f8c9768 WD |
286 | |
| 287 | /* Flash bank size (for preliminary settings) | |
| 288 | */ | |
| 6d0f6bcf | 289 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE |
| 0f8c9768 WD |
290 | |
| 291 | /*----------------------------------------------------------------------- | |
| 292 | * FLASH organization | |
| 293 | */ | |
| 6d0f6bcf JCPV |
294 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
| 295 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
| 0f8c9768 | 296 | |
| 6d0f6bcf JCPV |
297 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
| 298 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
| 0f8c9768 | 299 | |
| 60c68d9c WD |
300 | /* use CFI flash driver */ |
| 301 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ | |
| 302 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
| 303 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
| 304 | #define CONFIG_SYS_FLASH_EMPTY_INFO 1 | |
| 305 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
| 306 | ||
| 5a1aceb0 | 307 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 055b12f2 WD |
308 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
| 309 | #define CONFIG_ENV_SIZE 0x08000 | |
| 0e8d1586 | 310 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
| 055b12f2 WD |
311 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
| 312 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
| 0f8c9768 WD |
313 | |
| 314 | /*----------------------------------------------------------------------- | |
| 315 | * Hardware Information Block | |
| 316 | */ | |
| 6d0f6bcf JCPV |
317 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
| 318 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
| 319 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
| 0f8c9768 WD |
320 | |
| 321 | /*----------------------------------------------------------------------- | |
| 322 | * Hard Reset Configuration Words | |
| 323 | * | |
| 6d0f6bcf | 324 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
| 0f8c9768 | 325 | * defines for the various registers affected by the HRCW e.g. changing |
| 6d0f6bcf | 326 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
| 0f8c9768 | 327 | */ |
| 7aa78614 WD |
328 | #define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) |
| 329 | ||
| 27b207fd | 330 | #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) |
| 6d0f6bcf | 331 | # define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) |
| 27b207fd | 332 | #else /* ! MPC8255 && !MPC8265 */ |
| 7aa78614 | 333 | # if defined(CONFIG_266MHz) |
| 6d0f6bcf | 334 | # define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) |
| 7aa78614 | 335 | # elif defined(CONFIG_300MHz) |
| 6d0f6bcf | 336 | # define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110) |
| 7aa78614 | 337 | # else |
| 6d0f6bcf | 338 | # define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__) |
| 7aa78614 WD |
339 | # endif |
| 340 | #endif /* CONFIG_MPC8255 */ | |
| 0f8c9768 WD |
341 | |
| 342 | /* no slaves so just fill with zeros */ | |
| 6d0f6bcf JCPV |
343 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
| 344 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
| 345 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
| 346 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
| 347 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
| 348 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
| 349 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
| 0f8c9768 WD |
350 | |
| 351 | /*----------------------------------------------------------------------- | |
| 352 | * Internal Memory Mapped Register | |
| 353 | */ | |
| 6d0f6bcf | 354 | #define CONFIG_SYS_IMMR 0xFFF00000 |
| 0f8c9768 WD |
355 | |
| 356 | /*----------------------------------------------------------------------- | |
| 357 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 358 | */ | |
| 6d0f6bcf | 359 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
| 553f0982 | 360 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
| 25ddd1fb | 361 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 6d0f6bcf | 362 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 0f8c9768 WD |
363 | |
| 364 | /*----------------------------------------------------------------------- | |
| 365 | * Start addresses for the final memory configuration | |
| 366 | * (Set up by the startup code) | |
| 6d0f6bcf | 367 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 0f8c9768 | 368 | * |
| 6d0f6bcf | 369 | * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM |
| 0f8c9768 WD |
370 | * is mapped at SDRAM_BASE2_PRELIM. |
| 371 | */ | |
| 6d0f6bcf JCPV |
372 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 373 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE | |
| 14d0a02a | 374 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| 6d0f6bcf | 375 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 055b12f2 | 376 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc()*/ |
| 0f8c9768 | 377 | |
| 0f8c9768 WD |
378 | /*----------------------------------------------------------------------- |
| 379 | * Cache Configuration | |
| 380 | */ | |
| 6d0f6bcf | 381 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
| 2694690e | 382 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 383 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 0f8c9768 WD |
384 | #endif |
| 385 | ||
| 386 | /*----------------------------------------------------------------------- | |
| 387 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
| 388 | *----------------------------------------------------------------------- | |
| 389 | * HID0 also contains cache control - initially enable both caches and | |
| 390 | * invalidate contents, then the final state leaves only the instruction | |
| 391 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
| 392 | * but Soft reset does not. | |
| 393 | * | |
| 394 | * HID1 has only read-only information - nothing to set. | |
| 395 | */ | |
| 6d0f6bcf | 396 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
| 8bde7f77 | 397 | HID0_IFEM|HID0_ABE) |
| 6d0f6bcf JCPV |
398 | #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) |
| 399 | #define CONFIG_SYS_HID2 0 | |
| 0f8c9768 WD |
400 | |
| 401 | /*----------------------------------------------------------------------- | |
| 402 | * RMR - Reset Mode Register 5-5 | |
| 403 | *----------------------------------------------------------------------- | |
| 404 | * turn on Checkstop Reset Enable | |
| 405 | */ | |
| 6d0f6bcf | 406 | #define CONFIG_SYS_RMR RMR_CSRE |
| 0f8c9768 WD |
407 | |
| 408 | /*----------------------------------------------------------------------- | |
| 409 | * BCR - Bus Configuration 4-25 | |
| 410 | *----------------------------------------------------------------------- | |
| 411 | */ | |
| 412 | #ifdef CONFIG_BUSMODE_60x | |
| 6d0f6bcf | 413 | #define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ |
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414 | BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ |
| 415 | #else | |
| 416 | #define BCR_APD01 0x10000000 | |
| 6d0f6bcf | 417 | #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
| 0f8c9768 WD |
418 | #endif |
| 419 | ||
| 420 | /*----------------------------------------------------------------------- | |
| 421 | * SIUMCR - SIU Module Configuration 4-31 | |
| 422 | *----------------------------------------------------------------------- | |
| 423 | */ | |
| 424 | #if 0 | |
| 6d0f6bcf | 425 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) |
| 0f8c9768 | 426 | #else |
| 6d0f6bcf | 427 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) |
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428 | #endif |
| 429 | ||
| 430 | ||
| 431 | /*----------------------------------------------------------------------- | |
| 432 | * SYPCR - System Protection Control 4-35 | |
| 433 | * SYPCR can only be written once after reset! | |
| 434 | *----------------------------------------------------------------------- | |
| 435 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
| 436 | */ | |
| 437 | #if defined(CONFIG_WATCHDOG) | |
| 6d0f6bcf | 438 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
| 8bde7f77 | 439 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
| 0f8c9768 | 440 | #else |
| 6d0f6bcf | 441 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
| 8bde7f77 | 442 | SYPCR_SWRI|SYPCR_SWP) |
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443 | #endif /* CONFIG_WATCHDOG */ |
| 444 | ||
| 445 | /*----------------------------------------------------------------------- | |
| 446 | * TMCNTSC - Time Counter Status and Control 4-40 | |
| 447 | *----------------------------------------------------------------------- | |
| 448 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
| 449 | * and enable Time Counter | |
| 450 | */ | |
| 6d0f6bcf | 451 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
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452 | |
| 453 | /*----------------------------------------------------------------------- | |
| 454 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
| 455 | *----------------------------------------------------------------------- | |
| 456 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
| 457 | * Periodic timer | |
| 458 | */ | |
| 6d0f6bcf | 459 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
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460 | |
| 461 | /*----------------------------------------------------------------------- | |
| 462 | * SCCR - System Clock Control 9-8 | |
| 463 | *----------------------------------------------------------------------- | |
| 464 | * Ensure DFBRG is Divide by 16 | |
| 465 | */ | |
| 6d0f6bcf | 466 | #define CONFIG_SYS_SCCR 0 |
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467 | |
| 468 | /*----------------------------------------------------------------------- | |
| 469 | * RCCR - RISC Controller Configuration 13-7 | |
| 470 | *----------------------------------------------------------------------- | |
| 471 | */ | |
| 6d0f6bcf | 472 | #define CONFIG_SYS_RCCR 0 |
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473 | |
| 474 | /* | |
| 475 | * Init Memory Controller: | |
| 476 | * | |
| 477 | * Bank Bus Machine PortSz Device | |
| 478 | * ---- --- ------- ------ ------ | |
| 479 | * 0 60x GPCM 64 bit FLASH | |
| 480 | * 1 60x SDRAM 64 bit SDRAM | |
| 481 | * 2 Local SDRAM 32 bit SDRAM | |
| 482 | * | |
| 483 | */ | |
| 484 | ||
| 485 | /* Initialize SDRAM on local bus | |
| 486 | */ | |
| 6d0f6bcf | 487 | #define CONFIG_SYS_INIT_LOCAL_SDRAM |
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488 | |
| 489 | #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
| 490 | ||
| 491 | /* Minimum mask to separate preliminary | |
| 492 | * address ranges for CS[0:2] | |
| 493 | */ | |
| 6d0f6bcf JCPV |
494 | #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ |
| 495 | #define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ | |
| 0f8c9768 | 496 | |
| 6d0f6bcf | 497 | #define CONFIG_SYS_MPTPR 0x4000 |
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498 | |
| 499 | /*----------------------------------------------------------------------------- | |
| 500 | * Address for Mode Register Set (MRS) command | |
| 501 | *----------------------------------------------------------------------------- | |
| 502 | * In fact, the address is rather configuration data presented to the SDRAM on | |
| 503 | * its address lines. Because the address lines may be mux'ed externally either | |
| 504 | * for 8 column or 9 column devices, some bits appear twice in the 8260's | |
| 505 | * address: | |
| 506 | * | |
| 507 | * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | | |
| 508 | * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | | |
| 509 | * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | | |
| 510 | * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | | |
| 511 | * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | | |
| 512 | *----------------------------------------------------------------------------- | |
| 513 | */ | |
| 6d0f6bcf | 514 | #define CONFIG_SYS_MRS_OFFS 0x00000110 |
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515 | |
| 516 | ||
| 517 | /* Bank 0 - FLASH | |
| 518 | */ | |
| 6d0f6bcf | 519 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
| 8bde7f77 WD |
520 | BRx_PS_64 |\ |
| 521 | BRx_MS_GPCM_P |\ | |
| 522 | BRx_V) | |
| 0f8c9768 | 523 | |
| 6d0f6bcf | 524 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
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525 | ORxG_CSNT |\ |
| 526 | ORxG_ACS_DIV1 |\ | |
| 527 | ORxG_SCY_3_CLK |\ | |
| 528 | ORxG_EHTR |\ | |
| 529 | ORxG_TRLX) | |
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530 | |
| 531 | /* SDRAM on TQM8260 can have either 8 or 9 columns. | |
| 532 | * The number affects configuration values. | |
| 533 | */ | |
| 534 | ||
| 535 | /* Bank 1 - 60x bus SDRAM | |
| 536 | */ | |
| 6d0f6bcf JCPV |
537 | #define CONFIG_SYS_PSRT 0x20 |
| 538 | #define CONFIG_SYS_LSRT 0x20 | |
| 539 | #ifndef CONFIG_SYS_RAMBOOT | |
| 540 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ | |
| 8bde7f77 WD |
541 | BRx_PS_64 |\ |
| 542 | BRx_MS_SDRAM_P |\ | |
| 543 | BRx_V) | |
| 0f8c9768 | 544 | |
| 6d0f6bcf | 545 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL |
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546 | |
| 547 | ||
| 548 | /* SDRAM initialization values for 8-column chips | |
| 549 | */ | |
| 6d0f6bcf | 550 | #define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
| 8bde7f77 WD |
551 | ORxS_BPD_4 |\ |
| 552 | ORxS_ROWST_PBI1_A7 |\ | |
| 553 | ORxS_NUMR_12) | |
| 0f8c9768 | 554 | |
| 6d0f6bcf | 555 | #define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ |
| 8bde7f77 WD |
556 | PSDMR_SDAM_A15_IS_A5 |\ |
| 557 | PSDMR_BSMA_A12_A14 |\ | |
| 558 | PSDMR_SDA10_PBI1_A8 |\ | |
| 559 | PSDMR_RFRC_7_CLK |\ | |
| 560 | PSDMR_PRETOACT_2W |\ | |
| 561 | PSDMR_ACTTORW_2W |\ | |
| 562 | PSDMR_LDOTOPRE_1C |\ | |
| 563 | PSDMR_WRC_2C |\ | |
| 564 | PSDMR_EAMUX |\ | |
| 565 | PSDMR_CL_2) | |
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566 | |
| 567 | /* SDRAM initialization values for 9-column chips | |
| 568 | */ | |
| 6d0f6bcf | 569 | #define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
| 8bde7f77 WD |
570 | ORxS_BPD_4 |\ |
| 571 | ORxS_ROWST_PBI1_A5 |\ | |
| 572 | ORxS_NUMR_13) | |
| 0f8c9768 | 573 | |
| 6d0f6bcf | 574 | #define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ |
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575 | PSDMR_SDAM_A16_IS_A5 |\ |
| 576 | PSDMR_BSMA_A12_A14 |\ | |
| 577 | PSDMR_SDA10_PBI1_A7 |\ | |
| 578 | PSDMR_RFRC_7_CLK |\ | |
| 579 | PSDMR_PRETOACT_2W |\ | |
| 580 | PSDMR_ACTTORW_2W |\ | |
| 581 | PSDMR_LDOTOPRE_1C |\ | |
| 582 | PSDMR_WRC_2C |\ | |
| 583 | PSDMR_EAMUX |\ | |
| 584 | PSDMR_CL_2) | |
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585 | |
| 586 | /* Bank 2 - Local bus SDRAM | |
| 587 | */ | |
| 6d0f6bcf JCPV |
588 | #ifdef CONFIG_SYS_INIT_LOCAL_SDRAM |
| 589 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ | |
| 8bde7f77 WD |
590 | BRx_PS_32 |\ |
| 591 | BRx_MS_SDRAM_L |\ | |
| 592 | BRx_V) | |
| 0f8c9768 | 593 | |
| 6d0f6bcf | 594 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL |
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595 | |
| 596 | #define SDRAM_BASE2_PRELIM 0x80000000 | |
| 597 | ||
| 598 | /* SDRAM initialization values for 8-column chips | |
| 599 | */ | |
| 6d0f6bcf | 600 | #define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
| 8bde7f77 WD |
601 | ORxS_BPD_4 |\ |
| 602 | ORxS_ROWST_PBI1_A8 |\ | |
| 603 | ORxS_NUMR_12) | |
| 0f8c9768 | 604 | |
| 6d0f6bcf | 605 | #define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\ |
| 8bde7f77 WD |
606 | PSDMR_SDAM_A15_IS_A5 |\ |
| 607 | PSDMR_BSMA_A13_A15 |\ | |
| 608 | PSDMR_SDA10_PBI1_A9 |\ | |
| 609 | PSDMR_RFRC_7_CLK |\ | |
| 610 | PSDMR_PRETOACT_2W |\ | |
| 611 | PSDMR_ACTTORW_2W |\ | |
| 612 | PSDMR_BL |\ | |
| 613 | PSDMR_LDOTOPRE_1C |\ | |
| 614 | PSDMR_WRC_2C |\ | |
| 615 | PSDMR_CL_2) | |
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616 | |
| 617 | /* SDRAM initialization values for 9-column chips | |
| 618 | */ | |
| 6d0f6bcf | 619 | #define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
| 8bde7f77 WD |
620 | ORxS_BPD_4 |\ |
| 621 | ORxS_ROWST_PBI1_A6 |\ | |
| 622 | ORxS_NUMR_13) | |
| 0f8c9768 | 623 | |
| 6d0f6bcf | 624 | #define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\ |
| 8bde7f77 WD |
625 | PSDMR_SDAM_A16_IS_A5 |\ |
| 626 | PSDMR_BSMA_A13_A15 |\ | |
| 627 | PSDMR_SDA10_PBI1_A8 |\ | |
| 628 | PSDMR_RFRC_7_CLK |\ | |
| 629 | PSDMR_PRETOACT_2W |\ | |
| 630 | PSDMR_ACTTORW_2W |\ | |
| 631 | PSDMR_BL |\ | |
| 632 | PSDMR_LDOTOPRE_1C |\ | |
| 633 | PSDMR_WRC_2C |\ | |
| 634 | PSDMR_CL_2) | |
| 0f8c9768 | 635 | |
| 6d0f6bcf | 636 | #endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ |
| 0f8c9768 | 637 | |
| 6d0f6bcf | 638 | #endif /* CONFIG_SYS_RAMBOOT */ |
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639 | |
| 640 | #endif /* __CONFIG_H */ |