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0f8c9768 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * Imported from global configuration: | |
33 | * CONFIG_L2_CACHE | |
34 | * CONFIG_266MHz | |
35 | * CONFIG_300MHz | |
36 | */ | |
37 | ||
38 | /* | |
39 | * High Level Configuration Options | |
40 | * (easy to change) | |
41 | */ | |
42 | ||
43 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ | |
44 | ||
45 | #if 0 | |
46 | #define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ | |
47 | #else | |
48 | #define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ | |
49 | #endif | |
50 | ||
51 | /* Define 60x busmode only if your TQM8260 has L2 cache! */ | |
52 | #ifdef CONFIG_L2_CACHE | |
53 | # define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */ | |
54 | #else | |
55 | # undef CONFIG_BUSMODE_60x /* bus mode: 8260 */ | |
56 | #endif | |
57 | ||
58 | /* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */ | |
59 | #ifdef CONFIG_300MHz | |
60 | # define CONFIG_BUSMODE_60x | |
61 | #endif | |
62 | ||
63 | #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ | |
64 | ||
65 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
66 | ||
67 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
68 | ||
69 | #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" | |
70 | ||
71 | #undef CONFIG_BOOTARGS | |
72 | #define CONFIG_BOOTCOMMAND \ | |
73 | "bootp; " \ | |
74 | "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ | |
75 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ | |
76 | "bootm" | |
77 | ||
78 | /* enable I2C and select the hardware/software driver */ | |
79 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
80 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
81 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
82 | #define CFG_I2C_SLAVE 0x7F | |
83 | ||
84 | /* | |
85 | * Software (bit-bang) I2C driver configuration | |
86 | */ | |
87 | ||
88 | /* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */ | |
89 | #if (CONFIG_TQM8260 <= 100) | |
90 | ||
91 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
92 | #define I2C_ACTIVE (iop->pdir |= 0x00020000) | |
93 | #define I2C_TRISTATE (iop->pdir &= ~0x00020000) | |
94 | #define I2C_READ ((iop->pdat & 0x00020000) != 0) | |
95 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \ | |
96 | else iop->pdat &= ~0x00020000 | |
97 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \ | |
98 | else iop->pdat &= ~0x00010000 | |
99 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
100 | ||
101 | #else | |
102 | ||
103 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
104 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
105 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
106 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
107 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
108 | else iop->pdat &= ~0x00010000 | |
109 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
110 | else iop->pdat &= ~0x00020000 | |
111 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
112 | #endif | |
113 | ||
114 | #define CFG_I2C_EEPROM_ADDR 0x50 | |
115 | #define CFG_I2C_EEPROM_ADDR_LEN 2 | |
116 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 | |
117 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
118 | ||
119 | #define CONFIG_I2C_X | |
120 | ||
121 | /* | |
122 | * select serial console configuration | |
123 | * | |
124 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
125 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
126 | * for SCC). | |
127 | * | |
128 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
129 | * defined elsewhere (for example, on the cogent platform, there are serial | |
130 | * ports on the motherboard which are used for the serial console - see | |
131 | * cogent/cma101/serial.[ch]). | |
132 | */ | |
133 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
134 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
135 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
136 | #ifdef CONFIG_82xx_CONS_SMC1 | |
137 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
138 | #endif | |
139 | #ifdef CONFIG_82xx_CONS_SMC2 | |
140 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
141 | #endif | |
142 | ||
143 | #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ | |
144 | #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ | |
145 | #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ | |
146 | ||
147 | /* | |
148 | * select ethernet configuration | |
149 | * | |
150 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
151 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
152 | * for FCC) | |
153 | * | |
154 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
155 | * defined elsewhere (as for the console), or CFG_CMD_NET must be removed | |
156 | * from CONFIG_COMMANDS to remove support for networking. | |
157 | * | |
158 | * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the | |
159 | * X.29 connector, and FCC2 is hardwired to the X.1 connector) | |
160 | */ | |
161 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
162 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
163 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
164 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
165 | ||
166 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) | |
167 | ||
168 | /* | |
169 | * - RX clk is CLK11 | |
170 | * - TX clk is CLK12 | |
171 | */ | |
172 | # define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) | |
173 | ||
174 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
175 | ||
176 | /* | |
177 | * - Rx-CLK is CLK13 | |
178 | * - Tx-CLK is CLK14 | |
179 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
180 | * - Enable Full Duplex in FSMR | |
181 | */ | |
182 | # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) | |
183 | # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
184 | # define CFG_CPMFCR_RAMTYPE 0 | |
185 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
186 | ||
187 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
188 | ||
189 | ||
190 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
191 | #ifndef CONFIG_300MHz | |
192 | #define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
193 | #else | |
194 | #define CONFIG_8260_CLKIN 83333000 /* in Hz */ | |
195 | #endif | |
196 | ||
197 | #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) | |
198 | #define CONFIG_BAUDRATE 230400 | |
199 | #else | |
200 | #define CONFIG_BAUDRATE 9600 | |
201 | #endif | |
202 | ||
203 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
204 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
205 | ||
206 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
207 | ||
208 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) | |
209 | ||
210 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ | |
211 | CFG_CMD_I2C | \ | |
212 | CFG_CMD_EEPROM) | |
213 | ||
214 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
215 | #include <cmd_confdefs.h> | |
216 | ||
217 | /* | |
218 | * Miscellaneous configurable options | |
219 | */ | |
220 | #define CFG_LONGHELP /* undef to save memory */ | |
221 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
222 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
223 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
224 | #else | |
225 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
226 | #endif | |
227 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
228 | #define CFG_MAXARGS 16 /* max number of command args */ | |
229 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
230 | ||
231 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
232 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
233 | ||
234 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
235 | ||
236 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
237 | ||
238 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
239 | ||
240 | #define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ | |
241 | ||
242 | /* | |
243 | * For booting Linux, the board info and command line data | |
244 | * have to be in the first 8 MB of memory, since this is | |
245 | * the maximum mapped by the Linux kernel during initialization. | |
246 | */ | |
247 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
248 | ||
249 | ||
250 | /* What should the base address of the main FLASH be and how big is | |
251 | * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk | |
252 | * The main FLASH is whichever is connected to *CS0. | |
253 | */ | |
254 | #define CFG_FLASH0_BASE 0x40000000 | |
255 | #define CFG_FLASH1_BASE 0x60000000 | |
256 | #define CFG_FLASH0_SIZE 32 | |
257 | #define CFG_FLASH1_SIZE 32 | |
258 | ||
259 | /* Flash bank size (for preliminary settings) | |
260 | */ | |
261 | #define CFG_FLASH_SIZE CFG_FLASH0_SIZE | |
262 | ||
263 | /*----------------------------------------------------------------------- | |
264 | * FLASH organization | |
265 | */ | |
266 | #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
267 | #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
268 | ||
269 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
270 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
271 | ||
272 | #if 0 | |
273 | /* Start port with environment in flash; switch to EEPROM later */ | |
274 | #define CFG_ENV_IS_IN_FLASH 1 | |
275 | #define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) | |
276 | #define CFG_ENV_SIZE 0x40000 | |
277 | #define CFG_ENV_SECT_SIZE 0x40000 | |
278 | #else | |
279 | /* Final version: environment in EEPROM */ | |
280 | #define CFG_ENV_IS_IN_EEPROM 1 | |
281 | #define CFG_ENV_OFFSET 0 | |
282 | #define CFG_ENV_SIZE 2048 | |
283 | #endif | |
284 | ||
285 | /*----------------------------------------------------------------------- | |
286 | * Hardware Information Block | |
287 | */ | |
288 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
289 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
290 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
291 | ||
292 | /*----------------------------------------------------------------------- | |
293 | * Hard Reset Configuration Words | |
294 | * | |
295 | * if you change bits in the HRCW, you must also change the CFG_* | |
296 | * defines for the various registers affected by the HRCW e.g. changing | |
297 | * HRCW_DPPCxx requires you to also change CFG_SIUMCR. | |
298 | */ | |
299 | #if defined(CONFIG_266MHz) | |
300 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ | |
301 | HRCW_MODCK_H0111) | |
302 | #elif defined(CONFIG_300MHz) | |
303 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ | |
304 | HRCW_MODCK_H0110) | |
305 | #else | |
306 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) | |
307 | #endif | |
308 | ||
309 | /* no slaves so just fill with zeros */ | |
310 | #define CFG_HRCW_SLAVE1 0 | |
311 | #define CFG_HRCW_SLAVE2 0 | |
312 | #define CFG_HRCW_SLAVE3 0 | |
313 | #define CFG_HRCW_SLAVE4 0 | |
314 | #define CFG_HRCW_SLAVE5 0 | |
315 | #define CFG_HRCW_SLAVE6 0 | |
316 | #define CFG_HRCW_SLAVE7 0 | |
317 | ||
318 | /*----------------------------------------------------------------------- | |
319 | * Internal Memory Mapped Register | |
320 | */ | |
321 | #define CFG_IMMR 0xFFF00000 | |
322 | ||
323 | /*----------------------------------------------------------------------- | |
324 | * Definitions for initial stack pointer and data area (in DPRAM) | |
325 | */ | |
326 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
327 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
328 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ | |
329 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
330 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
331 | ||
332 | /*----------------------------------------------------------------------- | |
333 | * Start addresses for the final memory configuration | |
334 | * (Set up by the startup code) | |
335 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
336 | * | |
337 | * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM | |
338 | * is mapped at SDRAM_BASE2_PRELIM. | |
339 | */ | |
340 | #define CFG_SDRAM_BASE 0x00000000 | |
341 | #define CFG_FLASH_BASE CFG_FLASH0_BASE | |
342 | #define CFG_MONITOR_BASE TEXT_BASE | |
343 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
344 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
345 | ||
346 | /* | |
347 | * Internal Definitions | |
348 | * | |
349 | * Boot Flags | |
350 | */ | |
351 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
352 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
353 | ||
354 | ||
355 | /*----------------------------------------------------------------------- | |
356 | * Cache Configuration | |
357 | */ | |
358 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ | |
359 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
360 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
361 | #endif | |
362 | ||
363 | /*----------------------------------------------------------------------- | |
364 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
365 | *----------------------------------------------------------------------- | |
366 | * HID0 also contains cache control - initially enable both caches and | |
367 | * invalidate contents, then the final state leaves only the instruction | |
368 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
369 | * but Soft reset does not. | |
370 | * | |
371 | * HID1 has only read-only information - nothing to set. | |
372 | */ | |
373 | #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ | |
374 | HID0_IFEM|HID0_ABE) | |
375 | #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) | |
376 | #define CFG_HID2 0 | |
377 | ||
378 | /*----------------------------------------------------------------------- | |
379 | * RMR - Reset Mode Register 5-5 | |
380 | *----------------------------------------------------------------------- | |
381 | * turn on Checkstop Reset Enable | |
382 | */ | |
383 | #define CFG_RMR RMR_CSRE | |
384 | ||
385 | /*----------------------------------------------------------------------- | |
386 | * BCR - Bus Configuration 4-25 | |
387 | *----------------------------------------------------------------------- | |
388 | */ | |
389 | #ifdef CONFIG_BUSMODE_60x | |
390 | #define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ | |
391 | BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ | |
392 | #else | |
393 | #define BCR_APD01 0x10000000 | |
394 | #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ | |
395 | #endif | |
396 | ||
397 | /*----------------------------------------------------------------------- | |
398 | * SIUMCR - SIU Module Configuration 4-31 | |
399 | *----------------------------------------------------------------------- | |
400 | */ | |
401 | #if 0 | |
402 | #define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) | |
403 | #else | |
404 | #define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) | |
405 | #endif | |
406 | ||
407 | ||
408 | /*----------------------------------------------------------------------- | |
409 | * SYPCR - System Protection Control 4-35 | |
410 | * SYPCR can only be written once after reset! | |
411 | *----------------------------------------------------------------------- | |
412 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
413 | */ | |
414 | #if defined(CONFIG_WATCHDOG) | |
415 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
416 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) | |
417 | #else | |
418 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
419 | SYPCR_SWRI|SYPCR_SWP) | |
420 | #endif /* CONFIG_WATCHDOG */ | |
421 | ||
422 | /*----------------------------------------------------------------------- | |
423 | * TMCNTSC - Time Counter Status and Control 4-40 | |
424 | *----------------------------------------------------------------------- | |
425 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
426 | * and enable Time Counter | |
427 | */ | |
428 | #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
429 | ||
430 | /*----------------------------------------------------------------------- | |
431 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
432 | *----------------------------------------------------------------------- | |
433 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
434 | * Periodic timer | |
435 | */ | |
436 | #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
437 | ||
438 | /*----------------------------------------------------------------------- | |
439 | * SCCR - System Clock Control 9-8 | |
440 | *----------------------------------------------------------------------- | |
441 | * Ensure DFBRG is Divide by 16 | |
442 | */ | |
443 | #define CFG_SCCR 0 | |
444 | ||
445 | /*----------------------------------------------------------------------- | |
446 | * RCCR - RISC Controller Configuration 13-7 | |
447 | *----------------------------------------------------------------------- | |
448 | */ | |
449 | #define CFG_RCCR 0 | |
450 | ||
451 | /* | |
452 | * Init Memory Controller: | |
453 | * | |
454 | * Bank Bus Machine PortSz Device | |
455 | * ---- --- ------- ------ ------ | |
456 | * 0 60x GPCM 64 bit FLASH | |
457 | * 1 60x SDRAM 64 bit SDRAM | |
458 | * 2 Local SDRAM 32 bit SDRAM | |
459 | * | |
460 | */ | |
461 | ||
462 | /* Initialize SDRAM on local bus | |
463 | */ | |
464 | #define CFG_INIT_LOCAL_SDRAM | |
465 | ||
466 | #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
467 | ||
468 | /* Minimum mask to separate preliminary | |
469 | * address ranges for CS[0:2] | |
470 | */ | |
471 | #define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ | |
472 | #define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ | |
473 | ||
474 | #define CFG_MPTPR 0x4000 | |
475 | ||
476 | /*----------------------------------------------------------------------------- | |
477 | * Address for Mode Register Set (MRS) command | |
478 | *----------------------------------------------------------------------------- | |
479 | * In fact, the address is rather configuration data presented to the SDRAM on | |
480 | * its address lines. Because the address lines may be mux'ed externally either | |
481 | * for 8 column or 9 column devices, some bits appear twice in the 8260's | |
482 | * address: | |
483 | * | |
484 | * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | | |
485 | * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | | |
486 | * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | | |
487 | * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | | |
488 | * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | | |
489 | *----------------------------------------------------------------------------- | |
490 | */ | |
491 | #define CFG_MRS_OFFS 0x00000110 | |
492 | ||
493 | ||
494 | /* Bank 0 - FLASH | |
495 | */ | |
496 | #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ | |
497 | BRx_PS_64 |\ | |
498 | BRx_MS_GPCM_P |\ | |
499 | BRx_V) | |
500 | ||
501 | #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ | |
502 | ORxG_CSNT |\ | |
503 | ORxG_ACS_DIV1 |\ | |
504 | ORxG_SCY_3_CLK |\ | |
505 | ORxG_EHTR |\ | |
506 | ORxG_TRLX) | |
507 | ||
508 | /* SDRAM on TQM8260 can have either 8 or 9 columns. | |
509 | * The number affects configuration values. | |
510 | */ | |
511 | ||
512 | /* Bank 1 - 60x bus SDRAM | |
513 | */ | |
514 | #define CFG_PSRT 0x20 | |
515 | #define CFG_LSRT 0x20 | |
516 | #ifndef CFG_RAMBOOT | |
517 | #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ | |
518 | BRx_PS_64 |\ | |
519 | BRx_MS_SDRAM_P |\ | |
520 | BRx_V) | |
521 | ||
522 | #define CFG_OR1_PRELIM CFG_OR1_8COL | |
523 | ||
524 | ||
525 | /* SDRAM initialization values for 8-column chips | |
526 | */ | |
527 | #define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ | |
528 | ORxS_BPD_4 |\ | |
529 | ORxS_ROWST_PBI1_A7 |\ | |
530 | ORxS_NUMR_12) | |
531 | ||
532 | #define CFG_PSDMR_8COL (PSDMR_PBI |\ | |
533 | PSDMR_SDAM_A15_IS_A5 |\ | |
534 | PSDMR_BSMA_A12_A14 |\ | |
535 | PSDMR_SDA10_PBI1_A8 |\ | |
536 | PSDMR_RFRC_7_CLK |\ | |
537 | PSDMR_PRETOACT_2W |\ | |
538 | PSDMR_ACTTORW_2W |\ | |
539 | PSDMR_LDOTOPRE_1C |\ | |
540 | PSDMR_WRC_2C |\ | |
541 | PSDMR_EAMUX |\ | |
542 | PSDMR_CL_2) | |
543 | ||
544 | /* SDRAM initialization values for 9-column chips | |
545 | */ | |
546 | #define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ | |
547 | ORxS_BPD_4 |\ | |
548 | ORxS_ROWST_PBI1_A5 |\ | |
549 | ORxS_NUMR_13) | |
550 | ||
551 | #define CFG_PSDMR_9COL (PSDMR_PBI |\ | |
552 | PSDMR_SDAM_A16_IS_A5 |\ | |
553 | PSDMR_BSMA_A12_A14 |\ | |
554 | PSDMR_SDA10_PBI1_A7 |\ | |
555 | PSDMR_RFRC_7_CLK |\ | |
556 | PSDMR_PRETOACT_2W |\ | |
557 | PSDMR_ACTTORW_2W |\ | |
558 | PSDMR_LDOTOPRE_1C |\ | |
559 | PSDMR_WRC_2C |\ | |
560 | PSDMR_EAMUX |\ | |
561 | PSDMR_CL_2) | |
562 | ||
563 | /* Bank 2 - Local bus SDRAM | |
564 | */ | |
565 | #ifdef CFG_INIT_LOCAL_SDRAM | |
566 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ | |
567 | BRx_PS_32 |\ | |
568 | BRx_MS_SDRAM_L |\ | |
569 | BRx_V) | |
570 | ||
571 | #define CFG_OR2_PRELIM CFG_OR2_8COL | |
572 | ||
573 | #define SDRAM_BASE2_PRELIM 0x80000000 | |
574 | ||
575 | /* SDRAM initialization values for 8-column chips | |
576 | */ | |
577 | #define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ | |
578 | ORxS_BPD_4 |\ | |
579 | ORxS_ROWST_PBI1_A8 |\ | |
580 | ORxS_NUMR_12) | |
581 | ||
582 | #define CFG_LSDMR_8COL (PSDMR_PBI |\ | |
583 | PSDMR_SDAM_A15_IS_A5 |\ | |
584 | PSDMR_BSMA_A13_A15 |\ | |
585 | PSDMR_SDA10_PBI1_A9 |\ | |
586 | PSDMR_RFRC_7_CLK |\ | |
587 | PSDMR_PRETOACT_2W |\ | |
588 | PSDMR_ACTTORW_2W |\ | |
589 | PSDMR_BL |\ | |
590 | PSDMR_LDOTOPRE_1C |\ | |
591 | PSDMR_WRC_2C |\ | |
592 | PSDMR_CL_2) | |
593 | ||
594 | /* SDRAM initialization values for 9-column chips | |
595 | */ | |
596 | #define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ | |
597 | ORxS_BPD_4 |\ | |
598 | ORxS_ROWST_PBI1_A6 |\ | |
599 | ORxS_NUMR_13) | |
600 | ||
601 | #define CFG_LSDMR_9COL (PSDMR_PBI |\ | |
602 | PSDMR_SDAM_A16_IS_A5 |\ | |
603 | PSDMR_BSMA_A13_A15 |\ | |
604 | PSDMR_SDA10_PBI1_A8 |\ | |
605 | PSDMR_RFRC_7_CLK |\ | |
606 | PSDMR_PRETOACT_2W |\ | |
607 | PSDMR_ACTTORW_2W |\ | |
608 | PSDMR_BL |\ | |
609 | PSDMR_LDOTOPRE_1C |\ | |
610 | PSDMR_WRC_2C |\ | |
611 | PSDMR_CL_2) | |
612 | ||
613 | #endif /* CFG_INIT_LOCAL_SDRAM */ | |
614 | ||
615 | #endif /* CFG_RAMBOOT */ | |
616 | ||
617 | #endif /* __CONFIG_H */ |