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Commit | Line | Data |
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0f8c9768 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2001-2005 |
0f8c9768 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
0f8c9768 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * Imported from global configuration: | |
27b207fd WD |
17 | * CONFIG_MPC8255 |
18 | * CONFIG_MPC8265 | |
19 | * CONFIG_200MHz | |
0f8c9768 WD |
20 | * CONFIG_266MHz |
21 | * CONFIG_300MHz | |
27b207fd WD |
22 | * CONFIG_L2_CACHE |
23 | * CONFIG_BUSMODE_60x | |
0f8c9768 WD |
24 | */ |
25 | ||
26 | /* | |
27 | * High Level Configuration Options | |
28 | * (easy to change) | |
29 | */ | |
30 | ||
2ae18241 WD |
31 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
32 | ||
0f8c9768 WD |
33 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ |
34 | ||
35 | #if 0 | |
36 | #define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ | |
37 | #else | |
38 | #define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ | |
39 | #endif | |
40 | ||
9c4c5ae3 JL |
41 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
42 | ||
0f8c9768 WD |
43 | #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ |
44 | ||
45 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
46 | ||
ae3af05e WD |
47 | #define CONFIG_BOOTCOUNT_LIMIT |
48 | ||
055b12f2 | 49 | #define CONFIG_BAUDRATE 115200 |
0f8c9768 | 50 | |
32bf3d14 | 51 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
0f8c9768 WD |
52 | |
53 | #undef CONFIG_BOOTARGS | |
506f0441 WD |
54 | |
55 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
ae3af05e | 56 | "netdev=eth0\0" \ |
506f0441 | 57 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b | 58 | "nfsroot=${serverip}:${rootpath}\0" \ |
506f0441 | 59 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
60 | "addip=setenv bootargs ${bootargs} " \ |
61 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
62 | ":${hostname}:${netdev}:off panic=1\0" \ | |
506f0441 | 63 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 64 | "bootm ${kernel_addr}\0" \ |
506f0441 | 65 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
66 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
67 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
055b12f2 WD |
68 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
69 | "bootfile=tqm8260/uImage\0" \ | |
86b4bafd WD |
70 | "kernel_addr=400C0000\0" \ |
71 | "ramdisk_addr=40240000\0" \ | |
506f0441 WD |
72 | "" |
73 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
0f8c9768 WD |
74 | |
75 | /* enable I2C and select the hardware/software driver */ | |
ea818dbb HS |
76 | #define CONFIG_SYS_I2C |
77 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
78 | #define CONFIG_SYS_I2C_SOFT_SPEED 400000 | |
79 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F | |
0f8c9768 WD |
80 | |
81 | /* | |
82 | * Software (bit-bang) I2C driver configuration | |
83 | */ | |
84 | ||
85 | /* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */ | |
86 | #if (CONFIG_TQM8260 <= 100) | |
87 | ||
88 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
89 | #define I2C_ACTIVE (iop->pdir |= 0x00020000) | |
90 | #define I2C_TRISTATE (iop->pdir &= ~0x00020000) | |
91 | #define I2C_READ ((iop->pdat & 0x00020000) != 0) | |
92 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \ | |
93 | else iop->pdat &= ~0x00020000 | |
94 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \ | |
95 | else iop->pdat &= ~0x00010000 | |
96 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
97 | ||
98 | #else | |
99 | ||
100 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
101 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
102 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
103 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
104 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
105 | else iop->pdat &= ~0x00010000 | |
106 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
107 | else iop->pdat &= ~0x00020000 | |
108 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
109 | #endif | |
110 | ||
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
112 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
113 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
114 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
0f8c9768 WD |
115 | |
116 | #define CONFIG_I2C_X | |
117 | ||
118 | /* | |
119 | * select serial console configuration | |
120 | * | |
121 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
122 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
123 | * for SCC). | |
124 | * | |
125 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
126 | * defined elsewhere (for example, on the cogent platform, there are serial | |
127 | * ports on the motherboard which are used for the serial console - see | |
128 | * cogent/cma101/serial.[ch]). | |
129 | */ | |
130 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
131 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
132 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
133 | #ifdef CONFIG_82xx_CONS_SMC1 | |
134 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
135 | #endif | |
136 | #ifdef CONFIG_82xx_CONS_SMC2 | |
137 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
138 | #endif | |
139 | ||
140 | #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ | |
141 | #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ | |
142 | #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ | |
143 | ||
144 | /* | |
145 | * select ethernet configuration | |
146 | * | |
147 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
148 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
149 | * for FCC) | |
150 | * | |
151 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 152 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
0f8c9768 WD |
153 | * |
154 | * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the | |
155 | * X.29 connector, and FCC2 is hardwired to the X.1 connector) | |
156 | */ | |
157 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
158 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
159 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
160 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
161 | ||
162 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) | |
163 | ||
164 | /* | |
165 | * - RX clk is CLK11 | |
166 | * - TX clk is CLK12 | |
167 | */ | |
d4590da4 | 168 | # define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) |
0f8c9768 WD |
169 | |
170 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
171 | ||
172 | /* | |
173 | * - Rx-CLK is CLK13 | |
174 | * - Tx-CLK is CLK14 | |
175 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
176 | * - Enable Full Duplex in FSMR | |
177 | */ | |
d4590da4 MF |
178 | # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
179 | # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
6d0f6bcf JCPV |
180 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
181 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
0f8c9768 WD |
182 | |
183 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
184 | ||
185 | ||
186 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
27b207fd | 187 | #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) |
7aa78614 | 188 | # define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
27b207fd | 189 | #else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */ |
7aa78614 WD |
190 | # ifndef CONFIG_300MHz |
191 | # define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
192 | # else | |
193 | # define CONFIG_8260_CLKIN 83333000 /* in Hz */ | |
194 | # endif | |
195 | #endif /* CONFIG_MPC8255 */ | |
0f8c9768 | 196 | |
0f8c9768 | 197 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 198 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
0f8c9768 WD |
199 | |
200 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
201 | ||
414eec35 WD |
202 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
203 | ||
37d4bb70 JL |
204 | |
205 | /* | |
206 | * BOOTP options | |
207 | */ | |
208 | #define CONFIG_BOOTP_SUBNETMASK | |
209 | #define CONFIG_BOOTP_GATEWAY | |
210 | #define CONFIG_BOOTP_HOSTNAME | |
211 | #define CONFIG_BOOTP_BOOTPATH | |
212 | #define CONFIG_BOOTP_BOOTFILESIZE | |
0f8c9768 | 213 | |
0f8c9768 | 214 | |
2694690e JL |
215 | /* |
216 | * Command line configuration. | |
217 | */ | |
218 | #include <config_cmd_default.h> | |
219 | ||
220 | #define CONFIG_CMD_DHCP | |
221 | #define CONFIG_CMD_I2C | |
222 | #define CONFIG_CMD_EEPROM | |
223 | #define CONFIG_CMD_NFS | |
224 | #define CONFIG_CMD_SNTP | |
225 | ||
0f8c9768 WD |
226 | |
227 | /* | |
228 | * Miscellaneous configurable options | |
229 | */ | |
6d0f6bcf | 230 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
2751a95a WD |
231 | |
232 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
6d0f6bcf | 233 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
2751a95a | 234 | |
2694690e | 235 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 236 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0f8c9768 | 237 | #else |
6d0f6bcf | 238 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0f8c9768 | 239 | #endif |
6d0f6bcf JCPV |
240 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
241 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
242 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0f8c9768 | 243 | |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
245 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
0f8c9768 | 246 | |
6d0f6bcf | 247 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
0f8c9768 | 248 | |
6d0f6bcf | 249 | #define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ |
0f8c9768 WD |
250 | |
251 | /* | |
252 | * For booting Linux, the board info and command line data | |
253 | * have to be in the first 8 MB of memory, since this is | |
254 | * the maximum mapped by the Linux kernel during initialization. | |
255 | */ | |
6d0f6bcf | 256 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
0f8c9768 WD |
257 | |
258 | ||
259 | /* What should the base address of the main FLASH be and how big is | |
14d0a02a | 260 | * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk |
0f8c9768 WD |
261 | * The main FLASH is whichever is connected to *CS0. |
262 | */ | |
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_FLASH0_BASE 0x40000000 |
264 | #define CONFIG_SYS_FLASH1_BASE 0x60000000 | |
265 | #define CONFIG_SYS_FLASH0_SIZE 32 | |
266 | #define CONFIG_SYS_FLASH1_SIZE 32 | |
0f8c9768 WD |
267 | |
268 | /* Flash bank size (for preliminary settings) | |
269 | */ | |
6d0f6bcf | 270 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE |
0f8c9768 WD |
271 | |
272 | /*----------------------------------------------------------------------- | |
273 | * FLASH organization | |
274 | */ | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
276 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
0f8c9768 | 277 | |
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
279 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
0f8c9768 | 280 | |
60c68d9c WD |
281 | /* use CFI flash driver */ |
282 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ | |
283 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
284 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
285 | #define CONFIG_SYS_FLASH_EMPTY_INFO 1 | |
286 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
287 | ||
5a1aceb0 | 288 | #define CONFIG_ENV_IS_IN_FLASH 1 |
055b12f2 WD |
289 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
290 | #define CONFIG_ENV_SIZE 0x08000 | |
0e8d1586 | 291 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
055b12f2 WD |
292 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
293 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
0f8c9768 WD |
294 | |
295 | /*----------------------------------------------------------------------- | |
296 | * Hardware Information Block | |
297 | */ | |
6d0f6bcf JCPV |
298 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
299 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
300 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
0f8c9768 WD |
301 | |
302 | /*----------------------------------------------------------------------- | |
303 | * Hard Reset Configuration Words | |
304 | * | |
6d0f6bcf | 305 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
0f8c9768 | 306 | * defines for the various registers affected by the HRCW e.g. changing |
6d0f6bcf | 307 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
0f8c9768 | 308 | */ |
7aa78614 WD |
309 | #define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) |
310 | ||
27b207fd | 311 | #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) |
6d0f6bcf | 312 | # define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) |
27b207fd | 313 | #else /* ! MPC8255 && !MPC8265 */ |
7aa78614 | 314 | # if defined(CONFIG_266MHz) |
6d0f6bcf | 315 | # define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) |
7aa78614 | 316 | # elif defined(CONFIG_300MHz) |
6d0f6bcf | 317 | # define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110) |
7aa78614 | 318 | # else |
6d0f6bcf | 319 | # define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__) |
7aa78614 WD |
320 | # endif |
321 | #endif /* CONFIG_MPC8255 */ | |
0f8c9768 WD |
322 | |
323 | /* no slaves so just fill with zeros */ | |
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
325 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
326 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
327 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
328 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
329 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
330 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
0f8c9768 WD |
331 | |
332 | /*----------------------------------------------------------------------- | |
333 | * Internal Memory Mapped Register | |
334 | */ | |
6d0f6bcf | 335 | #define CONFIG_SYS_IMMR 0xFFF00000 |
0f8c9768 WD |
336 | |
337 | /*----------------------------------------------------------------------- | |
338 | * Definitions for initial stack pointer and data area (in DPRAM) | |
339 | */ | |
6d0f6bcf | 340 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 341 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
25ddd1fb | 342 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 343 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
0f8c9768 WD |
344 | |
345 | /*----------------------------------------------------------------------- | |
346 | * Start addresses for the final memory configuration | |
347 | * (Set up by the startup code) | |
6d0f6bcf | 348 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
0f8c9768 | 349 | * |
6d0f6bcf | 350 | * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM |
0f8c9768 WD |
351 | * is mapped at SDRAM_BASE2_PRELIM. |
352 | */ | |
6d0f6bcf JCPV |
353 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
354 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE | |
14d0a02a | 355 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf | 356 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
055b12f2 | 357 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc()*/ |
0f8c9768 | 358 | |
0f8c9768 WD |
359 | /*----------------------------------------------------------------------- |
360 | * Cache Configuration | |
361 | */ | |
6d0f6bcf | 362 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
2694690e | 363 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 364 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
0f8c9768 WD |
365 | #endif |
366 | ||
367 | /*----------------------------------------------------------------------- | |
368 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
369 | *----------------------------------------------------------------------- | |
370 | * HID0 also contains cache control - initially enable both caches and | |
371 | * invalidate contents, then the final state leaves only the instruction | |
372 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
373 | * but Soft reset does not. | |
374 | * | |
375 | * HID1 has only read-only information - nothing to set. | |
376 | */ | |
6d0f6bcf | 377 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
8bde7f77 | 378 | HID0_IFEM|HID0_ABE) |
6d0f6bcf JCPV |
379 | #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) |
380 | #define CONFIG_SYS_HID2 0 | |
0f8c9768 WD |
381 | |
382 | /*----------------------------------------------------------------------- | |
383 | * RMR - Reset Mode Register 5-5 | |
384 | *----------------------------------------------------------------------- | |
385 | * turn on Checkstop Reset Enable | |
386 | */ | |
6d0f6bcf | 387 | #define CONFIG_SYS_RMR RMR_CSRE |
0f8c9768 WD |
388 | |
389 | /*----------------------------------------------------------------------- | |
390 | * BCR - Bus Configuration 4-25 | |
391 | *----------------------------------------------------------------------- | |
392 | */ | |
393 | #ifdef CONFIG_BUSMODE_60x | |
6d0f6bcf | 394 | #define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ |
0f8c9768 WD |
395 | BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ |
396 | #else | |
397 | #define BCR_APD01 0x10000000 | |
6d0f6bcf | 398 | #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
0f8c9768 WD |
399 | #endif |
400 | ||
401 | /*----------------------------------------------------------------------- | |
402 | * SIUMCR - SIU Module Configuration 4-31 | |
403 | *----------------------------------------------------------------------- | |
404 | */ | |
405 | #if 0 | |
6d0f6bcf | 406 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) |
0f8c9768 | 407 | #else |
6d0f6bcf | 408 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) |
0f8c9768 WD |
409 | #endif |
410 | ||
411 | ||
412 | /*----------------------------------------------------------------------- | |
413 | * SYPCR - System Protection Control 4-35 | |
414 | * SYPCR can only be written once after reset! | |
415 | *----------------------------------------------------------------------- | |
416 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
417 | */ | |
418 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 419 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
8bde7f77 | 420 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
0f8c9768 | 421 | #else |
6d0f6bcf | 422 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
8bde7f77 | 423 | SYPCR_SWRI|SYPCR_SWP) |
0f8c9768 WD |
424 | #endif /* CONFIG_WATCHDOG */ |
425 | ||
426 | /*----------------------------------------------------------------------- | |
427 | * TMCNTSC - Time Counter Status and Control 4-40 | |
428 | *----------------------------------------------------------------------- | |
429 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
430 | * and enable Time Counter | |
431 | */ | |
6d0f6bcf | 432 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
0f8c9768 WD |
433 | |
434 | /*----------------------------------------------------------------------- | |
435 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
436 | *----------------------------------------------------------------------- | |
437 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
438 | * Periodic timer | |
439 | */ | |
6d0f6bcf | 440 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
0f8c9768 WD |
441 | |
442 | /*----------------------------------------------------------------------- | |
443 | * SCCR - System Clock Control 9-8 | |
444 | *----------------------------------------------------------------------- | |
445 | * Ensure DFBRG is Divide by 16 | |
446 | */ | |
6d0f6bcf | 447 | #define CONFIG_SYS_SCCR 0 |
0f8c9768 WD |
448 | |
449 | /*----------------------------------------------------------------------- | |
450 | * RCCR - RISC Controller Configuration 13-7 | |
451 | *----------------------------------------------------------------------- | |
452 | */ | |
6d0f6bcf | 453 | #define CONFIG_SYS_RCCR 0 |
0f8c9768 WD |
454 | |
455 | /* | |
456 | * Init Memory Controller: | |
457 | * | |
458 | * Bank Bus Machine PortSz Device | |
459 | * ---- --- ------- ------ ------ | |
460 | * 0 60x GPCM 64 bit FLASH | |
461 | * 1 60x SDRAM 64 bit SDRAM | |
462 | * 2 Local SDRAM 32 bit SDRAM | |
463 | * | |
464 | */ | |
465 | ||
466 | /* Initialize SDRAM on local bus | |
467 | */ | |
6d0f6bcf | 468 | #define CONFIG_SYS_INIT_LOCAL_SDRAM |
0f8c9768 WD |
469 | |
470 | #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
471 | ||
472 | /* Minimum mask to separate preliminary | |
473 | * address ranges for CS[0:2] | |
474 | */ | |
6d0f6bcf JCPV |
475 | #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ |
476 | #define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ | |
0f8c9768 | 477 | |
6d0f6bcf | 478 | #define CONFIG_SYS_MPTPR 0x4000 |
0f8c9768 WD |
479 | |
480 | /*----------------------------------------------------------------------------- | |
481 | * Address for Mode Register Set (MRS) command | |
482 | *----------------------------------------------------------------------------- | |
483 | * In fact, the address is rather configuration data presented to the SDRAM on | |
484 | * its address lines. Because the address lines may be mux'ed externally either | |
485 | * for 8 column or 9 column devices, some bits appear twice in the 8260's | |
486 | * address: | |
487 | * | |
488 | * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | | |
489 | * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | | |
490 | * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | | |
491 | * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | | |
492 | * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | | |
493 | *----------------------------------------------------------------------------- | |
494 | */ | |
6d0f6bcf | 495 | #define CONFIG_SYS_MRS_OFFS 0x00000110 |
0f8c9768 WD |
496 | |
497 | ||
498 | /* Bank 0 - FLASH | |
499 | */ | |
6d0f6bcf | 500 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
501 | BRx_PS_64 |\ |
502 | BRx_MS_GPCM_P |\ | |
503 | BRx_V) | |
0f8c9768 | 504 | |
6d0f6bcf | 505 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
8bde7f77 WD |
506 | ORxG_CSNT |\ |
507 | ORxG_ACS_DIV1 |\ | |
508 | ORxG_SCY_3_CLK |\ | |
509 | ORxG_EHTR |\ | |
510 | ORxG_TRLX) | |
0f8c9768 WD |
511 | |
512 | /* SDRAM on TQM8260 can have either 8 or 9 columns. | |
513 | * The number affects configuration values. | |
514 | */ | |
515 | ||
516 | /* Bank 1 - 60x bus SDRAM | |
517 | */ | |
6d0f6bcf JCPV |
518 | #define CONFIG_SYS_PSRT 0x20 |
519 | #define CONFIG_SYS_LSRT 0x20 | |
520 | #ifndef CONFIG_SYS_RAMBOOT | |
521 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ | |
8bde7f77 WD |
522 | BRx_PS_64 |\ |
523 | BRx_MS_SDRAM_P |\ | |
524 | BRx_V) | |
0f8c9768 | 525 | |
6d0f6bcf | 526 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL |
0f8c9768 WD |
527 | |
528 | ||
529 | /* SDRAM initialization values for 8-column chips | |
530 | */ | |
6d0f6bcf | 531 | #define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
8bde7f77 WD |
532 | ORxS_BPD_4 |\ |
533 | ORxS_ROWST_PBI1_A7 |\ | |
534 | ORxS_NUMR_12) | |
0f8c9768 | 535 | |
6d0f6bcf | 536 | #define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ |
8bde7f77 WD |
537 | PSDMR_SDAM_A15_IS_A5 |\ |
538 | PSDMR_BSMA_A12_A14 |\ | |
539 | PSDMR_SDA10_PBI1_A8 |\ | |
540 | PSDMR_RFRC_7_CLK |\ | |
541 | PSDMR_PRETOACT_2W |\ | |
542 | PSDMR_ACTTORW_2W |\ | |
543 | PSDMR_LDOTOPRE_1C |\ | |
544 | PSDMR_WRC_2C |\ | |
545 | PSDMR_EAMUX |\ | |
546 | PSDMR_CL_2) | |
0f8c9768 WD |
547 | |
548 | /* SDRAM initialization values for 9-column chips | |
549 | */ | |
6d0f6bcf | 550 | #define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
8bde7f77 WD |
551 | ORxS_BPD_4 |\ |
552 | ORxS_ROWST_PBI1_A5 |\ | |
553 | ORxS_NUMR_13) | |
0f8c9768 | 554 | |
6d0f6bcf | 555 | #define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ |
8bde7f77 WD |
556 | PSDMR_SDAM_A16_IS_A5 |\ |
557 | PSDMR_BSMA_A12_A14 |\ | |
558 | PSDMR_SDA10_PBI1_A7 |\ | |
559 | PSDMR_RFRC_7_CLK |\ | |
560 | PSDMR_PRETOACT_2W |\ | |
561 | PSDMR_ACTTORW_2W |\ | |
562 | PSDMR_LDOTOPRE_1C |\ | |
563 | PSDMR_WRC_2C |\ | |
564 | PSDMR_EAMUX |\ | |
565 | PSDMR_CL_2) | |
0f8c9768 WD |
566 | |
567 | /* Bank 2 - Local bus SDRAM | |
568 | */ | |
6d0f6bcf JCPV |
569 | #ifdef CONFIG_SYS_INIT_LOCAL_SDRAM |
570 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ | |
8bde7f77 WD |
571 | BRx_PS_32 |\ |
572 | BRx_MS_SDRAM_L |\ | |
573 | BRx_V) | |
0f8c9768 | 574 | |
6d0f6bcf | 575 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL |
0f8c9768 WD |
576 | |
577 | #define SDRAM_BASE2_PRELIM 0x80000000 | |
578 | ||
579 | /* SDRAM initialization values for 8-column chips | |
580 | */ | |
6d0f6bcf | 581 | #define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
8bde7f77 WD |
582 | ORxS_BPD_4 |\ |
583 | ORxS_ROWST_PBI1_A8 |\ | |
584 | ORxS_NUMR_12) | |
0f8c9768 | 585 | |
6d0f6bcf | 586 | #define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\ |
8bde7f77 WD |
587 | PSDMR_SDAM_A15_IS_A5 |\ |
588 | PSDMR_BSMA_A13_A15 |\ | |
589 | PSDMR_SDA10_PBI1_A9 |\ | |
590 | PSDMR_RFRC_7_CLK |\ | |
591 | PSDMR_PRETOACT_2W |\ | |
592 | PSDMR_ACTTORW_2W |\ | |
593 | PSDMR_BL |\ | |
594 | PSDMR_LDOTOPRE_1C |\ | |
595 | PSDMR_WRC_2C |\ | |
596 | PSDMR_CL_2) | |
0f8c9768 WD |
597 | |
598 | /* SDRAM initialization values for 9-column chips | |
599 | */ | |
6d0f6bcf | 600 | #define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
8bde7f77 WD |
601 | ORxS_BPD_4 |\ |
602 | ORxS_ROWST_PBI1_A6 |\ | |
603 | ORxS_NUMR_13) | |
0f8c9768 | 604 | |
6d0f6bcf | 605 | #define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\ |
8bde7f77 WD |
606 | PSDMR_SDAM_A16_IS_A5 |\ |
607 | PSDMR_BSMA_A13_A15 |\ | |
608 | PSDMR_SDA10_PBI1_A8 |\ | |
609 | PSDMR_RFRC_7_CLK |\ | |
610 | PSDMR_PRETOACT_2W |\ | |
611 | PSDMR_ACTTORW_2W |\ | |
612 | PSDMR_BL |\ | |
613 | PSDMR_LDOTOPRE_1C |\ | |
614 | PSDMR_WRC_2C |\ | |
615 | PSDMR_CL_2) | |
0f8c9768 | 616 | |
6d0f6bcf | 617 | #endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ |
0f8c9768 | 618 | |
6d0f6bcf | 619 | #endif /* CONFIG_SYS_RAMBOOT */ |
0f8c9768 WD |
620 | |
621 | #endif /* __CONFIG_H */ |