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fa230445 HS |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ | |
37 | #define CONFIG_MPC8272_FAMILY 1 | |
38 | #define CONFIG_TQM8272 1 | |
39 | ||
40 | #define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */ | |
9c0f42ec WD |
41 | #define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */ |
42 | ||
fa230445 HS |
43 | #define STK82xx_150 1 /* on a STK82xx.150 */ |
44 | ||
45 | #define CONFIG_CPM2 1 /* Has a CPM2 */ | |
46 | ||
47 | #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ | |
48 | ||
49 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
50 | ||
51 | #define CONFIG_BOARD_EARLY_INIT_R 1 | |
52 | ||
53 | #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) | |
54 | #define CONFIG_BAUDRATE 230400 | |
55 | #else | |
56 | #define CONFIG_BAUDRATE 115200 | |
57 | #endif | |
58 | ||
32bf3d14 | 59 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
fa230445 HS |
60 | |
61 | #undef CONFIG_BOOTARGS | |
62 | ||
63 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
64 | "netdev=eth0\0" \ | |
65 | "consdev=ttyCPM0\0" \ | |
66 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
67 | "nfsroot=${serverip}:${rootpath}\0" \ | |
68 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
69 | "hostname=tqm8272\0" \ | |
70 | "addip=setenv bootargs ${bootargs} " \ | |
71 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
72 | ":${hostname}:${netdev}:off panic=1\0" \ | |
73 | "addcons=setenv bootargs ${bootargs} " \ | |
9c0f42ec WD |
74 | "console=$(consdev),$(baudrate)\0" \ |
75 | "flash_nfs=run nfsargs addip addcons;" \ | |
fa230445 | 76 | "bootm ${kernel_addr}\0" \ |
9c0f42ec | 77 | "flash_self=run ramargs addip addcons;" \ |
fa230445 HS |
78 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
79 | "net_nfs=tftp 300000 ${bootfile};" \ | |
9c0f42ec | 80 | "run nfsargs addip addcons;bootm\0" \ |
fa230445 HS |
81 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
82 | "bootfile=/tftpboot/tqm8272/uImage\0" \ | |
83 | "kernel_addr=40080000\0" \ | |
84 | "ramdisk_addr=40100000\0" \ | |
85 | "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \ | |
86 | "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \ | |
87 | "cp.b 300000 40000000 40000;" \ | |
88 | "setenv filesize;saveenv\0" \ | |
9c0f42ec | 89 | "cphwib=cp.b 4003fc00 33fc00 400\0" \ |
d8ab58b2 | 90 | "upd=run load cphwib update\0" \ |
fa230445 HS |
91 | "" |
92 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
93 | ||
94 | #define CONFIG_I2C 1 | |
95 | ||
96 | #if CONFIG_I2C | |
97 | /* enable I2C and select the hardware/software driver */ | |
98 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
99 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
fa230445 HS |
100 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
101 | #define CFG_I2C_SLAVE 0x7F | |
102 | ||
103 | /* | |
104 | * Software (bit-bang) I2C driver configuration | |
105 | */ | |
106 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
107 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
108 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
109 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
110 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
111 | else iop->pdat &= ~0x00010000 | |
112 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
113 | else iop->pdat &= ~0x00020000 | |
114 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
115 | ||
116 | #define CONFIG_I2C_X | |
117 | ||
118 | /* EEPROM */ | |
119 | #define CFG_I2C_EEPROM_ADDR_LEN 2 | |
120 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 | |
121 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
122 | #define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */ | |
123 | #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ | |
124 | ||
125 | /* I2C RTC */ | |
126 | #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ | |
127 | #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
128 | ||
129 | /* I2C SYSMON (LM75) */ | |
130 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
131 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
132 | #define CFG_DTT_MAX_TEMP 70 | |
133 | #define CFG_DTT_LOW_TEMP -30 | |
134 | #define CFG_DTT_HYSTERESIS 3 | |
135 | ||
136 | #else | |
137 | #undef CONFIG_HARD_I2C | |
138 | #undef CONFIG_SOFT_I2C | |
fa230445 HS |
139 | #endif |
140 | ||
141 | /* | |
142 | * select serial console configuration | |
143 | * | |
144 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
145 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
146 | * for SCC). | |
147 | * | |
148 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
149 | * defined elsewhere (for example, on the cogent platform, there are serial | |
150 | * ports on the motherboard which are used for the serial console - see | |
151 | * cogent/cma101/serial.[ch]). | |
152 | */ | |
153 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
154 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
155 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
156 | #ifdef CONFIG_82xx_CONS_SMC1 | |
157 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
158 | #endif | |
159 | #ifdef CONFIG_82xx_CONS_SMC2 | |
160 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
161 | #endif | |
162 | ||
163 | #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ | |
164 | #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ | |
165 | #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ | |
166 | ||
167 | /* | |
168 | * select ethernet configuration | |
169 | * | |
170 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
171 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
172 | * for FCC) | |
173 | * | |
174 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 175 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
fa230445 HS |
176 | * |
177 | * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the | |
178 | * X.29 connector, and FCC2 is hardwired to the X.1 connector) | |
179 | */ | |
180 | #define CFG_FCC_ETHERNET | |
181 | ||
182 | #if defined(CFG_FCC_ETHERNET) | |
183 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
184 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
185 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
186 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
187 | #else | |
188 | #define CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
189 | #undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
190 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
191 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ | |
192 | #endif | |
193 | ||
194 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) | |
195 | ||
196 | /* | |
197 | * - RX clk is CLK11 | |
198 | * - TX clk is CLK12 | |
199 | */ | |
200 | # define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) | |
201 | ||
202 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
203 | ||
204 | /* | |
205 | * - Rx-CLK is CLK13 | |
206 | * - Tx-CLK is CLK14 | |
207 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
208 | * - Enable Full Duplex in FSMR | |
209 | */ | |
210 | # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) | |
211 | # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
212 | # define CFG_CPMFCR_RAMTYPE 0 | |
213 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
214 | ||
215 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
216 | ||
217 | #define CONFIG_MII /* MII PHY management */ | |
218 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
219 | /* | |
220 | * GPIO pins used for bit-banged MII communications | |
221 | */ | |
222 | #define MDIO_PORT 2 /* Port C */ | |
223 | ||
224 | #if STK82xx_150 | |
225 | #define CFG_MDIO_PIN 0x00008000 /* PC16 */ | |
226 | #define CFG_MDC_PIN 0x00004000 /* PC17 */ | |
227 | #endif | |
228 | ||
229 | #if STK82xx_100 | |
230 | #define CFG_MDIO_PIN 0x00000002 /* PC30 */ | |
231 | #define CFG_MDC_PIN 0x00000001 /* PC31 */ | |
232 | #endif | |
233 | ||
234 | #if 1 | |
235 | #define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) | |
236 | #define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) | |
237 | #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) | |
238 | ||
239 | #define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ | |
240 | else iop->pdat &= ~CFG_MDIO_PIN | |
241 | ||
242 | #define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ | |
243 | else iop->pdat &= ~CFG_MDC_PIN | |
244 | #else | |
245 | #define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CFG_MDIO_PIN; iop->pdir = tmp;}) | |
246 | #define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;}) | |
247 | #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) | |
248 | ||
249 | #define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDIO_PIN; iop->pdat = tmp;}\ | |
250 | else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;} | |
251 | ||
252 | #define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDC_PIN; iop->pdat = tmp;}\ | |
253 | else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;} | |
254 | #endif | |
255 | ||
256 | #define MIIDELAY udelay(1) | |
257 | ||
258 | ||
fa230445 HS |
259 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
260 | #define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
261 | ||
262 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
263 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
264 | ||
265 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
266 | ||
267 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
268 | ||
37d4bb70 JL |
269 | /* |
270 | * BOOTP options | |
271 | */ | |
272 | #define CONFIG_BOOTP_SUBNETMASK | |
273 | #define CONFIG_BOOTP_GATEWAY | |
274 | #define CONFIG_BOOTP_HOSTNAME | |
275 | #define CONFIG_BOOTP_BOOTPATH | |
276 | #define CONFIG_BOOTP_BOOTFILESIZE | |
fa230445 | 277 | |
2694690e JL |
278 | |
279 | /* | |
280 | * Command line configuration. | |
281 | */ | |
282 | #include <config_cmd_default.h> | |
283 | ||
284 | #define CONFIG_CMD_I2C | |
285 | #define CONFIG_CMD_DHCP | |
286 | #define CONFIG_CMD_MII | |
287 | #define CONFIG_CMD_NAND | |
288 | #define CONFIG_CMD_NFS | |
289 | #define CONFIG_CMD_PCI | |
290 | #define CONFIG_CMD_PING | |
291 | #define CONFIG_CMD_SNTP | |
292 | ||
a1aa0bb5 JL |
293 | #if CONFIG_I2C |
294 | #define CONFIG_CMD_I2C | |
295 | #define CONFIG_CMD_DATE | |
296 | #define CONFIG_CMD_DTT | |
297 | #define CONFIG_CMD_EEPROM | |
298 | #endif | |
299 | ||
fa230445 HS |
300 | |
301 | /* | |
302 | * Miscellaneous configurable options | |
303 | */ | |
304 | #define CFG_LONGHELP /* undef to save memory */ | |
305 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
306 | ||
307 | #if 0 | |
308 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
309 | #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ | |
310 | #ifdef CFG_HUSH_PARSER | |
311 | #define CFG_PROMPT_HUSH_PS2 "> " | |
312 | #endif | |
313 | #endif | |
314 | ||
2694690e | 315 | #if defined(CONFIG_CMD_KGDB) |
fa230445 HS |
316 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
317 | #else | |
318 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
319 | #endif | |
320 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
321 | #define CFG_MAXARGS 16 /* max number of command args */ | |
322 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
323 | ||
324 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
325 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
326 | ||
327 | #define CFG_LOAD_ADDR 0x300000 /* default load address */ | |
328 | ||
329 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
330 | ||
331 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
332 | ||
333 | #define CFG_RESET_ADDRESS 0x40000104 /* "bad" address */ | |
334 | ||
335 | /* | |
336 | * For booting Linux, the board info and command line data | |
337 | * have to be in the first 8 MB of memory, since this is | |
338 | * the maximum mapped by the Linux kernel during initialization. | |
339 | */ | |
340 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
341 | ||
342 | /*----------------------------------------------------------------------- | |
343 | * CAN stuff | |
344 | *----------------------------------------------------------------------- | |
345 | */ | |
346 | #define CFG_CAN_BASE 0x51000000 | |
347 | #define CFG_CAN_SIZE 1 | |
348 | #define CFG_CAN_BR ((CFG_CAN_BASE & BRx_BA_MSK) |\ | |
349 | BRx_PS_8 |\ | |
350 | BRx_MS_UPMC |\ | |
351 | BRx_V) | |
352 | ||
353 | #define CFG_CAN_OR (MEG_TO_AM(CFG_CAN_SIZE) |\ | |
354 | ORxU_BI) | |
355 | ||
356 | ||
357 | /* What should the base address of the main FLASH be and how big is | |
358 | * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk | |
359 | * The main FLASH is whichever is connected to *CS0. | |
360 | */ | |
361 | #define CFG_FLASH0_BASE 0x40000000 | |
362 | #define CFG_FLASH0_SIZE 32 /* 32 MB */ | |
363 | ||
364 | /* Flash bank size (for preliminary settings) | |
365 | */ | |
366 | #define CFG_FLASH_SIZE CFG_FLASH0_SIZE | |
367 | ||
368 | /*----------------------------------------------------------------------- | |
369 | * FLASH organization | |
370 | */ | |
371 | #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
372 | #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
373 | ||
374 | #define CFG_FLASH_CFI /* flash is CFI compat. */ | |
375 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ | |
376 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ | |
377 | #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ | |
378 | ||
379 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
380 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
381 | ||
382 | #define CFG_UPDATE_FLASH_SIZE | |
383 | ||
384 | #define CFG_ENV_IS_IN_FLASH 1 | |
385 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) | |
386 | #define CFG_ENV_SIZE 0x20000 | |
387 | #define CFG_ENV_SECT_SIZE 0x20000 | |
388 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SIZE) | |
389 | #define CFG_ENV_SIZE_REDUND 0x20000 | |
390 | ||
391 | /* Where is the Hardwareinformation Block (from Monitor Sources) */ | |
392 | #define MON_RES_LENGTH (0x0003FC00) | |
393 | #define HWIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH) | |
394 | #define HWIB_INFO_LEN 512 | |
395 | #define CIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN) | |
396 | #define CIB_INFO_LEN 512 | |
397 | ||
398 | #define CFG_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */ | |
399 | #define CFG_HWINFO_SIZE 0x00000060 /* size of HW Info block */ | |
400 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
401 | ||
402 | /*----------------------------------------------------------------------- | |
403 | * NAND-FLASH stuff | |
404 | *----------------------------------------------------------------------- | |
405 | */ | |
2694690e | 406 | #if defined(CONFIG_CMD_NAND) |
fa230445 HS |
407 | |
408 | #define CFG_NAND_CS_DIST 0x80 | |
409 | #define CFG_NAND_UPM_WRITE_CMD_OFS 0x20 | |
410 | #define CFG_NAND_UPM_WRITE_ADDR_OFS 0x40 | |
411 | ||
412 | #define CFG_NAND_BR ((CFG_NAND0_BASE & BRx_BA_MSK) |\ | |
413 | BRx_PS_8 |\ | |
414 | BRx_MS_UPMB |\ | |
415 | BRx_V) | |
416 | ||
417 | #define CFG_NAND_OR (MEG_TO_AM(CFG_NAND_SIZE) |\ | |
418 | ORxU_BI |\ | |
419 | ORxU_EHTR_8IDLE) | |
420 | ||
421 | #define CFG_NAND_SIZE 1 | |
422 | #define CFG_NAND0_BASE 0x50000000 | |
423 | #define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST) | |
424 | #define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST) | |
425 | #define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST) | |
426 | ||
427 | #define CFG_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ | |
428 | #define NAND_MAX_CHIPS 1 | |
429 | ||
430 | #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ | |
431 | CFG_NAND1_BASE, \ | |
432 | CFG_NAND2_BASE, \ | |
433 | CFG_NAND3_BASE, \ | |
434 | } | |
435 | ||
436 | #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0) | |
437 | #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr))) | |
438 | #define WRITE_NAND_UPM(d, adr, off) do \ | |
439 | { \ | |
440 | volatile unsigned char *addr = (unsigned char *) (adr + off); \ | |
441 | WRITE_NAND(d, addr); \ | |
442 | } while(0) | |
443 | ||
a1aa0bb5 | 444 | #endif /* CONFIG_CMD_NAND */ |
fa230445 HS |
445 | |
446 | #define CONFIG_PCI | |
447 | #ifdef CONFIG_PCI | |
448 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
449 | #define CONFIG_PCI_PNP | |
450 | #define CONFIG_EEPRO100 | |
451 | #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ | |
452 | #define CONFIG_PCI_SCAN_SHOW | |
453 | #endif | |
454 | ||
455 | /*----------------------------------------------------------------------- | |
456 | * Hard Reset Configuration Words | |
457 | * | |
458 | * if you change bits in the HRCW, you must also change the CFG_* | |
459 | * defines for the various registers affected by the HRCW e.g. changing | |
460 | * HRCW_DPPCxx requires you to also change CFG_SIUMCR. | |
461 | */ | |
462 | #if 0 | |
463 | #define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) | |
464 | ||
465 | # define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) | |
466 | #else | |
467 | #define CFG_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111) | |
468 | #endif | |
469 | ||
470 | /* no slaves so just fill with zeros */ | |
471 | #define CFG_HRCW_SLAVE1 0 | |
472 | #define CFG_HRCW_SLAVE2 0 | |
473 | #define CFG_HRCW_SLAVE3 0 | |
474 | #define CFG_HRCW_SLAVE4 0 | |
475 | #define CFG_HRCW_SLAVE5 0 | |
476 | #define CFG_HRCW_SLAVE6 0 | |
477 | #define CFG_HRCW_SLAVE7 0 | |
478 | ||
479 | /*----------------------------------------------------------------------- | |
480 | * Internal Memory Mapped Register | |
481 | */ | |
482 | #define CFG_IMMR 0xFFF00000 | |
483 | ||
484 | /*----------------------------------------------------------------------- | |
485 | * Definitions for initial stack pointer and data area (in DPRAM) | |
486 | */ | |
487 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
488 | #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ | |
489 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ | |
490 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
491 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
492 | ||
493 | /*----------------------------------------------------------------------- | |
494 | * Start addresses for the final memory configuration | |
495 | * (Set up by the startup code) | |
496 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
497 | */ | |
498 | #define CFG_SDRAM_BASE 0x00000000 | |
499 | #define CFG_FLASH_BASE CFG_FLASH0_BASE | |
500 | #define CFG_MONITOR_BASE TEXT_BASE | |
501 | #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ | |
502 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
503 | ||
504 | /* | |
505 | * Internal Definitions | |
506 | * | |
507 | * Boot Flags | |
508 | */ | |
509 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
510 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
511 | ||
fa230445 HS |
512 | /*----------------------------------------------------------------------- |
513 | * Cache Configuration | |
514 | */ | |
515 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ | |
2694690e | 516 | #if defined(CONFIG_CMD_KGDB) |
fa230445 HS |
517 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
518 | #endif | |
519 | ||
520 | /*----------------------------------------------------------------------- | |
521 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
522 | *----------------------------------------------------------------------- | |
523 | * HID0 also contains cache control - initially enable both caches and | |
524 | * invalidate contents, then the final state leaves only the instruction | |
525 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
526 | * but Soft reset does not. | |
527 | * | |
528 | * HID1 has only read-only information - nothing to set. | |
529 | */ | |
530 | #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ | |
531 | HID0_IFEM|HID0_ABE) | |
532 | #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) | |
533 | #define CFG_HID2 0 | |
534 | ||
535 | /*----------------------------------------------------------------------- | |
536 | * RMR - Reset Mode Register 5-5 | |
537 | *----------------------------------------------------------------------- | |
538 | * turn on Checkstop Reset Enable | |
539 | */ | |
540 | #define CFG_RMR RMR_CSRE | |
541 | ||
542 | /*----------------------------------------------------------------------- | |
543 | * BCR - Bus Configuration 4-25 | |
544 | *----------------------------------------------------------------------- | |
545 | */ | |
546 | #define CFG_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */ | |
547 | #define BCR_APD01 0x10000000 | |
548 | #define CFG_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */ | |
549 | ||
550 | /*----------------------------------------------------------------------- | |
551 | * SIUMCR - SIU Module Configuration 4-31 | |
552 | *----------------------------------------------------------------------- | |
553 | */ | |
554 | #if defined(CONFIG_BOARD_GET_CPU_CLK_F) | |
555 | #define CFG_SIUMCR_LOW (SIUMCR_DPPC00) | |
556 | #define CFG_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE) | |
557 | #else | |
558 | #define CFG_SIUMCR (SIUMCR_DPPC00) | |
559 | #endif | |
560 | ||
561 | /*----------------------------------------------------------------------- | |
562 | * SYPCR - System Protection Control 4-35 | |
563 | * SYPCR can only be written once after reset! | |
564 | *----------------------------------------------------------------------- | |
565 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
566 | */ | |
567 | #if defined(CONFIG_WATCHDOG) | |
568 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
569 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) | |
570 | #else | |
571 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
572 | SYPCR_SWRI|SYPCR_SWP) | |
573 | #endif /* CONFIG_WATCHDOG */ | |
574 | ||
575 | /*----------------------------------------------------------------------- | |
576 | * TMCNTSC - Time Counter Status and Control 4-40 | |
577 | *----------------------------------------------------------------------- | |
578 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
579 | * and enable Time Counter | |
580 | */ | |
581 | #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
582 | ||
583 | /*----------------------------------------------------------------------- | |
584 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
585 | *----------------------------------------------------------------------- | |
586 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
587 | * Periodic timer | |
588 | */ | |
589 | #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
590 | ||
591 | /*----------------------------------------------------------------------- | |
592 | * SCCR - System Clock Control 9-8 | |
593 | *----------------------------------------------------------------------- | |
594 | * Ensure DFBRG is Divide by 16 | |
595 | */ | |
596 | #define CFG_SCCR SCCR_DFBRG01 | |
597 | ||
598 | /*----------------------------------------------------------------------- | |
599 | * RCCR - RISC Controller Configuration 13-7 | |
600 | *----------------------------------------------------------------------- | |
601 | */ | |
602 | #define CFG_RCCR 0 | |
603 | ||
604 | /* | |
605 | * Init Memory Controller: | |
606 | * | |
607 | * Bank Bus Machine PortSz Device | |
608 | * ---- --- ------- ------ ------ | |
609 | * 0 60x GPCM 32 bit FLASH | |
610 | * 1 60x SDRAM 64 bit SDRAM | |
611 | * 2 60x UPMB 8 bit NAND | |
9c0f42ec | 612 | * 3 60x UPMC 8 bit CAN |
fa230445 HS |
613 | * |
614 | */ | |
615 | ||
616 | /* Initialize SDRAM | |
617 | */ | |
618 | #undef CFG_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */ | |
619 | ||
620 | #define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */ | |
621 | ||
622 | /* Minimum mask to separate preliminary | |
623 | * address ranges for CS[0:2] | |
624 | */ | |
625 | #define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ | |
626 | ||
627 | #define CFG_MPTPR 0x4000 | |
628 | ||
629 | /*----------------------------------------------------------------------------- | |
630 | * Address for Mode Register Set (MRS) command | |
631 | *----------------------------------------------------------------------------- | |
632 | * In fact, the address is rather configuration data presented to the SDRAM on | |
633 | * its address lines. Because the address lines may be mux'ed externally either | |
634 | * for 8 column or 9 column devices, some bits appear twice in the 8260's | |
635 | * address: | |
636 | * | |
637 | * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | | |
638 | * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | | |
639 | * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | | |
640 | * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | | |
641 | * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | | |
642 | *----------------------------------------------------------------------------- | |
643 | */ | |
644 | #define CFG_MRS_OFFS 0x00000110 | |
645 | ||
fa230445 HS |
646 | /* Bank 0 - FLASH |
647 | */ | |
648 | #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ | |
649 | BRx_PS_32 |\ | |
650 | BRx_MS_GPCM_P |\ | |
651 | BRx_V) | |
652 | ||
653 | #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ | |
654 | ORxG_CSNT |\ | |
655 | ORxG_ACS_DIV4 |\ | |
656 | ORxG_SCY_8_CLK |\ | |
657 | ORxG_TRLX) | |
658 | ||
659 | /* SDRAM on TQM8272 can have either 8 or 9 columns. | |
660 | * The number affects configuration values. | |
661 | */ | |
662 | ||
663 | /* Bank 1 - 60x bus SDRAM | |
664 | */ | |
665 | #define CFG_PSRT 0x20 /* Low Value */ | |
666 | /* #define CFG_PSRT 0x10 Fast Value */ | |
667 | #define CFG_LSRT 0x20 /* Local Bus */ | |
668 | #ifndef CFG_RAMBOOT | |
669 | #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ | |
670 | BRx_PS_64 |\ | |
671 | BRx_MS_SDRAM_P |\ | |
672 | BRx_V) | |
673 | ||
674 | #define CFG_OR1_PRELIM CFG_OR1_8COL | |
675 | ||
676 | /* SDRAM initialization values for 8-column chips | |
677 | */ | |
678 | #define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ | |
679 | ORxS_BPD_4 |\ | |
680 | ORxS_ROWST_PBI1_A7 |\ | |
681 | ORxS_NUMR_12) | |
682 | ||
683 | #define CFG_PSDMR_8COL (PSDMR_PBI |\ | |
684 | PSDMR_SDAM_A15_IS_A5 |\ | |
685 | PSDMR_BSMA_A12_A14 |\ | |
686 | PSDMR_SDA10_PBI1_A8 |\ | |
687 | PSDMR_RFRC_7_CLK |\ | |
688 | PSDMR_PRETOACT_2W |\ | |
689 | PSDMR_ACTTORW_2W |\ | |
690 | PSDMR_LDOTOPRE_1C |\ | |
691 | PSDMR_WRC_2C |\ | |
692 | PSDMR_EAMUX |\ | |
693 | PSDMR_BUFCMD |\ | |
694 | PSDMR_CL_2) | |
695 | ||
696 | ||
697 | /* SDRAM initialization values for 9-column chips | |
698 | */ | |
699 | #define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ | |
700 | ORxS_BPD_4 |\ | |
701 | ORxS_ROWST_PBI1_A5 |\ | |
702 | ORxS_NUMR_13) | |
703 | ||
704 | #define CFG_PSDMR_9COL (PSDMR_PBI |\ | |
705 | PSDMR_SDAM_A16_IS_A5 |\ | |
706 | PSDMR_BSMA_A12_A14 |\ | |
707 | PSDMR_SDA10_PBI1_A7 |\ | |
708 | PSDMR_RFRC_7_CLK |\ | |
709 | PSDMR_PRETOACT_2W |\ | |
710 | PSDMR_ACTTORW_2W |\ | |
711 | PSDMR_LDOTOPRE_1C |\ | |
712 | PSDMR_WRC_2C |\ | |
713 | PSDMR_EAMUX |\ | |
714 | PSDMR_BUFCMD |\ | |
715 | PSDMR_CL_2) | |
716 | ||
717 | #define CFG_OR1_10COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ | |
718 | ORxS_BPD_4 |\ | |
719 | ORxS_ROWST_PBI1_A4 |\ | |
720 | ORxS_NUMR_13) | |
721 | ||
722 | #define CFG_PSDMR_10COL (PSDMR_PBI |\ | |
723 | PSDMR_SDAM_A17_IS_A5 |\ | |
724 | PSDMR_BSMA_A12_A14 |\ | |
725 | PSDMR_SDA10_PBI1_A4 |\ | |
726 | PSDMR_RFRC_6_CLK |\ | |
727 | PSDMR_PRETOACT_2W |\ | |
728 | PSDMR_ACTTORW_2W |\ | |
729 | PSDMR_LDOTOPRE_1C |\ | |
730 | PSDMR_WRC_2C |\ | |
731 | PSDMR_EAMUX |\ | |
732 | PSDMR_BUFCMD |\ | |
733 | PSDMR_CL_2) | |
734 | ||
fa230445 HS |
735 | #define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ |
736 | #define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ | |
737 | #define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ | |
738 | #define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */ | |
739 | #define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */ | |
740 | #define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */ | |
741 | ||
742 | #define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */ | |
743 | #define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */ | |
744 | #define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */ | |
745 | #define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */ | |
746 | #define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */ | |
747 | #define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */ | |
748 | ||
749 | #define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */ | |
750 | #define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */ | |
751 | #define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */ | |
752 | #define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */ | |
753 | #define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */ | |
754 | #define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */ | |
755 | ||
756 | #define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */ | |
757 | #define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */ | |
758 | #define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */ | |
759 | #define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */ | |
760 | #define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */ | |
761 | #define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */ | |
762 | ||
763 | #endif /* CFG_RAMBOOT */ | |
764 | ||
765 | #endif /* __CONFIG_H */ |