projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| fa230445 HS |
1 | /* |
| 2 | * (C) Copyright 2006 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | /* | |
| 32 | * High Level Configuration Options | |
| 33 | * (easy to change) | |
| 34 | */ | |
| 35 | ||
| 36 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ | |
| 37 | #define CONFIG_MPC8272_FAMILY 1 | |
| 38 | #define CONFIG_TQM8272 1 | |
| 39 | ||
| 2ae18241 WD |
40 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
| 41 | ||
| fa230445 | 42 | #define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */ |
| 9c0f42ec WD |
43 | #define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */ |
| 44 | ||
| fa230445 HS |
45 | #define STK82xx_150 1 /* on a STK82xx.150 */ |
| 46 | ||
| 47 | #define CONFIG_CPM2 1 /* Has a CPM2 */ | |
| 48 | ||
| 49 | #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ | |
| 50 | ||
| 51 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 52 | ||
| 53 | #define CONFIG_BOARD_EARLY_INIT_R 1 | |
| 54 | ||
| 55 | #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) | |
| 56 | #define CONFIG_BAUDRATE 230400 | |
| 57 | #else | |
| 58 | #define CONFIG_BAUDRATE 115200 | |
| 59 | #endif | |
| 60 | ||
| 32bf3d14 | 61 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
| fa230445 HS |
62 | |
| 63 | #undef CONFIG_BOOTARGS | |
| 64 | ||
| 65 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 66 | "netdev=eth0\0" \ | |
| 67 | "consdev=ttyCPM0\0" \ | |
| 68 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 69 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 70 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 71 | "hostname=tqm8272\0" \ | |
| 72 | "addip=setenv bootargs ${bootargs} " \ | |
| 73 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 74 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 75 | "addcons=setenv bootargs ${bootargs} " \ | |
| 9c0f42ec WD |
76 | "console=$(consdev),$(baudrate)\0" \ |
| 77 | "flash_nfs=run nfsargs addip addcons;" \ | |
| fa230445 | 78 | "bootm ${kernel_addr}\0" \ |
| 9c0f42ec | 79 | "flash_self=run ramargs addip addcons;" \ |
| fa230445 HS |
80 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 81 | "net_nfs=tftp 300000 ${bootfile};" \ | |
| 9c0f42ec | 82 | "run nfsargs addip addcons;bootm\0" \ |
| fa230445 HS |
83 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
| 84 | "bootfile=/tftpboot/tqm8272/uImage\0" \ | |
| 85 | "kernel_addr=40080000\0" \ | |
| 86 | "ramdisk_addr=40100000\0" \ | |
| 87 | "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \ | |
| 88 | "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \ | |
| 89 | "cp.b 300000 40000000 40000;" \ | |
| 90 | "setenv filesize;saveenv\0" \ | |
| 9c0f42ec | 91 | "cphwib=cp.b 4003fc00 33fc00 400\0" \ |
| d8ab58b2 | 92 | "upd=run load cphwib update\0" \ |
| fa230445 HS |
93 | "" |
| 94 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 95 | ||
| 96 | #define CONFIG_I2C 1 | |
| 97 | ||
| 98 | #if CONFIG_I2C | |
| 99 | /* enable I2C and select the hardware/software driver */ | |
| 100 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 101 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
| 6d0f6bcf JCPV |
102 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 103 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| fa230445 HS |
104 | |
| 105 | /* | |
| 106 | * Software (bit-bang) I2C driver configuration | |
| 107 | */ | |
| 108 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
| 109 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
| 110 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
| 111 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
| 112 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
| 113 | else iop->pdat &= ~0x00010000 | |
| 114 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
| 115 | else iop->pdat &= ~0x00020000 | |
| 116 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
| 117 | ||
| 118 | #define CONFIG_I2C_X | |
| 119 | ||
| 120 | /* EEPROM */ | |
| 6d0f6bcf JCPV |
121 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
| 122 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
| 123 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
| 124 | #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ | |
| fa230445 HS |
125 | |
| 126 | /* I2C RTC */ | |
| 127 | #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ | |
| 6d0f6bcf | 128 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
| fa230445 HS |
129 | |
| 130 | /* I2C SYSMON (LM75) */ | |
| 131 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
| 132 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
| 6d0f6bcf JCPV |
133 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
| 134 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
| 135 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
| fa230445 HS |
136 | |
| 137 | #else | |
| 138 | #undef CONFIG_HARD_I2C | |
| 139 | #undef CONFIG_SOFT_I2C | |
| fa230445 HS |
140 | #endif |
| 141 | ||
| 142 | /* | |
| 143 | * select serial console configuration | |
| 144 | * | |
| 145 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
| 146 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
| 147 | * for SCC). | |
| 148 | * | |
| 149 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
| 150 | * defined elsewhere (for example, on the cogent platform, there are serial | |
| 151 | * ports on the motherboard which are used for the serial console - see | |
| 152 | * cogent/cma101/serial.[ch]). | |
| 153 | */ | |
| 154 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
| 155 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
| 156 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
| 157 | #ifdef CONFIG_82xx_CONS_SMC1 | |
| 158 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
| 159 | #endif | |
| 160 | #ifdef CONFIG_82xx_CONS_SMC2 | |
| 161 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
| 162 | #endif | |
| 163 | ||
| 164 | #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ | |
| 165 | #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ | |
| 166 | #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ | |
| 167 | ||
| 168 | /* | |
| 169 | * select ethernet configuration | |
| 170 | * | |
| 171 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
| 172 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
| 173 | * for FCC) | |
| 174 | * | |
| 175 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
| 639221c7 | 176 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
| fa230445 HS |
177 | * |
| 178 | * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the | |
| 179 | * X.29 connector, and FCC2 is hardwired to the X.1 connector) | |
| 180 | */ | |
| 6d0f6bcf | 181 | #define CONFIG_SYS_FCC_ETHERNET |
| fa230445 | 182 | |
| 6d0f6bcf | 183 | #if defined(CONFIG_SYS_FCC_ETHERNET) |
| fa230445 HS |
184 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
| 185 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
| 186 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
| 187 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
| 188 | #else | |
| 189 | #define CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
| 190 | #undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
| 191 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
| 192 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ | |
| 193 | #endif | |
| 194 | ||
| 195 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) | |
| 196 | ||
| 197 | /* | |
| 198 | * - RX clk is CLK11 | |
| 199 | * - TX clk is CLK12 | |
| 200 | */ | |
| 6d0f6bcf | 201 | # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) |
| fa230445 HS |
202 | |
| 203 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
| 204 | ||
| 205 | /* | |
| 206 | * - Rx-CLK is CLK13 | |
| 207 | * - Tx-CLK is CLK14 | |
| 208 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
| 209 | * - Enable Full Duplex in FSMR | |
| 210 | */ | |
| 6d0f6bcf JCPV |
211 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
| 212 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
| 213 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
| 214 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
| fa230445 HS |
215 | |
| 216 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
| 217 | ||
| 218 | #define CONFIG_MII /* MII PHY management */ | |
| 219 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
| 220 | /* | |
| 221 | * GPIO pins used for bit-banged MII communications | |
| 222 | */ | |
| 223 | #define MDIO_PORT 2 /* Port C */ | |
| be225442 LCM |
224 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
| 225 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
| 226 | #define MDC_DECLARE MDIO_DECLARE | |
| fa230445 HS |
227 | |
| 228 | #if STK82xx_150 | |
| 6d0f6bcf JCPV |
229 | #define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */ |
| 230 | #define CONFIG_SYS_MDC_PIN 0x00004000 /* PC17 */ | |
| fa230445 HS |
231 | #endif |
| 232 | ||
| 233 | #if STK82xx_100 | |
| 6d0f6bcf JCPV |
234 | #define CONFIG_SYS_MDIO_PIN 0x00000002 /* PC30 */ |
| 235 | #define CONFIG_SYS_MDC_PIN 0x00000001 /* PC31 */ | |
| fa230445 HS |
236 | #endif |
| 237 | ||
| 238 | #if 1 | |
| 6d0f6bcf JCPV |
239 | #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) |
| 240 | #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) | |
| 241 | #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) | |
| fa230445 | 242 | |
| 6d0f6bcf JCPV |
243 | #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ |
| 244 | else iop->pdat &= ~CONFIG_SYS_MDIO_PIN | |
| fa230445 | 245 | |
| 6d0f6bcf JCPV |
246 | #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ |
| 247 | else iop->pdat &= ~CONFIG_SYS_MDC_PIN | |
| fa230445 | 248 | #else |
| 6d0f6bcf JCPV |
249 | #define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) |
| 250 | #define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) | |
| 251 | #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) | |
| fa230445 | 252 | |
| 6d0f6bcf JCPV |
253 | #define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\ |
| 254 | else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;} | |
| fa230445 | 255 | |
| 6d0f6bcf JCPV |
256 | #define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\ |
| 257 | else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;} | |
| fa230445 HS |
258 | #endif |
| 259 | ||
| 260 | #define MIIDELAY udelay(1) | |
| 261 | ||
| 262 | ||
| fa230445 HS |
263 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
| 264 | #define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
| 265 | ||
| 266 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 267 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| fa230445 HS |
268 | |
| 269 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 270 | ||
| 271 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
| 272 | ||
| 37d4bb70 JL |
273 | /* |
| 274 | * BOOTP options | |
| 275 | */ | |
| 276 | #define CONFIG_BOOTP_SUBNETMASK | |
| 277 | #define CONFIG_BOOTP_GATEWAY | |
| 278 | #define CONFIG_BOOTP_HOSTNAME | |
| 279 | #define CONFIG_BOOTP_BOOTPATH | |
| 280 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| fa230445 | 281 | |
| 2694690e JL |
282 | |
| 283 | /* | |
| 284 | * Command line configuration. | |
| 285 | */ | |
| 286 | #include <config_cmd_default.h> | |
| 287 | ||
| 288 | #define CONFIG_CMD_I2C | |
| 289 | #define CONFIG_CMD_DHCP | |
| 290 | #define CONFIG_CMD_MII | |
| 291 | #define CONFIG_CMD_NAND | |
| 292 | #define CONFIG_CMD_NFS | |
| 293 | #define CONFIG_CMD_PCI | |
| 294 | #define CONFIG_CMD_PING | |
| 295 | #define CONFIG_CMD_SNTP | |
| 296 | ||
| a1aa0bb5 JL |
297 | #if CONFIG_I2C |
| 298 | #define CONFIG_CMD_I2C | |
| 299 | #define CONFIG_CMD_DATE | |
| 300 | #define CONFIG_CMD_DTT | |
| 301 | #define CONFIG_CMD_EEPROM | |
| 302 | #endif | |
| 303 | ||
| fa230445 HS |
304 | |
| 305 | /* | |
| 306 | * Miscellaneous configurable options | |
| 307 | */ | |
| 6d0f6bcf JCPV |
308 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 309 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| fa230445 HS |
310 | |
| 311 | #if 0 | |
| 312 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
| 6d0f6bcf JCPV |
313 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
| 314 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 315 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| fa230445 HS |
316 | #endif |
| 317 | #endif | |
| 318 | ||
| 2694690e | 319 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 320 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| fa230445 | 321 | #else |
| 6d0f6bcf | 322 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| fa230445 | 323 | #endif |
| 6d0f6bcf JCPV |
324 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 325 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 326 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| fa230445 | 327 | |
| 6d0f6bcf JCPV |
328 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 329 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| fa230445 | 330 | |
| 6d0f6bcf | 331 | #define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ |
| fa230445 | 332 | |
| 6d0f6bcf | 333 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| fa230445 | 334 | |
| 6d0f6bcf | 335 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| fa230445 | 336 | |
| 6d0f6bcf | 337 | #define CONFIG_SYS_RESET_ADDRESS 0x40000104 /* "bad" address */ |
| fa230445 HS |
338 | |
| 339 | /* | |
| 340 | * For booting Linux, the board info and command line data | |
| 341 | * have to be in the first 8 MB of memory, since this is | |
| 342 | * the maximum mapped by the Linux kernel during initialization. | |
| 343 | */ | |
| 6d0f6bcf | 344 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| fa230445 HS |
345 | |
| 346 | /*----------------------------------------------------------------------- | |
| 347 | * CAN stuff | |
| 348 | *----------------------------------------------------------------------- | |
| 349 | */ | |
| 6d0f6bcf JCPV |
350 | #define CONFIG_SYS_CAN_BASE 0x51000000 |
| 351 | #define CONFIG_SYS_CAN_SIZE 1 | |
| 352 | #define CONFIG_SYS_CAN_BR ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK) |\ | |
| fa230445 HS |
353 | BRx_PS_8 |\ |
| 354 | BRx_MS_UPMC |\ | |
| 355 | BRx_V) | |
| 356 | ||
| 6d0f6bcf | 357 | #define CONFIG_SYS_CAN_OR (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\ |
| fa230445 HS |
358 | ORxU_BI) |
| 359 | ||
| 360 | ||
| 361 | /* What should the base address of the main FLASH be and how big is | |
| 14d0a02a | 362 | * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk |
| fa230445 HS |
363 | * The main FLASH is whichever is connected to *CS0. |
| 364 | */ | |
| 6d0f6bcf JCPV |
365 | #define CONFIG_SYS_FLASH0_BASE 0x40000000 |
| 366 | #define CONFIG_SYS_FLASH0_SIZE 32 /* 32 MB */ | |
| fa230445 HS |
367 | |
| 368 | /* Flash bank size (for preliminary settings) | |
| 369 | */ | |
| 6d0f6bcf | 370 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE |
| fa230445 HS |
371 | |
| 372 | /*----------------------------------------------------------------------- | |
| 373 | * FLASH organization | |
| 374 | */ | |
| 6d0f6bcf JCPV |
375 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
| 376 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
| fa230445 | 377 | |
| 6d0f6bcf | 378 | #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ |
| 00b1883a | 379 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ |
| 6d0f6bcf JCPV |
380 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ |
| 381 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ | |
| fa230445 | 382 | |
| 6d0f6bcf JCPV |
383 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
| 384 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
| fa230445 | 385 | |
| 6d0f6bcf | 386 | #define CONFIG_SYS_UPDATE_FLASH_SIZE |
| fa230445 | 387 | |
| 5a1aceb0 | 388 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 389 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
| 0e8d1586 JCPV |
390 | #define CONFIG_ENV_SIZE 0x20000 |
| 391 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
| 392 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) | |
| 393 | #define CONFIG_ENV_SIZE_REDUND 0x20000 | |
| fa230445 HS |
394 | |
| 395 | /* Where is the Hardwareinformation Block (from Monitor Sources) */ | |
| 396 | #define MON_RES_LENGTH (0x0003FC00) | |
| 6d0f6bcf | 397 | #define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH) |
| fa230445 | 398 | #define HWIB_INFO_LEN 512 |
| 6d0f6bcf | 399 | #define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN) |
| fa230445 HS |
400 | #define CIB_INFO_LEN 512 |
| 401 | ||
| 6d0f6bcf JCPV |
402 | #define CONFIG_SYS_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */ |
| 403 | #define CONFIG_SYS_HWINFO_SIZE 0x00000060 /* size of HW Info block */ | |
| 404 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
| fa230445 HS |
405 | |
| 406 | /*----------------------------------------------------------------------- | |
| 407 | * NAND-FLASH stuff | |
| 408 | *----------------------------------------------------------------------- | |
| 409 | */ | |
| 2694690e | 410 | #if defined(CONFIG_CMD_NAND) |
| fa230445 | 411 | |
| 6d0f6bcf JCPV |
412 | #define CONFIG_SYS_NAND_CS_DIST 0x80 |
| 413 | #define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS 0x20 | |
| 414 | #define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x40 | |
| fa230445 | 415 | |
| 6d0f6bcf | 416 | #define CONFIG_SYS_NAND_BR ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK) |\ |
| fa230445 HS |
417 | BRx_PS_8 |\ |
| 418 | BRx_MS_UPMB |\ | |
| 419 | BRx_V) | |
| 420 | ||
| 6d0f6bcf | 421 | #define CONFIG_SYS_NAND_OR (MEG_TO_AM(CONFIG_SYS_NAND_SIZE) |\ |
| fa230445 HS |
422 | ORxU_BI |\ |
| 423 | ORxU_EHTR_8IDLE) | |
| 424 | ||
| 6d0f6bcf JCPV |
425 | #define CONFIG_SYS_NAND_SIZE 1 |
| 426 | #define CONFIG_SYS_NAND0_BASE 0x50000000 | |
| 427 | #define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST) | |
| 428 | #define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST) | |
| 429 | #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) | |
| fa230445 | 430 | |
| 6d0f6bcf | 431 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ |
| fa230445 | 432 | |
| 6d0f6bcf JCPV |
433 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ |
| 434 | CONFIG_SYS_NAND1_BASE, \ | |
| 435 | CONFIG_SYS_NAND2_BASE, \ | |
| 436 | CONFIG_SYS_NAND3_BASE, \ | |
| fa230445 HS |
437 | } |
| 438 | ||
| 439 | #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0) | |
| 440 | #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr))) | |
| 441 | #define WRITE_NAND_UPM(d, adr, off) do \ | |
| 442 | { \ | |
| 443 | volatile unsigned char *addr = (unsigned char *) (adr + off); \ | |
| 444 | WRITE_NAND(d, addr); \ | |
| 445 | } while(0) | |
| 446 | ||
| a1aa0bb5 | 447 | #endif /* CONFIG_CMD_NAND */ |
| fa230445 HS |
448 | |
| 449 | #define CONFIG_PCI | |
| 450 | #ifdef CONFIG_PCI | |
| 451 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
| 452 | #define CONFIG_PCI_PNP | |
| 453 | #define CONFIG_EEPRO100 | |
| 6d0f6bcf | 454 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
| fa230445 HS |
455 | #define CONFIG_PCI_SCAN_SHOW |
| 456 | #endif | |
| 457 | ||
| 458 | /*----------------------------------------------------------------------- | |
| 459 | * Hard Reset Configuration Words | |
| 460 | * | |
| 6d0f6bcf | 461 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
| fa230445 | 462 | * defines for the various registers affected by the HRCW e.g. changing |
| 6d0f6bcf | 463 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
| fa230445 HS |
464 | */ |
| 465 | #if 0 | |
| 466 | #define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) | |
| 467 | ||
| 6d0f6bcf | 468 | # define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) |
| fa230445 | 469 | #else |
| 6d0f6bcf | 470 | #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111) |
| fa230445 HS |
471 | #endif |
| 472 | ||
| 473 | /* no slaves so just fill with zeros */ | |
| 6d0f6bcf JCPV |
474 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
| 475 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
| 476 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
| 477 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
| 478 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
| 479 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
| 480 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
| fa230445 HS |
481 | |
| 482 | /*----------------------------------------------------------------------- | |
| 483 | * Internal Memory Mapped Register | |
| 484 | */ | |
| 6d0f6bcf | 485 | #define CONFIG_SYS_IMMR 0xFFF00000 |
| fa230445 HS |
486 | |
| 487 | /*----------------------------------------------------------------------- | |
| 488 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 489 | */ | |
| 6d0f6bcf | 490 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
| 553f0982 | 491 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ |
| 6d0f6bcf | 492 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ |
| 553f0982 | 493 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) |
| 6d0f6bcf | 494 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| fa230445 HS |
495 | |
| 496 | /*----------------------------------------------------------------------- | |
| 497 | * Start addresses for the final memory configuration | |
| 498 | * (Set up by the startup code) | |
| 6d0f6bcf | 499 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| fa230445 | 500 | */ |
| 6d0f6bcf JCPV |
501 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 502 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE | |
| 14d0a02a | 503 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| 6d0f6bcf JCPV |
504 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
| 505 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
| fa230445 | 506 | |
| fa230445 HS |
507 | /*----------------------------------------------------------------------- |
| 508 | * Cache Configuration | |
| 509 | */ | |
| 6d0f6bcf | 510 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
| 2694690e | 511 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 512 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| fa230445 HS |
513 | #endif |
| 514 | ||
| 515 | /*----------------------------------------------------------------------- | |
| 516 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
| 517 | *----------------------------------------------------------------------- | |
| 518 | * HID0 also contains cache control - initially enable both caches and | |
| 519 | * invalidate contents, then the final state leaves only the instruction | |
| 520 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
| 521 | * but Soft reset does not. | |
| 522 | * | |
| 523 | * HID1 has only read-only information - nothing to set. | |
| 524 | */ | |
| 6d0f6bcf | 525 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
| fa230445 | 526 | HID0_IFEM|HID0_ABE) |
| 6d0f6bcf JCPV |
527 | #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) |
| 528 | #define CONFIG_SYS_HID2 0 | |
| fa230445 HS |
529 | |
| 530 | /*----------------------------------------------------------------------- | |
| 531 | * RMR - Reset Mode Register 5-5 | |
| 532 | *----------------------------------------------------------------------- | |
| 533 | * turn on Checkstop Reset Enable | |
| 534 | */ | |
| 6d0f6bcf | 535 | #define CONFIG_SYS_RMR RMR_CSRE |
| fa230445 HS |
536 | |
| 537 | /*----------------------------------------------------------------------- | |
| 538 | * BCR - Bus Configuration 4-25 | |
| 539 | *----------------------------------------------------------------------- | |
| 540 | */ | |
| 6d0f6bcf | 541 | #define CONFIG_SYS_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */ |
| fa230445 | 542 | #define BCR_APD01 0x10000000 |
| 6d0f6bcf | 543 | #define CONFIG_SYS_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */ |
| fa230445 HS |
544 | |
| 545 | /*----------------------------------------------------------------------- | |
| 546 | * SIUMCR - SIU Module Configuration 4-31 | |
| 547 | *----------------------------------------------------------------------- | |
| 548 | */ | |
| 549 | #if defined(CONFIG_BOARD_GET_CPU_CLK_F) | |
| 6d0f6bcf JCPV |
550 | #define CONFIG_SYS_SIUMCR_LOW (SIUMCR_DPPC00) |
| 551 | #define CONFIG_SYS_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE) | |
| fa230445 | 552 | #else |
| 6d0f6bcf | 553 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00) |
| fa230445 HS |
554 | #endif |
| 555 | ||
| 556 | /*----------------------------------------------------------------------- | |
| 557 | * SYPCR - System Protection Control 4-35 | |
| 558 | * SYPCR can only be written once after reset! | |
| 559 | *----------------------------------------------------------------------- | |
| 560 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
| 561 | */ | |
| 562 | #if defined(CONFIG_WATCHDOG) | |
| 6d0f6bcf | 563 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
| fa230445 HS |
564 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
| 565 | #else | |
| 6d0f6bcf | 566 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
| fa230445 HS |
567 | SYPCR_SWRI|SYPCR_SWP) |
| 568 | #endif /* CONFIG_WATCHDOG */ | |
| 569 | ||
| 570 | /*----------------------------------------------------------------------- | |
| 571 | * TMCNTSC - Time Counter Status and Control 4-40 | |
| 572 | *----------------------------------------------------------------------- | |
| 573 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
| 574 | * and enable Time Counter | |
| 575 | */ | |
| 6d0f6bcf | 576 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
| fa230445 HS |
577 | |
| 578 | /*----------------------------------------------------------------------- | |
| 579 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
| 580 | *----------------------------------------------------------------------- | |
| 581 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
| 582 | * Periodic timer | |
| 583 | */ | |
| 6d0f6bcf | 584 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
| fa230445 HS |
585 | |
| 586 | /*----------------------------------------------------------------------- | |
| 587 | * SCCR - System Clock Control 9-8 | |
| 588 | *----------------------------------------------------------------------- | |
| 589 | * Ensure DFBRG is Divide by 16 | |
| 590 | */ | |
| 6d0f6bcf | 591 | #define CONFIG_SYS_SCCR SCCR_DFBRG01 |
| fa230445 HS |
592 | |
| 593 | /*----------------------------------------------------------------------- | |
| 594 | * RCCR - RISC Controller Configuration 13-7 | |
| 595 | *----------------------------------------------------------------------- | |
| 596 | */ | |
| 6d0f6bcf | 597 | #define CONFIG_SYS_RCCR 0 |
| fa230445 HS |
598 | |
| 599 | /* | |
| 600 | * Init Memory Controller: | |
| 601 | * | |
| 602 | * Bank Bus Machine PortSz Device | |
| 603 | * ---- --- ------- ------ ------ | |
| 604 | * 0 60x GPCM 32 bit FLASH | |
| 605 | * 1 60x SDRAM 64 bit SDRAM | |
| 606 | * 2 60x UPMB 8 bit NAND | |
| 9c0f42ec | 607 | * 3 60x UPMC 8 bit CAN |
| fa230445 HS |
608 | * |
| 609 | */ | |
| 610 | ||
| 611 | /* Initialize SDRAM | |
| 612 | */ | |
| 6d0f6bcf | 613 | #undef CONFIG_SYS_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */ |
| fa230445 HS |
614 | |
| 615 | #define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */ | |
| 616 | ||
| 617 | /* Minimum mask to separate preliminary | |
| 618 | * address ranges for CS[0:2] | |
| 619 | */ | |
| 6d0f6bcf | 620 | #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ |
| fa230445 | 621 | |
| 6d0f6bcf | 622 | #define CONFIG_SYS_MPTPR 0x4000 |
| fa230445 HS |
623 | |
| 624 | /*----------------------------------------------------------------------------- | |
| 625 | * Address for Mode Register Set (MRS) command | |
| 626 | *----------------------------------------------------------------------------- | |
| 627 | * In fact, the address is rather configuration data presented to the SDRAM on | |
| 628 | * its address lines. Because the address lines may be mux'ed externally either | |
| 629 | * for 8 column or 9 column devices, some bits appear twice in the 8260's | |
| 630 | * address: | |
| 631 | * | |
| 632 | * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | | |
| 633 | * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | | |
| 634 | * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | | |
| 635 | * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | | |
| 636 | * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | | |
| 637 | *----------------------------------------------------------------------------- | |
| 638 | */ | |
| 6d0f6bcf | 639 | #define CONFIG_SYS_MRS_OFFS 0x00000110 |
| fa230445 | 640 | |
| fa230445 HS |
641 | /* Bank 0 - FLASH |
| 642 | */ | |
| 6d0f6bcf | 643 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
| fa230445 HS |
644 | BRx_PS_32 |\ |
| 645 | BRx_MS_GPCM_P |\ | |
| 646 | BRx_V) | |
| 647 | ||
| 6d0f6bcf | 648 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
| fa230445 HS |
649 | ORxG_CSNT |\ |
| 650 | ORxG_ACS_DIV4 |\ | |
| 651 | ORxG_SCY_8_CLK |\ | |
| 652 | ORxG_TRLX) | |
| 653 | ||
| 654 | /* SDRAM on TQM8272 can have either 8 or 9 columns. | |
| 655 | * The number affects configuration values. | |
| 656 | */ | |
| 657 | ||
| 658 | /* Bank 1 - 60x bus SDRAM | |
| 659 | */ | |
| 6d0f6bcf JCPV |
660 | #define CONFIG_SYS_PSRT 0x20 /* Low Value */ |
| 661 | /* #define CONFIG_SYS_PSRT 0x10 Fast Value */ | |
| 662 | #define CONFIG_SYS_LSRT 0x20 /* Local Bus */ | |
| 663 | #ifndef CONFIG_SYS_RAMBOOT | |
| 664 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ | |
| fa230445 HS |
665 | BRx_PS_64 |\ |
| 666 | BRx_MS_SDRAM_P |\ | |
| 667 | BRx_V) | |
| 668 | ||
| 6d0f6bcf | 669 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL |
| fa230445 HS |
670 | |
| 671 | /* SDRAM initialization values for 8-column chips | |
| 672 | */ | |
| 6d0f6bcf | 673 | #define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
| fa230445 HS |
674 | ORxS_BPD_4 |\ |
| 675 | ORxS_ROWST_PBI1_A7 |\ | |
| 676 | ORxS_NUMR_12) | |
| 677 | ||
| 6d0f6bcf | 678 | #define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ |
| fa230445 HS |
679 | PSDMR_SDAM_A15_IS_A5 |\ |
| 680 | PSDMR_BSMA_A12_A14 |\ | |
| 681 | PSDMR_SDA10_PBI1_A8 |\ | |
| 682 | PSDMR_RFRC_7_CLK |\ | |
| 683 | PSDMR_PRETOACT_2W |\ | |
| 684 | PSDMR_ACTTORW_2W |\ | |
| 685 | PSDMR_LDOTOPRE_1C |\ | |
| 686 | PSDMR_WRC_2C |\ | |
| 687 | PSDMR_EAMUX |\ | |
| 688 | PSDMR_BUFCMD |\ | |
| 689 | PSDMR_CL_2) | |
| 690 | ||
| 691 | ||
| 692 | /* SDRAM initialization values for 9-column chips | |
| 693 | */ | |
| 6d0f6bcf | 694 | #define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
| fa230445 HS |
695 | ORxS_BPD_4 |\ |
| 696 | ORxS_ROWST_PBI1_A5 |\ | |
| 697 | ORxS_NUMR_13) | |
| 698 | ||
| 6d0f6bcf | 699 | #define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ |
| fa230445 HS |
700 | PSDMR_SDAM_A16_IS_A5 |\ |
| 701 | PSDMR_BSMA_A12_A14 |\ | |
| 702 | PSDMR_SDA10_PBI1_A7 |\ | |
| 703 | PSDMR_RFRC_7_CLK |\ | |
| 704 | PSDMR_PRETOACT_2W |\ | |
| 705 | PSDMR_ACTTORW_2W |\ | |
| 706 | PSDMR_LDOTOPRE_1C |\ | |
| 707 | PSDMR_WRC_2C |\ | |
| 708 | PSDMR_EAMUX |\ | |
| 709 | PSDMR_BUFCMD |\ | |
| 710 | PSDMR_CL_2) | |
| 711 | ||
| 6d0f6bcf | 712 | #define CONFIG_SYS_OR1_10COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
| fa230445 HS |
713 | ORxS_BPD_4 |\ |
| 714 | ORxS_ROWST_PBI1_A4 |\ | |
| 715 | ORxS_NUMR_13) | |
| 716 | ||
| 6d0f6bcf | 717 | #define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\ |
| fa230445 HS |
718 | PSDMR_SDAM_A17_IS_A5 |\ |
| 719 | PSDMR_BSMA_A12_A14 |\ | |
| 720 | PSDMR_SDA10_PBI1_A4 |\ | |
| 721 | PSDMR_RFRC_6_CLK |\ | |
| 722 | PSDMR_PRETOACT_2W |\ | |
| 723 | PSDMR_ACTTORW_2W |\ | |
| 724 | PSDMR_LDOTOPRE_1C |\ | |
| 725 | PSDMR_WRC_2C |\ | |
| 726 | PSDMR_EAMUX |\ | |
| 727 | PSDMR_BUFCMD |\ | |
| 728 | PSDMR_CL_2) | |
| 729 | ||
| fa230445 HS |
730 | #define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ |
| 731 | #define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ | |
| 732 | #define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ | |
| 733 | #define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */ | |
| 734 | #define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */ | |
| 735 | #define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */ | |
| 736 | ||
| 737 | #define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */ | |
| 738 | #define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */ | |
| 739 | #define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */ | |
| 740 | #define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */ | |
| 741 | #define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */ | |
| 742 | #define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */ | |
| 743 | ||
| 744 | #define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */ | |
| 745 | #define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */ | |
| 746 | #define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */ | |
| 747 | #define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */ | |
| 748 | #define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */ | |
| 749 | #define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */ | |
| 750 | ||
| 751 | #define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */ | |
| 752 | #define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */ | |
| 753 | #define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */ | |
| 754 | #define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */ | |
| 755 | #define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */ | |
| 756 | #define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */ | |
| 757 | ||
| 6d0f6bcf | 758 | #endif /* CONFIG_SYS_RAMBOOT */ |
| fa230445 HS |
759 | |
| 760 | #endif /* __CONFIG_H */ |