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Commit | Line | Data |
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e6f2e902 MB |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
e6f2e902 MB |
6 | */ |
7 | ||
8 | /* | |
9 | * TQM8349 board configuration file | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
e6f2e902 MB |
15 | /* |
16 | * High Level Configuration Options | |
17 | */ | |
18 | #define CONFIG_E300 1 /* E300 Family */ | |
0f898604 | 19 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
2c7920af | 20 | #define CONFIG_MPC834x 1 /* MPC834x specific */ |
9ca880a2 | 21 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
e6f2e902 MB |
22 | #define CONFIG_TQM834X 1 /* TQM834X board specific */ |
23 | ||
2ae18241 WD |
24 | #define CONFIG_SYS_TEXT_BASE 0x80000000 |
25 | ||
16263087 | 26 | /* IMMR Base Address Register, use Freescale default: 0xff400000 */ |
6d0f6bcf | 27 | #define CONFIG_SYS_IMMR 0xff400000 |
e6f2e902 MB |
28 | |
29 | /* System clock. Primary input clock when in PCI host mode */ | |
30 | #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ | |
31 | ||
32 | /* | |
33 | * Local Bus LCRR | |
34 | * LCRR: DLL bypass, Clock divider is 8 | |
35 | * | |
36 | * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz | |
37 | * | |
38 | * External Local Bus rate is | |
39 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
40 | */ | |
c7190f02 KP |
41 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
42 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
e6f2e902 MB |
43 | |
44 | /* board pre init: do not call, nothing to do */ | |
45 | #undef CONFIG_BOARD_EARLY_INIT_F | |
46 | ||
47 | /* detect the number of flash banks */ | |
48 | #define CONFIG_BOARD_EARLY_INIT_R | |
49 | ||
50 | /* | |
51 | * DDR Setup | |
52 | */ | |
df939e16 JH |
53 | /* DDR is system memory*/ |
54 | #define CONFIG_SYS_DDR_BASE 0x00000000 | |
55 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
6d0f6bcf | 56 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
df939e16 JH |
57 | #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ |
58 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
59 | #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ | |
e6f2e902 | 60 | |
df939e16 | 61 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
6d0f6bcf JCPV |
62 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
63 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
e6f2e902 MB |
64 | |
65 | /* | |
66 | * FLASH on the Local Bus | |
67 | */ | |
df939e16 JH |
68 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
69 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf JCPV |
70 | #undef CONFIG_SYS_FLASH_CHECKSUM |
71 | #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ | |
72 | #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ | |
df939e16 | 73 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ |
a3455c00 | 74 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
e6f2e902 MB |
75 | |
76 | /* | |
77 | * FLASH bank number detection | |
78 | */ | |
79 | ||
80 | /* | |
df939e16 JH |
81 | * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of |
82 | * Flash banks has to be determined at runtime and stored in a gloabl variable | |
83 | * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is | |
84 | * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array | |
85 | * flash_info, and should be made sufficiently large to accomodate the number | |
86 | * of banks that might actually be detected. Since most (all?) Flash related | |
87 | * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on | |
88 | * the board, it is defined as tqm834x_num_flash_banks. | |
e6f2e902 | 89 | */ |
6d0f6bcf | 90 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 |
e6f2e902 | 91 | |
df939e16 | 92 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ |
e6f2e902 MB |
93 | |
94 | /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ | |
df939e16 JH |
95 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ |
96 | | BR_MS_GPCM \ | |
97 | | BR_PS_32 \ | |
98 | | BR_V) | |
e6f2e902 MB |
99 | |
100 | /* FLASH timing (0x0000_0c54) */ | |
df939e16 JH |
101 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ |
102 | | OR_GPCM_ACS_DIV4 \ | |
103 | | OR_GPCM_SCY_5 \ | |
104 | | OR_GPCM_TRLX) | |
e6f2e902 | 105 | |
7d6a0982 | 106 | #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ |
e6f2e902 | 107 | |
df939e16 JH |
108 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ |
109 | | CONFIG_SYS_OR_TIMING_FLASH) | |
e6f2e902 | 110 | |
7d6a0982 | 111 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) |
6902df56 | 112 | |
df939e16 JH |
113 | /* Window base at flash base */ |
114 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
e6f2e902 MB |
115 | |
116 | /* disable remaining mappings */ | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_BR1_PRELIM 0x00000000 |
118 | #define CONFIG_SYS_OR1_PRELIM 0x00000000 | |
119 | #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 | |
120 | #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 | |
121 | ||
122 | #define CONFIG_SYS_BR2_PRELIM 0x00000000 | |
123 | #define CONFIG_SYS_OR2_PRELIM 0x00000000 | |
124 | #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 | |
125 | #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 | |
126 | ||
127 | #define CONFIG_SYS_BR3_PRELIM 0x00000000 | |
128 | #define CONFIG_SYS_OR3_PRELIM 0x00000000 | |
129 | #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 | |
130 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 | |
e6f2e902 MB |
131 | |
132 | /* | |
133 | * Monitor config | |
134 | */ | |
14d0a02a | 135 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
e6f2e902 | 136 | |
6d0f6bcf | 137 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
4681e673 | 138 | # define CONFIG_SYS_RAMBOOT |
e6f2e902 | 139 | #else |
4681e673 | 140 | # undef CONFIG_SYS_RAMBOOT |
e6f2e902 MB |
141 | #endif |
142 | ||
6d0f6bcf | 143 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
df939e16 JH |
144 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ |
145 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
e6f2e902 | 146 | |
df939e16 JH |
147 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
148 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 149 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
e6f2e902 | 150 | |
df939e16 JH |
151 | /* Reserve 384 kB = 3 sect. for Mon */ |
152 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) | |
153 | /* Reserve 512 kB for malloc */ | |
154 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
e6f2e902 MB |
155 | |
156 | /* | |
157 | * Serial Port | |
158 | */ | |
159 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_NS16550 |
161 | #define CONFIG_SYS_NS16550_SERIAL | |
162 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
163 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
e6f2e902 | 164 | |
6d0f6bcf | 165 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
df939e16 | 166 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
e6f2e902 | 167 | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
169 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
e6f2e902 MB |
170 | |
171 | /* | |
172 | * I2C | |
173 | */ | |
00f792e0 HS |
174 | #define CONFIG_SYS_I2C |
175 | #define CONFIG_SYS_I2C_FSL | |
176 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
177 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
178 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
e6f2e902 MB |
179 | |
180 | /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ | |
df939e16 JH |
181 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
182 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ | |
183 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ | |
184 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ | |
185 | #define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */ | |
e6f2e902 MB |
186 | |
187 | /* I2C RTC */ | |
df939e16 JH |
188 | #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ |
189 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
e6f2e902 MB |
190 | |
191 | /* I2C SYSMON (LM75) */ | |
df939e16 JH |
192 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
193 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
195 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
df939e16 | 196 | #define CONFIG_SYS_DTT_HYSTERESIS 3 |
e6f2e902 MB |
197 | |
198 | /* | |
199 | * TSEC | |
200 | */ | |
53677ef1 | 201 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
e6f2e902 MB |
202 | #define CONFIG_MII |
203 | ||
6d0f6bcf | 204 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
df939e16 | 205 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 206 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
df939e16 | 207 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) |
e6f2e902 MB |
208 | |
209 | #if defined(CONFIG_TSEC_ENET) | |
210 | ||
255a3577 KP |
211 | #define CONFIG_TSEC1 1 |
212 | #define CONFIG_TSEC1_NAME "TSEC0" | |
213 | #define CONFIG_TSEC2 1 | |
214 | #define CONFIG_TSEC2_NAME "TSEC1" | |
df939e16 JH |
215 | #define TSEC1_PHY_ADDR 2 |
216 | #define TSEC2_PHY_ADDR 1 | |
217 | #define TSEC1_PHYIDX 0 | |
218 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
219 | #define TSEC1_FLAGS TSEC_GIGABIT |
220 | #define TSEC2_FLAGS TSEC_GIGABIT | |
e6f2e902 MB |
221 | |
222 | /* Options are: TSEC[0-1] */ | |
df939e16 | 223 | #define CONFIG_ETHPRIME "TSEC0" |
e6f2e902 MB |
224 | |
225 | #endif /* CONFIG_TSEC_ENET */ | |
226 | ||
227 | /* | |
228 | * General PCI | |
229 | * Addresses are mapped 1-1. | |
230 | */ | |
6902df56 RJ |
231 | #define CONFIG_PCI |
232 | ||
e6f2e902 MB |
233 | #if defined(CONFIG_PCI) |
234 | ||
df939e16 JH |
235 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
236 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6902df56 RJ |
237 | |
238 | /* PCI1 host bridge */ | |
df939e16 JH |
239 | #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 |
240 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
241 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
242 | #define CONFIG_SYS_PCI1_MMIO_BASE \ | |
243 | (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
244 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
245 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
246 | #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 | |
247 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
248 | #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ | |
e6f2e902 | 249 | |
e6f2e902 | 250 | #undef CONFIG_EEPRO100 |
63ff004c | 251 | #define CONFIG_EEPRO100 |
e6f2e902 MB |
252 | #undef CONFIG_TULIP |
253 | ||
254 | #if !defined(CONFIG_PCI_PNP) | |
6d0f6bcf JCPV |
255 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE |
256 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE | |
6902df56 | 257 | #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ |
e6f2e902 MB |
258 | #endif |
259 | ||
6d0f6bcf | 260 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
e6f2e902 MB |
261 | |
262 | #endif /* CONFIG_PCI */ | |
263 | ||
264 | /* | |
265 | * Environment | |
266 | */ | |
df939e16 JH |
267 | #define CONFIG_ENV_IS_IN_FLASH 1 |
268 | #define CONFIG_ENV_ADDR \ | |
269 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
270 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ | |
271 | #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ | |
929b79a0 WD |
272 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
273 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
274 | ||
df939e16 JH |
275 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
276 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
e6f2e902 | 277 | |
a1aa0bb5 JL |
278 | /* |
279 | * BOOTP options | |
280 | */ | |
281 | #define CONFIG_BOOTP_BOOTFILESIZE | |
282 | #define CONFIG_BOOTP_BOOTPATH | |
283 | #define CONFIG_BOOTP_GATEWAY | |
284 | #define CONFIG_BOOTP_HOSTNAME | |
285 | ||
286 | ||
2694690e JL |
287 | /* |
288 | * Command line configuration. | |
289 | */ | |
290 | #include <config_cmd_default.h> | |
291 | ||
4681e673 | 292 | #define CONFIG_CMD_ASKENV |
2694690e | 293 | #define CONFIG_CMD_DATE |
4681e673 | 294 | #define CONFIG_CMD_DHCP |
2694690e JL |
295 | #define CONFIG_CMD_DTT |
296 | #define CONFIG_CMD_EEPROM | |
297 | #define CONFIG_CMD_I2C | |
4681e673 | 298 | #define CONFIG_CMD_NFS |
2694690e JL |
299 | #define CONFIG_CMD_JFFS2 |
300 | #define CONFIG_CMD_MII | |
301 | #define CONFIG_CMD_PING | |
4681e673 WD |
302 | #define CONFIG_CMD_REGINFO |
303 | #define CONFIG_CMD_SNTP | |
e6f2e902 MB |
304 | |
305 | #if defined(CONFIG_PCI) | |
2694690e | 306 | #define CONFIG_CMD_PCI |
e6f2e902 MB |
307 | #endif |
308 | ||
6d0f6bcf | 309 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 310 | #undef CONFIG_CMD_SAVEENV |
2694690e | 311 | #undef CONFIG_CMD_LOADS |
e6f2e902 MB |
312 | #endif |
313 | ||
e6f2e902 MB |
314 | /* |
315 | * Miscellaneous configurable options | |
316 | */ | |
df939e16 JH |
317 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
318 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
e6f2e902 | 319 | |
df939e16 JH |
320 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
321 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
a059e90e | 322 | |
df939e16 | 323 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
2751a95a | 324 | |
2694690e | 325 | #if defined(CONFIG_CMD_KGDB) |
df939e16 | 326 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
e6f2e902 | 327 | #else |
df939e16 | 328 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
e6f2e902 MB |
329 | #endif |
330 | ||
df939e16 JH |
331 | /* Print Buffer Size */ |
332 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
333 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
334 | /* Boot Argument Buffer Size */ | |
335 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
e6f2e902 | 336 | |
df939e16 | 337 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
e6f2e902 | 338 | |
4681e673 WD |
339 | /* pass open firmware flat tree */ |
340 | #define CONFIG_OF_LIBFDT 1 | |
341 | #define CONFIG_OF_BOARD_SETUP 1 | |
342 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
343 | ||
e6f2e902 MB |
344 | /* |
345 | * For booting Linux, the board info and command line data | |
9f530d59 | 346 | * have to be in the first 256 MB of memory, since this is |
e6f2e902 MB |
347 | * the maximum mapped by the Linux kernel during initialization. |
348 | */ | |
df939e16 JH |
349 | /* Initial Memory map for Linux */ |
350 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
e6f2e902 | 351 | |
6d0f6bcf | 352 | #define CONFIG_SYS_HRCW_LOW (\ |
e6f2e902 MB |
353 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
354 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
355 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
356 | HRCWL_VCO_1X2 |\ | |
357 | HRCWL_CORE_TO_CSB_2X1) | |
358 | ||
359 | #if defined(PCI_64BIT) | |
6d0f6bcf | 360 | #define CONFIG_SYS_HRCW_HIGH (\ |
e6f2e902 MB |
361 | HRCWH_PCI_HOST |\ |
362 | HRCWH_64_BIT_PCI |\ | |
363 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
364 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
365 | HRCWH_CORE_ENABLE |\ | |
366 | HRCWH_FROM_0X00000100 |\ | |
367 | HRCWH_BOOTSEQ_DISABLE |\ | |
368 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
369 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
370 | HRCWH_TSEC1M_IN_GMII |\ | |
df939e16 | 371 | HRCWH_TSEC2M_IN_GMII) |
e6f2e902 | 372 | #else |
6d0f6bcf | 373 | #define CONFIG_SYS_HRCW_HIGH (\ |
e6f2e902 MB |
374 | HRCWH_PCI_HOST |\ |
375 | HRCWH_32_BIT_PCI |\ | |
376 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
6902df56 | 377 | HRCWH_PCI2_ARBITER_DISABLE |\ |
e6f2e902 MB |
378 | HRCWH_CORE_ENABLE |\ |
379 | HRCWH_FROM_0X00000100 |\ | |
380 | HRCWH_BOOTSEQ_DISABLE |\ | |
381 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
382 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
383 | HRCWH_TSEC1M_IN_GMII |\ | |
df939e16 | 384 | HRCWH_TSEC2M_IN_GMII) |
e6f2e902 MB |
385 | #endif |
386 | ||
9260a561 | 387 | /* System IO Config */ |
3c9b1ee1 | 388 | #define CONFIG_SYS_SICRH 0 |
6d0f6bcf | 389 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
9260a561 | 390 | |
e6f2e902 | 391 | /* i-cache and d-cache disabled */ |
6d0f6bcf | 392 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
1a2e203b KP |
393 | #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ |
394 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 395 | #define CONFIG_SYS_HID2 HID2_HBE |
e6f2e902 | 396 | |
31d82672 BB |
397 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
398 | ||
2688e2f9 | 399 | /* DDR 0 - 512M */ |
df939e16 | 400 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 401 | | BATL_PP_RW \ |
df939e16 JH |
402 | | BATL_MEMCOHERENCE) |
403 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
404 | | BATU_BL_256M \ | |
405 | | BATU_VS \ | |
406 | | BATU_VP) | |
407 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ | |
72cd4087 | 408 | | BATL_PP_RW \ |
df939e16 JH |
409 | | BATL_MEMCOHERENCE) |
410 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ | |
411 | | BATU_BL_256M \ | |
412 | | BATU_VS \ | |
413 | | BATU_VP) | |
2688e2f9 KG |
414 | |
415 | /* stack in DCACHE @ 512M (no backing mem) */ | |
df939e16 | 416 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ |
72cd4087 | 417 | | BATL_PP_RW \ |
df939e16 JH |
418 | | BATL_MEMCOHERENCE) |
419 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ | |
420 | | BATU_BL_128K \ | |
421 | | BATU_VS \ | |
422 | | BATU_VP) | |
2688e2f9 KG |
423 | |
424 | /* PCI */ | |
6fe16a87 | 425 | #ifdef CONFIG_PCI |
842033e6 | 426 | #define CONFIG_PCI_INDIRECT_BRIDGE |
df939e16 | 427 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 428 | | BATL_PP_RW \ |
df939e16 JH |
429 | | BATL_MEMCOHERENCE) |
430 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ | |
431 | | BATU_BL_256M \ | |
432 | | BATU_VS \ | |
433 | | BATU_VP) | |
434 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 435 | | BATL_PP_RW \ |
df939e16 JH |
436 | | BATL_MEMCOHERENCE \ |
437 | | BATL_GUARDEDSTORAGE) | |
438 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
439 | | BATU_BL_256M \ | |
440 | | BATU_VS \ | |
441 | | BATU_VP) | |
442 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ | |
72cd4087 | 443 | | BATL_PP_RW \ |
df939e16 JH |
444 | | BATL_CACHEINHIBIT \ |
445 | | BATL_GUARDEDSTORAGE) | |
446 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ | |
447 | | BATU_BL_16M \ | |
448 | | BATU_VS \ | |
449 | | BATU_VP) | |
6fe16a87 | 450 | #else |
6d0f6bcf JCPV |
451 | #define CONFIG_SYS_IBAT3L (0) |
452 | #define CONFIG_SYS_IBAT3U (0) | |
453 | #define CONFIG_SYS_IBAT4L (0) | |
454 | #define CONFIG_SYS_IBAT4U (0) | |
455 | #define CONFIG_SYS_IBAT5L (0) | |
456 | #define CONFIG_SYS_IBAT5U (0) | |
6fe16a87 | 457 | #endif |
2688e2f9 KG |
458 | |
459 | /* IMMRBAR */ | |
df939e16 | 460 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ |
72cd4087 | 461 | | BATL_PP_RW \ |
df939e16 JH |
462 | | BATL_CACHEINHIBIT \ |
463 | | BATL_GUARDEDSTORAGE) | |
464 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ | |
465 | | BATU_BL_1M \ | |
466 | | BATU_VS \ | |
467 | | BATU_VP) | |
2688e2f9 KG |
468 | |
469 | /* FLASH */ | |
df939e16 | 470 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 471 | | BATL_PP_RW \ |
df939e16 JH |
472 | | BATL_CACHEINHIBIT \ |
473 | | BATL_GUARDEDSTORAGE) | |
474 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ | |
475 | | BATU_BL_256M \ | |
476 | | BATU_VS \ | |
477 | | BATU_VP) | |
6d0f6bcf JCPV |
478 | |
479 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
480 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
481 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
482 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
483 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
484 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
485 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
486 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
487 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
488 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
489 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
490 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
491 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
492 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
493 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
494 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
2688e2f9 | 495 | |
2694690e | 496 | #if defined(CONFIG_CMD_KGDB) |
e6f2e902 MB |
497 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
498 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
499 | #endif | |
500 | ||
501 | /* | |
502 | * Environment Configuration | |
503 | */ | |
504 | ||
df939e16 JH |
505 | /* default location for tftp and bootm */ |
506 | #define CONFIG_LOADADDR 400000 | |
e6f2e902 MB |
507 | |
508 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
df939e16 | 509 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
e6f2e902 MB |
510 | |
511 | #define CONFIG_BAUDRATE 115200 | |
512 | ||
513 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 514 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
e6f2e902 MB |
515 | "echo" |
516 | ||
517 | #undef CONFIG_BOOTARGS | |
518 | ||
519 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
520 | "netdev=eth0\0" \ | |
b931b3a9 | 521 | "hostname=tqm834x\0" \ |
e6f2e902 | 522 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b | 523 | "nfsroot=${serverip}:${rootpath}\0" \ |
e6f2e902 | 524 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
525 | "addip=setenv bootargs ${bootargs} " \ |
526 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
527 | ":${hostname}:${netdev}:off panic=1\0" \ | |
df939e16 | 528 | "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ |
4681e673 | 529 | "flash_nfs_old=run nfsargs addip addcons;" \ |
fe126d8b | 530 | "bootm ${kernel_addr}\0" \ |
4681e673 WD |
531 | "flash_nfs=run nfsargs addip addcons;" \ |
532 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
533 | "flash_self_old=run ramargs addip addcons;" \ | |
fe126d8b | 534 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
4681e673 WD |
535 | "flash_self=run ramargs addip addcons;" \ |
536 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
537 | "net_nfs_old=tftp 400000 ${bootfile};" \ | |
538 | "run nfsargs addip addcons;bootm\0" \ | |
539 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
540 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
541 | "run nfsargs addip addcons; " \ | |
542 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
e6f2e902 | 543 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
4681e673 WD |
544 | "bootfile=tqm834x/uImage\0" \ |
545 | "fdtfile=tqm834x/tqm834x.dtb\0" \ | |
546 | "kernel_addr_r=400000\0" \ | |
547 | "fdt_addr_r=600000\0" \ | |
548 | "ramdisk_addr_r=800000\0" \ | |
549 | "kernel_addr=800C0000\0" \ | |
550 | "fdt_addr=800A0000\0" \ | |
551 | "ramdisk_addr=80300000\0" \ | |
552 | "u-boot=tqm834x/u-boot.bin\0" \ | |
553 | "load=tftp 200000 ${u-boot}\0" \ | |
554 | "update=protect off 80000000 +${filesize};" \ | |
555 | "era 80000000 +${filesize};" \ | |
556 | "cp.b 200000 80000000 ${filesize}\0" \ | |
d8ab58b2 | 557 | "upd=run load update\0" \ |
e6f2e902 MB |
558 | "" |
559 | ||
560 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
561 | ||
562 | /* | |
563 | * JFFS2 partitions | |
564 | */ | |
565 | /* mtdparts command line support */ | |
68d7d651 | 566 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
567 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
568 | #define CONFIG_FLASH_CFI_MTD | |
e6f2e902 MB |
569 | #define MTDIDS_DEFAULT "nor0=TQM834x-0" |
570 | ||
571 | /* default mtd partition table */ | |
df939e16 JH |
572 | #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \ |
573 | "1m(kernel),2m(initrd)," \ | |
574 | "-(user);" \ | |
e6f2e902 MB |
575 | |
576 | #endif /* __CONFIG_H */ |