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Commit | Line | Data |
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e6f2e902 MB |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
e6f2e902 MB |
6 | */ |
7 | ||
8 | /* | |
9 | * TQM8349 board configuration file | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
e6f2e902 MB |
15 | /* |
16 | * High Level Configuration Options | |
17 | */ | |
18 | #define CONFIG_E300 1 /* E300 Family */ | |
2c7920af | 19 | #define CONFIG_MPC834x 1 /* MPC834x specific */ |
9ca880a2 | 20 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
e6f2e902 MB |
21 | #define CONFIG_TQM834X 1 /* TQM834X board specific */ |
22 | ||
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0x80000000 |
24 | ||
16263087 | 25 | /* IMMR Base Address Register, use Freescale default: 0xff400000 */ |
6d0f6bcf | 26 | #define CONFIG_SYS_IMMR 0xff400000 |
e6f2e902 MB |
27 | |
28 | /* System clock. Primary input clock when in PCI host mode */ | |
29 | #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ | |
30 | ||
31 | /* | |
32 | * Local Bus LCRR | |
33 | * LCRR: DLL bypass, Clock divider is 8 | |
34 | * | |
35 | * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz | |
36 | * | |
37 | * External Local Bus rate is | |
38 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
39 | */ | |
c7190f02 KP |
40 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
41 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
e6f2e902 MB |
42 | |
43 | /* board pre init: do not call, nothing to do */ | |
44 | #undef CONFIG_BOARD_EARLY_INIT_F | |
45 | ||
46 | /* detect the number of flash banks */ | |
47 | #define CONFIG_BOARD_EARLY_INIT_R | |
48 | ||
49 | /* | |
50 | * DDR Setup | |
51 | */ | |
df939e16 JH |
52 | /* DDR is system memory*/ |
53 | #define CONFIG_SYS_DDR_BASE 0x00000000 | |
54 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
6d0f6bcf | 55 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
df939e16 JH |
56 | #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ |
57 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
58 | #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ | |
e6f2e902 | 59 | |
df939e16 | 60 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
62 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
e6f2e902 MB |
63 | |
64 | /* | |
65 | * FLASH on the Local Bus | |
66 | */ | |
df939e16 JH |
67 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
68 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf JCPV |
69 | #undef CONFIG_SYS_FLASH_CHECKSUM |
70 | #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ | |
71 | #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ | |
df939e16 | 72 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ |
a3455c00 | 73 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
e6f2e902 MB |
74 | |
75 | /* | |
76 | * FLASH bank number detection | |
77 | */ | |
78 | ||
79 | /* | |
df939e16 JH |
80 | * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of |
81 | * Flash banks has to be determined at runtime and stored in a gloabl variable | |
82 | * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is | |
83 | * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array | |
84 | * flash_info, and should be made sufficiently large to accomodate the number | |
85 | * of banks that might actually be detected. Since most (all?) Flash related | |
86 | * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on | |
87 | * the board, it is defined as tqm834x_num_flash_banks. | |
e6f2e902 | 88 | */ |
6d0f6bcf | 89 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 |
e6f2e902 | 90 | |
df939e16 | 91 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ |
e6f2e902 MB |
92 | |
93 | /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ | |
df939e16 JH |
94 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ |
95 | | BR_MS_GPCM \ | |
96 | | BR_PS_32 \ | |
97 | | BR_V) | |
e6f2e902 MB |
98 | |
99 | /* FLASH timing (0x0000_0c54) */ | |
df939e16 JH |
100 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ |
101 | | OR_GPCM_ACS_DIV4 \ | |
102 | | OR_GPCM_SCY_5 \ | |
103 | | OR_GPCM_TRLX) | |
e6f2e902 | 104 | |
7d6a0982 | 105 | #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ |
e6f2e902 | 106 | |
df939e16 JH |
107 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ |
108 | | CONFIG_SYS_OR_TIMING_FLASH) | |
e6f2e902 | 109 | |
7d6a0982 | 110 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) |
6902df56 | 111 | |
df939e16 JH |
112 | /* Window base at flash base */ |
113 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
e6f2e902 MB |
114 | |
115 | /* disable remaining mappings */ | |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_BR1_PRELIM 0x00000000 |
117 | #define CONFIG_SYS_OR1_PRELIM 0x00000000 | |
118 | #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 | |
119 | #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 | |
120 | ||
121 | #define CONFIG_SYS_BR2_PRELIM 0x00000000 | |
122 | #define CONFIG_SYS_OR2_PRELIM 0x00000000 | |
123 | #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 | |
124 | #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 | |
125 | ||
126 | #define CONFIG_SYS_BR3_PRELIM 0x00000000 | |
127 | #define CONFIG_SYS_OR3_PRELIM 0x00000000 | |
128 | #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 | |
129 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 | |
e6f2e902 MB |
130 | |
131 | /* | |
132 | * Monitor config | |
133 | */ | |
14d0a02a | 134 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
e6f2e902 | 135 | |
6d0f6bcf | 136 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
4681e673 | 137 | # define CONFIG_SYS_RAMBOOT |
e6f2e902 | 138 | #else |
4681e673 | 139 | # undef CONFIG_SYS_RAMBOOT |
e6f2e902 MB |
140 | #endif |
141 | ||
6d0f6bcf | 142 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
df939e16 JH |
143 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ |
144 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
e6f2e902 | 145 | |
df939e16 JH |
146 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
147 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 148 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
e6f2e902 | 149 | |
df939e16 JH |
150 | /* Reserve 384 kB = 3 sect. for Mon */ |
151 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) | |
152 | /* Reserve 512 kB for malloc */ | |
153 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
e6f2e902 MB |
154 | |
155 | /* | |
156 | * Serial Port | |
157 | */ | |
158 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_NS16550 |
160 | #define CONFIG_SYS_NS16550_SERIAL | |
161 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
162 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
e6f2e902 | 163 | |
6d0f6bcf | 164 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
df939e16 | 165 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
e6f2e902 | 166 | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
168 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
e6f2e902 MB |
169 | |
170 | /* | |
171 | * I2C | |
172 | */ | |
00f792e0 HS |
173 | #define CONFIG_SYS_I2C |
174 | #define CONFIG_SYS_I2C_FSL | |
175 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
176 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
177 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
e6f2e902 MB |
178 | |
179 | /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ | |
df939e16 JH |
180 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
181 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ | |
182 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ | |
183 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ | |
184 | #define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */ | |
e6f2e902 MB |
185 | |
186 | /* I2C RTC */ | |
df939e16 JH |
187 | #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ |
188 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
e6f2e902 MB |
189 | |
190 | /* I2C SYSMON (LM75) */ | |
df939e16 JH |
191 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
192 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
194 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
df939e16 | 195 | #define CONFIG_SYS_DTT_HYSTERESIS 3 |
e6f2e902 MB |
196 | |
197 | /* | |
198 | * TSEC | |
199 | */ | |
53677ef1 | 200 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
e6f2e902 MB |
201 | #define CONFIG_MII |
202 | ||
6d0f6bcf | 203 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
df939e16 | 204 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 205 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
df939e16 | 206 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) |
e6f2e902 MB |
207 | |
208 | #if defined(CONFIG_TSEC_ENET) | |
209 | ||
255a3577 KP |
210 | #define CONFIG_TSEC1 1 |
211 | #define CONFIG_TSEC1_NAME "TSEC0" | |
212 | #define CONFIG_TSEC2 1 | |
213 | #define CONFIG_TSEC2_NAME "TSEC1" | |
df939e16 JH |
214 | #define TSEC1_PHY_ADDR 2 |
215 | #define TSEC2_PHY_ADDR 1 | |
216 | #define TSEC1_PHYIDX 0 | |
217 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
218 | #define TSEC1_FLAGS TSEC_GIGABIT |
219 | #define TSEC2_FLAGS TSEC_GIGABIT | |
e6f2e902 MB |
220 | |
221 | /* Options are: TSEC[0-1] */ | |
df939e16 | 222 | #define CONFIG_ETHPRIME "TSEC0" |
e6f2e902 MB |
223 | |
224 | #endif /* CONFIG_TSEC_ENET */ | |
225 | ||
226 | /* | |
227 | * General PCI | |
228 | * Addresses are mapped 1-1. | |
229 | */ | |
6902df56 RJ |
230 | #define CONFIG_PCI |
231 | ||
e6f2e902 MB |
232 | #if defined(CONFIG_PCI) |
233 | ||
df939e16 JH |
234 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
235 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6902df56 RJ |
236 | |
237 | /* PCI1 host bridge */ | |
df939e16 JH |
238 | #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 |
239 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
240 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
241 | #define CONFIG_SYS_PCI1_MMIO_BASE \ | |
242 | (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
243 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
244 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
245 | #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 | |
246 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
247 | #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ | |
e6f2e902 | 248 | |
e6f2e902 | 249 | #undef CONFIG_EEPRO100 |
63ff004c | 250 | #define CONFIG_EEPRO100 |
e6f2e902 MB |
251 | #undef CONFIG_TULIP |
252 | ||
253 | #if !defined(CONFIG_PCI_PNP) | |
6d0f6bcf JCPV |
254 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE |
255 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE | |
6902df56 | 256 | #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ |
e6f2e902 MB |
257 | #endif |
258 | ||
6d0f6bcf | 259 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
e6f2e902 MB |
260 | |
261 | #endif /* CONFIG_PCI */ | |
262 | ||
263 | /* | |
264 | * Environment | |
265 | */ | |
df939e16 JH |
266 | #define CONFIG_ENV_IS_IN_FLASH 1 |
267 | #define CONFIG_ENV_ADDR \ | |
268 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
269 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ | |
270 | #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ | |
929b79a0 WD |
271 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
272 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
273 | ||
df939e16 JH |
274 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
275 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
e6f2e902 | 276 | |
a1aa0bb5 JL |
277 | /* |
278 | * BOOTP options | |
279 | */ | |
280 | #define CONFIG_BOOTP_BOOTFILESIZE | |
281 | #define CONFIG_BOOTP_BOOTPATH | |
282 | #define CONFIG_BOOTP_GATEWAY | |
283 | #define CONFIG_BOOTP_HOSTNAME | |
284 | ||
285 | ||
2694690e JL |
286 | /* |
287 | * Command line configuration. | |
288 | */ | |
289 | #include <config_cmd_default.h> | |
290 | ||
4681e673 | 291 | #define CONFIG_CMD_ASKENV |
2694690e | 292 | #define CONFIG_CMD_DATE |
4681e673 | 293 | #define CONFIG_CMD_DHCP |
2694690e JL |
294 | #define CONFIG_CMD_DTT |
295 | #define CONFIG_CMD_EEPROM | |
296 | #define CONFIG_CMD_I2C | |
4681e673 | 297 | #define CONFIG_CMD_NFS |
2694690e JL |
298 | #define CONFIG_CMD_JFFS2 |
299 | #define CONFIG_CMD_MII | |
300 | #define CONFIG_CMD_PING | |
4681e673 WD |
301 | #define CONFIG_CMD_REGINFO |
302 | #define CONFIG_CMD_SNTP | |
e6f2e902 MB |
303 | |
304 | #if defined(CONFIG_PCI) | |
2694690e | 305 | #define CONFIG_CMD_PCI |
e6f2e902 MB |
306 | #endif |
307 | ||
6d0f6bcf | 308 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 309 | #undef CONFIG_CMD_SAVEENV |
2694690e | 310 | #undef CONFIG_CMD_LOADS |
e6f2e902 MB |
311 | #endif |
312 | ||
e6f2e902 MB |
313 | /* |
314 | * Miscellaneous configurable options | |
315 | */ | |
df939e16 JH |
316 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
317 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
e6f2e902 | 318 | |
df939e16 JH |
319 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
320 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
a059e90e | 321 | |
df939e16 | 322 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
2751a95a | 323 | |
2694690e | 324 | #if defined(CONFIG_CMD_KGDB) |
df939e16 | 325 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
e6f2e902 | 326 | #else |
df939e16 | 327 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
e6f2e902 MB |
328 | #endif |
329 | ||
df939e16 JH |
330 | /* Print Buffer Size */ |
331 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
332 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
333 | /* Boot Argument Buffer Size */ | |
334 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
e6f2e902 | 335 | |
df939e16 | 336 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
e6f2e902 | 337 | |
4681e673 WD |
338 | /* pass open firmware flat tree */ |
339 | #define CONFIG_OF_LIBFDT 1 | |
340 | #define CONFIG_OF_BOARD_SETUP 1 | |
341 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
342 | ||
e6f2e902 MB |
343 | /* |
344 | * For booting Linux, the board info and command line data | |
9f530d59 | 345 | * have to be in the first 256 MB of memory, since this is |
e6f2e902 MB |
346 | * the maximum mapped by the Linux kernel during initialization. |
347 | */ | |
df939e16 JH |
348 | /* Initial Memory map for Linux */ |
349 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
e6f2e902 | 350 | |
6d0f6bcf | 351 | #define CONFIG_SYS_HRCW_LOW (\ |
e6f2e902 MB |
352 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
353 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
354 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
355 | HRCWL_VCO_1X2 |\ | |
356 | HRCWL_CORE_TO_CSB_2X1) | |
357 | ||
358 | #if defined(PCI_64BIT) | |
6d0f6bcf | 359 | #define CONFIG_SYS_HRCW_HIGH (\ |
e6f2e902 MB |
360 | HRCWH_PCI_HOST |\ |
361 | HRCWH_64_BIT_PCI |\ | |
362 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
363 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
364 | HRCWH_CORE_ENABLE |\ | |
365 | HRCWH_FROM_0X00000100 |\ | |
366 | HRCWH_BOOTSEQ_DISABLE |\ | |
367 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
368 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
369 | HRCWH_TSEC1M_IN_GMII |\ | |
df939e16 | 370 | HRCWH_TSEC2M_IN_GMII) |
e6f2e902 | 371 | #else |
6d0f6bcf | 372 | #define CONFIG_SYS_HRCW_HIGH (\ |
e6f2e902 MB |
373 | HRCWH_PCI_HOST |\ |
374 | HRCWH_32_BIT_PCI |\ | |
375 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
6902df56 | 376 | HRCWH_PCI2_ARBITER_DISABLE |\ |
e6f2e902 MB |
377 | HRCWH_CORE_ENABLE |\ |
378 | HRCWH_FROM_0X00000100 |\ | |
379 | HRCWH_BOOTSEQ_DISABLE |\ | |
380 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
381 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
382 | HRCWH_TSEC1M_IN_GMII |\ | |
df939e16 | 383 | HRCWH_TSEC2M_IN_GMII) |
e6f2e902 MB |
384 | #endif |
385 | ||
9260a561 | 386 | /* System IO Config */ |
3c9b1ee1 | 387 | #define CONFIG_SYS_SICRH 0 |
6d0f6bcf | 388 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
9260a561 | 389 | |
e6f2e902 | 390 | /* i-cache and d-cache disabled */ |
6d0f6bcf | 391 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
1a2e203b KP |
392 | #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ |
393 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 394 | #define CONFIG_SYS_HID2 HID2_HBE |
e6f2e902 | 395 | |
31d82672 BB |
396 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
397 | ||
2688e2f9 | 398 | /* DDR 0 - 512M */ |
df939e16 | 399 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 400 | | BATL_PP_RW \ |
df939e16 JH |
401 | | BATL_MEMCOHERENCE) |
402 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
403 | | BATU_BL_256M \ | |
404 | | BATU_VS \ | |
405 | | BATU_VP) | |
406 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ | |
72cd4087 | 407 | | BATL_PP_RW \ |
df939e16 JH |
408 | | BATL_MEMCOHERENCE) |
409 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ | |
410 | | BATU_BL_256M \ | |
411 | | BATU_VS \ | |
412 | | BATU_VP) | |
2688e2f9 KG |
413 | |
414 | /* stack in DCACHE @ 512M (no backing mem) */ | |
df939e16 | 415 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ |
72cd4087 | 416 | | BATL_PP_RW \ |
df939e16 JH |
417 | | BATL_MEMCOHERENCE) |
418 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ | |
419 | | BATU_BL_128K \ | |
420 | | BATU_VS \ | |
421 | | BATU_VP) | |
2688e2f9 KG |
422 | |
423 | /* PCI */ | |
6fe16a87 | 424 | #ifdef CONFIG_PCI |
842033e6 | 425 | #define CONFIG_PCI_INDIRECT_BRIDGE |
df939e16 | 426 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 427 | | BATL_PP_RW \ |
df939e16 JH |
428 | | BATL_MEMCOHERENCE) |
429 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ | |
430 | | BATU_BL_256M \ | |
431 | | BATU_VS \ | |
432 | | BATU_VP) | |
433 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 434 | | BATL_PP_RW \ |
df939e16 JH |
435 | | BATL_MEMCOHERENCE \ |
436 | | BATL_GUARDEDSTORAGE) | |
437 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
438 | | BATU_BL_256M \ | |
439 | | BATU_VS \ | |
440 | | BATU_VP) | |
441 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ | |
72cd4087 | 442 | | BATL_PP_RW \ |
df939e16 JH |
443 | | BATL_CACHEINHIBIT \ |
444 | | BATL_GUARDEDSTORAGE) | |
445 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ | |
446 | | BATU_BL_16M \ | |
447 | | BATU_VS \ | |
448 | | BATU_VP) | |
6fe16a87 | 449 | #else |
6d0f6bcf JCPV |
450 | #define CONFIG_SYS_IBAT3L (0) |
451 | #define CONFIG_SYS_IBAT3U (0) | |
452 | #define CONFIG_SYS_IBAT4L (0) | |
453 | #define CONFIG_SYS_IBAT4U (0) | |
454 | #define CONFIG_SYS_IBAT5L (0) | |
455 | #define CONFIG_SYS_IBAT5U (0) | |
6fe16a87 | 456 | #endif |
2688e2f9 KG |
457 | |
458 | /* IMMRBAR */ | |
df939e16 | 459 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ |
72cd4087 | 460 | | BATL_PP_RW \ |
df939e16 JH |
461 | | BATL_CACHEINHIBIT \ |
462 | | BATL_GUARDEDSTORAGE) | |
463 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ | |
464 | | BATU_BL_1M \ | |
465 | | BATU_VS \ | |
466 | | BATU_VP) | |
2688e2f9 KG |
467 | |
468 | /* FLASH */ | |
df939e16 | 469 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 470 | | BATL_PP_RW \ |
df939e16 JH |
471 | | BATL_CACHEINHIBIT \ |
472 | | BATL_GUARDEDSTORAGE) | |
473 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ | |
474 | | BATU_BL_256M \ | |
475 | | BATU_VS \ | |
476 | | BATU_VP) | |
6d0f6bcf JCPV |
477 | |
478 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
479 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
480 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
481 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
482 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
483 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
484 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
485 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
486 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
487 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
488 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
489 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
490 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
491 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
492 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
493 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
2688e2f9 | 494 | |
2694690e | 495 | #if defined(CONFIG_CMD_KGDB) |
e6f2e902 | 496 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
e6f2e902 MB |
497 | #endif |
498 | ||
499 | /* | |
500 | * Environment Configuration | |
501 | */ | |
502 | ||
df939e16 JH |
503 | /* default location for tftp and bootm */ |
504 | #define CONFIG_LOADADDR 400000 | |
e6f2e902 MB |
505 | |
506 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
df939e16 | 507 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
e6f2e902 MB |
508 | |
509 | #define CONFIG_BAUDRATE 115200 | |
510 | ||
511 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 512 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
e6f2e902 MB |
513 | "echo" |
514 | ||
515 | #undef CONFIG_BOOTARGS | |
516 | ||
517 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
518 | "netdev=eth0\0" \ | |
b931b3a9 | 519 | "hostname=tqm834x\0" \ |
e6f2e902 | 520 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b | 521 | "nfsroot=${serverip}:${rootpath}\0" \ |
e6f2e902 | 522 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
523 | "addip=setenv bootargs ${bootargs} " \ |
524 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
525 | ":${hostname}:${netdev}:off panic=1\0" \ | |
df939e16 | 526 | "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ |
4681e673 | 527 | "flash_nfs_old=run nfsargs addip addcons;" \ |
fe126d8b | 528 | "bootm ${kernel_addr}\0" \ |
4681e673 WD |
529 | "flash_nfs=run nfsargs addip addcons;" \ |
530 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
531 | "flash_self_old=run ramargs addip addcons;" \ | |
fe126d8b | 532 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
4681e673 WD |
533 | "flash_self=run ramargs addip addcons;" \ |
534 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
535 | "net_nfs_old=tftp 400000 ${bootfile};" \ | |
536 | "run nfsargs addip addcons;bootm\0" \ | |
537 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
538 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
539 | "run nfsargs addip addcons; " \ | |
540 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
e6f2e902 | 541 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
4681e673 WD |
542 | "bootfile=tqm834x/uImage\0" \ |
543 | "fdtfile=tqm834x/tqm834x.dtb\0" \ | |
544 | "kernel_addr_r=400000\0" \ | |
545 | "fdt_addr_r=600000\0" \ | |
546 | "ramdisk_addr_r=800000\0" \ | |
547 | "kernel_addr=800C0000\0" \ | |
548 | "fdt_addr=800A0000\0" \ | |
549 | "ramdisk_addr=80300000\0" \ | |
550 | "u-boot=tqm834x/u-boot.bin\0" \ | |
551 | "load=tftp 200000 ${u-boot}\0" \ | |
552 | "update=protect off 80000000 +${filesize};" \ | |
553 | "era 80000000 +${filesize};" \ | |
554 | "cp.b 200000 80000000 ${filesize}\0" \ | |
d8ab58b2 | 555 | "upd=run load update\0" \ |
e6f2e902 MB |
556 | "" |
557 | ||
558 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
559 | ||
560 | /* | |
561 | * JFFS2 partitions | |
562 | */ | |
563 | /* mtdparts command line support */ | |
68d7d651 | 564 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
565 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
566 | #define CONFIG_FLASH_CFI_MTD | |
e6f2e902 MB |
567 | #define MTDIDS_DEFAULT "nor0=TQM834x-0" |
568 | ||
569 | /* default mtd partition table */ | |
df939e16 JH |
570 | #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \ |
571 | "1m(kernel),2m(initrd)," \ | |
572 | "-(user);" \ | |
e6f2e902 MB |
573 | |
574 | #endif /* __CONFIG_H */ |