[people/ms/u-boot.git] / include / configs / TQM834x.h

/*
 * (C) Copyright 2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * TQM8349 board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define DEBUG
#undef DEBUG

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */
#define CONFIG_MPC83XX		1	/* MPC83XX family */
#define CONFIG_MPC834X		1	/* MPC834X specific */
#define CONFIG_MPC8349		1	/* MPC8349 specific */
#define CONFIG_TQM834X		1	/* TQM834X board specific */

/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
#define CFG_IMMR		0xff400000

/* System clock. Primary input clock when in PCI host mode */
#define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */

/*
 * Local Bus LCRR
 *    LCRR:  DLL bypass, Clock divider is 8
 *
 *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
 *
 * External Local Bus rate is
 *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)

#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
				| CFG_SCCR_TSEC1CM	\
				| CFG_SCCR_TSEC2CM	\
				| CFG_SCCR_ENCCM	\
				| CFG_SCCR_USBCM	)

/* board pre init: do not call, nothing to do */
#undef CONFIG_BOARD_EARLY_INIT_F

/* detect the number of flash banks */
#define CONFIG_BOARD_EARLY_INIT_R

/*
 * DDR Setup
 */
#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
#define DDR_CASLAT_25				/* CASLAT set to 2.5 */
#undef CONFIG_DDR_ECC				/* only for ECC DDR module */
#undef CONFIG_SPD_EEPROM			/* do not use SPD EEPROM for DDR setup */

#undef CFG_DRAM_TEST				/* memory test, takes time */
#define CFG_MEMTEST_START	0x00000000	/* memtest region */
#define CFG_MEMTEST_END		0x00100000

/*
 * FLASH on the Local Bus
 */
#define CFG_FLASH_CFI				/* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_BASE		0x80000000	/* start of FLASH   */
#define CFG_FLASH_SIZE		8		/* FLASH size in MB */

/* buffered writes in the AMD chip set is not supported yet */
#undef CFG_FLASH_USE_BUFFER_WRITE

/*
 * FLASH bank number detection
 */

/*
 * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
 * banks has to be determined at runtime and stored in a gloabl variable
 * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
 * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
 * should be made sufficiently large to accomodate the number of banks that
 * might actually be detected.  Since most (all?) Flash related functions use
 * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
 * defined as tqm834x_num_flash_banks.
 */
#define CFG_MAX_FLASH_BANKS_DETECT	2
#ifndef __ASSEMBLY__
extern int tqm834x_num_flash_banks;
#endif
#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)

#define CFG_MAX_FLASH_SECT		512	/* max sectors per device */

/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
#define CFG_BR0_PRELIM		((CFG_FLASH_BASE & BR_BA) | \
					BR_MS_GPCM | BR_PS_32 | BR_V)

/* FLASH timing (0x0000_0c54) */
#define CFG_OR_TIMING_FLASH	(OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
					OR_GPCM_SCY_5 | OR_GPCM_TRLX)

#define CFG_PRELIM_OR_AM	0xc0000000	/* OR addr mask: 1 GiB */

#define CFG_OR0_PRELIM		(CFG_PRELIM_OR_AM  | CFG_OR_TIMING_FLASH)

#define CFG_LBLAWAR0_PRELIM	0x8000001D	/* 1 GiB window size (2^(size + 1)) */

#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */

/* disable remaining mappings */
#define CFG_BR1_PRELIM		0x00000000
#define CFG_OR1_PRELIM		0x00000000
#define CFG_LBLAWBAR1_PRELIM	0x00000000
#define CFG_LBLAWAR1_PRELIM	0x00000000

#define CFG_BR2_PRELIM		0x00000000
#define CFG_OR2_PRELIM		0x00000000
#define CFG_LBLAWBAR2_PRELIM	0x00000000
#define CFG_LBLAWAR2_PRELIM	0x00000000

#define CFG_BR3_PRELIM		0x00000000
#define CFG_OR3_PRELIM		0x00000000
#define CFG_LBLAWBAR3_PRELIM	0x00000000
#define CFG_LBLAWAR3_PRELIM	0x00000000

#define CFG_BR4_PRELIM		0x00000000
#define CFG_OR4_PRELIM		0x00000000
#define CFG_LBLAWBAR4_PRELIM	0x00000000
#define CFG_LBLAWAR4_PRELIM	0x00000000

#define CFG_BR5_PRELIM		0x00000000
#define CFG_OR5_PRELIM		0x00000000
#define CFG_LBLAWBAR5_PRELIM	0x00000000
#define CFG_LBLAWAR5_PRELIM	0x00000000

#define CFG_BR6_PRELIM		0x00000000
#define CFG_OR6_PRELIM		0x00000000
#define CFG_LBLAWBAR6_PRELIM	0x00000000
#define CFG_LBLAWAR6_PRELIM	0x00000000

#define CFG_BR7_PRELIM		0x00000000
#define CFG_OR7_PRELIM		0x00000000
#define CFG_LBLAWBAR7_PRELIM	0x00000000
#define CFG_LBLAWAR7_PRELIM	0x00000000

/*
 * Monitor config
 */
#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef  CFG_RAMBOOT
#endif

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0x20000000	/* Initial RAM address */
#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/

#define CFG_GBL_DATA_SIZE  	0x100		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1	(CFG_IMMR + 0x4500)
#define CFG_NS16550_COM2	(CFG_IMMR + 0x4600)

/*
 * I2C
 */
#define CONFIG_HARD_I2C				/* I2C with hardware support	*/
#undef CONFIG_SOFT_I2C				/* I2C bit-banged		*/
#define CONFIG_FSL_I2C
#define CFG_I2C_SPEED			400000	/* I2C speed: 400KHz		*/
#define CFG_I2C_SLAVE			0x7F	/* slave address		*/
#define CFG_I2C_OFFSET			0x3000

/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x			*/
#define CFG_I2C_EEPROM_ADDR_LEN		2	/* 16 bit			*/
#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes per write		*/
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20%			*/
#define CFG_I2C_MULTI_EEPROMS		1       /* more than one eeprom		*/

/* I2C RTC */
#define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c	*/
#define CFG_I2C_RTC_ADDR		0x68	/* at address 0x68		*/

/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM75			1	/* ON Semi's LM75		*/
#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses		*/
#define CFG_DTT_MAX_TEMP		70
#define CFG_DTT_LOW_TEMP		-30
#define CFG_DTT_HYSTERESIS		3

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
#define CONFIG_MII

#define CFG_TSEC1_OFFSET	0x24000
#define CFG_TSEC1		(CFG_IMMR + CFG_TSEC1_OFFSET)
#define CFG_TSEC2_OFFSET	0x25000
#define CFG_TSEC2		(CFG_IMMR + CFG_TSEC2_OFFSET)

#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI
#endif

#define CONFIG_MPC83XX_TSEC1		1
#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
#define CONFIG_MPC83XX_TSEC2		1
#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR			2
#define TSEC2_PHY_ADDR			1
#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME			"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_PCI

#if defined(CONFIG_PCI)

#define CONFIG_PCI_PNP                  /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */

/* PCI1 host bridge */
#define CFG_PCI1_MEM_BASE       0xc0000000
#define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
#define CFG_PCI1_IO_BASE        0xe2000000
#define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE        0x1000000       /* 16M */


#undef CONFIG_EEPRO100
#define CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
	#define PCI_ENET0_IOADDR	CFG_PCI1_IO_BASE
	#define PCI_ENET0_MEMADDR	CFG_PCI1_MEM_BASE
	#define PCI_IDSEL_NUMBER	0x1c    /* slot0 (IDSEL) = 28 */
#endif

#define CFG_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */

#endif	/* CONFIG_PCI */

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#ifndef CFG_RAMBOOT
	#define CFG_ENV_IS_IN_FLASH	1
	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
	#define CFG_ENV_SECT_SIZE	0x20000	/* 256K(one sector) for env */
	#define CFG_ENV_SIZE		0x2000
#else
	#define CFG_NO_FLASH		1	/* Flash is not usable now */
	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
	#define CFG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE		1	/* allow baudrate change */

/* Common commands */
#define CFG_CMD_TQM8349_COMMON	CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\
				| CFG_CMD_PING | CFG_CMD_EEPROM		\
				| CFG_CMD_MII | CFG_CMD_JFFS2

#if defined(CFG_RAMBOOT)

#if defined(CONFIG_PCI)
#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI	\
				| CFG_CMD_TQM8349_COMMON)	\
				&				\
				~(CFG_CMD_ENV | CFG_CMD_LOADS))
#else
#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL		\
				| CFG_CMD_TQM8349_COMMON)	\
				&				\
				~(CFG_CMD_ENV | CFG_CMD_LOADS))
#endif

#else /* CFG_RAMBOOT */

#if defined(CONFIG_PCI)
#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI	\
				| CFG_CMD_TQM8349_COMMON)
#else
#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL			\
				| CFG_CMD_TQM8349_COMMON)
#endif

#endif /* CFG_RAMBOOT */

#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP				/* undef to save memory	*/
#define CFG_LOAD_ADDR		0x2000000	/* default load address */
#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args */
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ			1000		/* decrementer freq: 1ms ticks */

#undef CONFIG_WATCHDOG				/* watchdog disabled */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

/*
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		32768
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
#endif

#define CFG_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN_4X1 |\
	HRCWL_VCO_1X2 |\
	HRCWL_CORE_TO_CSB_2X1)

#if defined(PCI_64BIT)
#define CFG_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_64_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII )
#else
#define CFG_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_32_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII )
#endif

/* System IO Config */
#define CFG_SICRH	SICRH_TSOBI1
#define CFG_SICRL	SICRL_LDP_A

/* i-cache and d-cache disabled */
#define CFG_HID0_INIT	0x000000000
#define CFG_HID0_FINAL	CFG_HID0_INIT
#define CFG_HID2	HID2_HBE

/* DDR 0 - 512M */
#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT1L	(CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U	(CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in DCACHE @ 512M (no backing mem) */
#define CFG_IBAT2L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT2U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

/* PCI */
#ifdef CONFIG_PCI
#define CFG_IBAT3L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT3U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT4L	(CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT4U	(CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT5L	(CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT5U	(CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
#else
#define CFG_IBAT3L	(0)
#define CFG_IBAT3U	(0)
#define CFG_IBAT4L	(0)
#define CFG_IBAT4U	(0)
#define CFG_IBAT5L	(0)
#define CFG_IBAT5U	(0)
#endif

/* IMMRBAR */
#define CFG_IBAT6L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT6U	(CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)

/* FLASH */
#define CFG_IBAT7L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT7U	(CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_DBAT0L	CFG_IBAT0L
#define CFG_DBAT0U	CFG_IBAT0U
#define CFG_DBAT1L	CFG_IBAT1L
#define CFG_DBAT1U	CFG_IBAT1U
#define CFG_DBAT2L	CFG_IBAT2L
#define CFG_DBAT2U	CFG_IBAT2U
#define CFG_DBAT3L	CFG_IBAT3L
#define CFG_DBAT3U	CFG_IBAT3U
#define CFG_DBAT4L	CFG_IBAT4L
#define CFG_DBAT4U	CFG_IBAT4U
#define CFG_DBAT5L	CFG_IBAT5L
#define CFG_DBAT5U	CFG_IBAT5U
#define CFG_DBAT6L	CFG_IBAT6L
#define CFG_DBAT6U	CFG_IBAT6U
#define CFG_DBAT7L	CFG_IBAT7L
#define CFG_DBAT7U	CFG_IBAT7U

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR		D2:DA:5E:44:BC:29
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR		1E:F3:40:21:92:53
#endif

#define CONFIG_IPADDR		192.168.205.1

#define CONFIG_HOSTNAME		tqm8349
#define CONFIG_ROOTPATH		/opt/eldk/ppc_6xx
#define CONFIG_BOOTFILE		/tftpboot/tqm83xx/uImage

#define CONFIG_SERVERIP		192.168.1.1
#define CONFIG_GATEWAYIP	192.168.1.1
#define CONFIG_NETMASK		255.255.255.0

#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */

#define CONFIG_BAUDRATE		115200

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=tqm83xx\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
		"bootm\0"						\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=/tftpboot/tqm83xx/uImage\0"				\
	"kernel_addr=80060000\0"					\
	"ramdisk_addr=80160000\0"					\
	"load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0"		\
	"update=protect off 80000000 8003ffff; "			\
		"era 80000000 8003ffff; cp.b 100000 80000000 40000\0"	\
	"upd=run load;run update\0"					\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * JFFS2 partitions
 */
/* mtdparts command line support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=TQM834x-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
						"1m(kernel),2m(initrd),"\
						"-(user);"\

#endif	/* __CONFIG_H */
Commit	Line	Data
e6f2e902 MB	1	/*
	2	* (C) Copyright 2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* TQM8349 board configuration file
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	#define DEBUG
	32	#undef DEBUG
	33
	34	/*
	35	* High Level Configuration Options
	36	*/
	37	#define CONFIG_E300 1 /* E300 Family */
	38	#define CONFIG_MPC83XX 1 /* MPC83XX family */
	39	#define CONFIG_MPC834X 1 /* MPC834X specific */
9ca880a2	40	#define CONFIG_MPC8349 1 /* MPC8349 specific */
e6f2e902 MB	41	#define CONFIG_TQM834X 1 /* TQM834X board specific */
	42
	43	/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
d239d74b	44	#define CFG_IMMR 0xff400000
e6f2e902 MB	45
	46	/* System clock. Primary input clock when in PCI host mode */
	47	#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
	48
	49	/*
	50	* Local Bus LCRR
	51	* LCRR: DLL bypass, Clock divider is 8
	52	*
	53	* for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
	54	*
	55	* External Local Bus rate is
	56	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
	57	*/
	58	#define CFG_LCRR (LCRR_DBYP \| LCRR_CLKDIV_8)
	59
2fc34ae6 TJ	60	#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK))
	61	#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */
	62	#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */
	63	#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */
	64	#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */
	65	#define CFG_SCCR_VAL ( CFG_SCCR_INIT \
	66	\| CFG_SCCR_TSEC1CM \
	67	\| CFG_SCCR_TSEC2CM \
	68	\| CFG_SCCR_ENCCM \
	69	\| CFG_SCCR_USBCM )
	70
e6f2e902 MB	71	/* board pre init: do not call, nothing to do */
	72	#undef CONFIG_BOARD_EARLY_INIT_F
	73
	74	/* detect the number of flash banks */
	75	#define CONFIG_BOARD_EARLY_INIT_R
	76
	77	/*
	78	* DDR Setup
	79	*/
	80	#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
	81	#define CFG_SDRAM_BASE CFG_DDR_BASE
	82	#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
	83	#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
	84	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	85	#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
	86
	87	#undef CFG_DRAM_TEST /* memory test, takes time */
	88	#define CFG_MEMTEST_START 0x00000000 /* memtest region */
	89	#define CFG_MEMTEST_END 0x00100000
	90
	91	/*
	92	* FLASH on the Local Bus
	93	*/
	94	#define CFG_FLASH_CFI /* use the Common Flash Interface */
	95	#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
	96	#undef CFG_FLASH_CHECKSUM
	97	#define CFG_FLASH_BASE 0x80000000 /* start of FLASH */
afd6e470	98	#define CFG_FLASH_SIZE 8 /* FLASH size in MB */
e6f2e902 MB	99
	100	/* buffered writes in the AMD chip set is not supported yet */
	101	#undef CFG_FLASH_USE_BUFFER_WRITE
	102
	103	/*
	104	* FLASH bank number detection
	105	*/
	106
	107	/*
	108	* When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
	109	* banks has to be determined at runtime and stored in a gloabl variable
	110	* tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
f013dacf	111	* used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
e6f2e902	112	* should be made sufficiently large to accomodate the number of banks that
f013dacf	113	* might actually be detected. Since most (all?) Flash related functions use
e6f2e902 MB	114	* CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
	115	* defined as tqm834x_num_flash_banks.
	116	*/
	117	#define CFG_MAX_FLASH_BANKS_DETECT 2
f013dacf	118	#ifndef __ASSEMBLY__
e6f2e902 MB	119	extern int tqm834x_num_flash_banks;
	120	#endif
	121	#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
	122
	123	#define CFG_MAX_FLASH_SECT 512 /* max sectors per device */
	124
	125	/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
	126	#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) \| \
	127	BR_MS_GPCM \| BR_PS_32 \| BR_V)
	128
	129	/* FLASH timing (0x0000_0c54) */
	130	#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT \| OR_GPCM_ACS_0b10 \| \
	131	OR_GPCM_SCY_5 \| OR_GPCM_TRLX)
	132
	133	#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
	134
	135	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
	136
	137	#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
6902df56	138
e6f2e902 MB	139	#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
	140
	141	/* disable remaining mappings */
	142	#define CFG_BR1_PRELIM 0x00000000
	143	#define CFG_OR1_PRELIM 0x00000000
	144	#define CFG_LBLAWBAR1_PRELIM 0x00000000
	145	#define CFG_LBLAWAR1_PRELIM 0x00000000
	146
	147	#define CFG_BR2_PRELIM 0x00000000
	148	#define CFG_OR2_PRELIM 0x00000000
	149	#define CFG_LBLAWBAR2_PRELIM 0x00000000
	150	#define CFG_LBLAWAR2_PRELIM 0x00000000
	151
	152	#define CFG_BR3_PRELIM 0x00000000
	153	#define CFG_OR3_PRELIM 0x00000000
	154	#define CFG_LBLAWBAR3_PRELIM 0x00000000
	155	#define CFG_LBLAWAR3_PRELIM 0x00000000
	156
	157	#define CFG_BR4_PRELIM 0x00000000
	158	#define CFG_OR4_PRELIM 0x00000000
	159	#define CFG_LBLAWBAR4_PRELIM 0x00000000
	160	#define CFG_LBLAWAR4_PRELIM 0x00000000
	161
	162	#define CFG_BR5_PRELIM 0x00000000
	163	#define CFG_OR5_PRELIM 0x00000000
	164	#define CFG_LBLAWBAR5_PRELIM 0x00000000
	165	#define CFG_LBLAWAR5_PRELIM 0x00000000
	166
	167	#define CFG_BR6_PRELIM 0x00000000
	168	#define CFG_OR6_PRELIM 0x00000000
	169	#define CFG_LBLAWBAR6_PRELIM 0x00000000
	170	#define CFG_LBLAWAR6_PRELIM 0x00000000
	171
	172	#define CFG_BR7_PRELIM 0x00000000
	173	#define CFG_OR7_PRELIM 0x00000000
	174	#define CFG_LBLAWBAR7_PRELIM 0x00000000
	175	#define CFG_LBLAWAR7_PRELIM 0x00000000
	176
	177	/*
	178	* Monitor config
	179	*/
	180	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
	181
	182	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	183	#define CFG_RAMBOOT
	184	#else
	185	#undef CFG_RAMBOOT
	186	#endif
	187
	188	#define CONFIG_L1_INIT_RAM
	189	#define CFG_INIT_RAM_LOCK 1
	190	#define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
	191	#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
	192
	193	#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
	194	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	195	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	196
	197	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
	198	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
	199
	200	/*
	201	* Serial Port
	202	*/
203	#define CONFIG_CONS_INDEX 1
204	#undef CONFIG_SERIAL_SOFTWARE_FIFO
205	#define CFG_NS16550
206	#define CFG_NS16550_SERIAL
207	#define CFG_NS16550_REG_SIZE 1
208	#define CFG_NS16550_CLK get_bus_freq(0)
209
210	#define CFG_BAUDRATE_TABLE \
211	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
212
d239d74b TT	213	#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500)
d239d74b TT	214	#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
e6f2e902 MB	215
	216	/*
	217	* I2C
	218	*/
	219	#define CONFIG_HARD_I2C /* I2C with hardware support */
	220	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
be5e6181	221	#define CONFIG_FSL_I2C
e6f2e902 MB	222	#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */
	223	#define CFG_I2C_SLAVE 0x7F /* slave address */
	224	#define CFG_I2C_OFFSET 0x3000
	225
	226	/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
	227	#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	228	#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
	229	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
	230	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	231	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
	232	#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
	233
	234	/* I2C RTC */
	235	#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
	236	#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
	237
	238	/* I2C SYSMON (LM75) */
	239	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	240	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
	241	#define CFG_DTT_MAX_TEMP 70
	242	#define CFG_DTT_LOW_TEMP -30
	243	#define CFG_DTT_HYSTERESIS 3
	244
	245	/*
	246	* TSEC
	247	*/
	248	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	249	#define CONFIG_MII
	250
	251	#define CFG_TSEC1_OFFSET 0x24000
d239d74b	252	#define CFG_TSEC1 (CFG_IMMR + CFG_TSEC1_OFFSET)
e6f2e902	253	#define CFG_TSEC2_OFFSET 0x25000
d239d74b	254	#define CFG_TSEC2 (CFG_IMMR + CFG_TSEC2_OFFSET)
e6f2e902 MB	255
	256	#if defined(CONFIG_TSEC_ENET)
	257
	258	#ifndef CONFIG_NET_MULTI
6902df56	259	#define CONFIG_NET_MULTI
e6f2e902 MB	260	#endif
	261
	262	#define CONFIG_MPC83XX_TSEC1 1
	263	#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
	264	#define CONFIG_MPC83XX_TSEC2 1
	265	#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
b6f84356	266	#define TSEC1_PHY_ADDR 2
e6f2e902 MB	267	#define TSEC2_PHY_ADDR 1
	268	#define TSEC1_PHYIDX 0
	269	#define TSEC2_PHYIDX 0
	270
	271	/* Options are: TSEC[0-1] */
	272	#define CONFIG_ETHPRIME "TSEC0"
	273
	274	#endif /* CONFIG_TSEC_ENET */
	275
	276	/*
	277	* General PCI
	278	* Addresses are mapped 1-1.
	279	*/
6902df56 RJ	280	#define CONFIG_PCI
6902df56 RJ	281
e6f2e902 MB	282	#if defined(CONFIG_PCI)
e6f2e902 MB	283
6902df56 RJ	284	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	285	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	286
	287	/* PCI1 host bridge */
	288	#define CFG_PCI1_MEM_BASE 0xc0000000
	289	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
	290	#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
	291	#define CFG_PCI1_IO_BASE 0xe2000000
	292	#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
	293	#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
e6f2e902	294
e6f2e902 MB	295
e6f2e902 MB	296	#undef CONFIG_EEPRO100
63ff004c	297	#define CONFIG_EEPRO100
e6f2e902 MB	298	#undef CONFIG_TULIP
	299
	300	#if !defined(CONFIG_PCI_PNP)
6902df56 RJ	301	#define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
	302	#define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE
	303	#define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
e6f2e902 MB	304	#endif
e6f2e902 MB	305
6902df56	306	#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
e6f2e902 MB	307
	308	#endif /* CONFIG_PCI */
	309
	310	/*
	311	* Environment
	312	*/
	313	#define CONFIG_ENV_OVERWRITE
	314
	315	#ifndef CFG_RAMBOOT
	316	#define CFG_ENV_IS_IN_FLASH 1
	317	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
	318	#define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
	319	#define CFG_ENV_SIZE 0x2000
	320	#else
	321	#define CFG_NO_FLASH 1 /* Flash is not usable now */
	322	#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	323	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	324	#define CFG_ENV_SIZE 0x2000
	325	#endif
	326
	327	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	328	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	329
	330	/* Common commands */
	331	#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE \| CFG_CMD_I2C \| CFG_CMD_DTT\
	332	\| CFG_CMD_PING \| CFG_CMD_EEPROM \
	333	\| CFG_CMD_MII \| CFG_CMD_JFFS2
	334
	335	#if defined(CFG_RAMBOOT)
	336
	337	#if defined(CONFIG_PCI)
	338	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \| CFG_CMD_PCI \
	339	\| CFG_CMD_TQM8349_COMMON) \
	340	& \
	341	~(CFG_CMD_ENV \| CFG_CMD_LOADS))
	342	#else
	343	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
	344	\| CFG_CMD_TQM8349_COMMON) \
	345	& \
	346	~(CFG_CMD_ENV \| CFG_CMD_LOADS))
	347	#endif
	348
	349	#else /* CFG_RAMBOOT */
	350
	351	#if defined(CONFIG_PCI)
	352	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| CFG_CMD_PCI \
	353	\| CFG_CMD_TQM8349_COMMON)
	354	#else
	355	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
	356	\| CFG_CMD_TQM8349_COMMON)
	357	#endif
	358
	359	#endif /* CFG_RAMBOOT */
	360
	361	#include <cmd_confdefs.h>
	362
	363	/*
	364	* Miscellaneous configurable options
	365	*/
	366	#define CFG_LONGHELP /* undef to save memory */
	367	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
	368	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	369
2751a95a WD	370	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	371	#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
	372	#ifdef CFG_HUSH_PARSER
	373	#define CFG_PROMPT_HUSH_PS2 "> "
	374	#endif
	375
e6f2e902 MB	376	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	377	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	378	#else
	379	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	380	#endif
	381
	382	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	383	#define CFG_MAXARGS 16 /* max number of command args */
	384	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	385	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
	386
	387	#undef CONFIG_WATCHDOG /* watchdog disabled */
	388
	389	/*
	390	* For booting Linux, the board info and command line data
	391	* have to be in the first 8 MB of memory, since this is
	392	* the maximum mapped by the Linux kernel during initialization.
	393	*/
	394	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
	395
	396	/*
	397	* Cache Configuration
	398	*/
	399	#define CFG_DCACHE_SIZE 32768
	400	#define CFG_CACHELINE_SIZE 32
	401	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	402	#define CFG_CACHELINE_SHIFT 5 /log base 2 of the above value/
	403	#endif
	404
	405	#define CFG_HRCW_LOW (\
	406	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	407	HRCWL_DDR_TO_SCB_CLK_1X1 \|\
	408	HRCWL_CSB_TO_CLKIN_4X1 \|\
	409	HRCWL_VCO_1X2 \|\
	410	HRCWL_CORE_TO_CSB_2X1)
	411
	412	#if defined(PCI_64BIT)
	413	#define CFG_HRCW_HIGH (\
	414	HRCWH_PCI_HOST \|\
	415	HRCWH_64_BIT_PCI \|\
	416	HRCWH_PCI1_ARBITER_ENABLE \|\
	417	HRCWH_PCI2_ARBITER_DISABLE \|\
	418	HRCWH_CORE_ENABLE \|\
	419	HRCWH_FROM_0X00000100 \|\
	420	HRCWH_BOOTSEQ_DISABLE \|\
	421	HRCWH_SW_WATCHDOG_DISABLE \|\
	422	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	423	HRCWH_TSEC1M_IN_GMII \|\
	424	HRCWH_TSEC2M_IN_GMII )
	425	#else
	426	#define CFG_HRCW_HIGH (\
	427	HRCWH_PCI_HOST \|\
	428	HRCWH_32_BIT_PCI \|\
	429	HRCWH_PCI1_ARBITER_ENABLE \|\
6902df56	430	HRCWH_PCI2_ARBITER_DISABLE \|\
e6f2e902 MB	431	HRCWH_CORE_ENABLE \|\
	432	HRCWH_FROM_0X00000100 \|\
	433	HRCWH_BOOTSEQ_DISABLE \|\
	434	HRCWH_SW_WATCHDOG_DISABLE \|\
	435	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	436	HRCWH_TSEC1M_IN_GMII \|\
	437	HRCWH_TSEC2M_IN_GMII )
	438	#endif
	439
9260a561 KG	440	/* System IO Config */
	441	#define CFG_SICRH SICRH_TSOBI1
	442	#define CFG_SICRL SICRL_LDP_A
	443
e6f2e902	444	/* i-cache and d-cache disabled */
6fe16a87 RJ	445	#define CFG_HID0_INIT 0x000000000
	446	#define CFG_HID0_FINAL CFG_HID0_INIT
	447	#define CFG_HID2 HID2_HBE
e6f2e902	448
2688e2f9 KG	449	/* DDR 0 - 512M */
	450	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	451	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	452	#define CFG_IBAT1L (CFG_SDRAM_BASE + 0x10000000 \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	453	#define CFG_IBAT1U (CFG_SDRAM_BASE + 0x10000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	454
	455	/* stack in DCACHE @ 512M (no backing mem) */
	456	#define CFG_IBAT2L (CFG_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	457	#define CFG_IBAT2U (CFG_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	458
	459	/* PCI */
6fe16a87 RJ	460	#ifdef CONFIG_PCI
6fe16a87 RJ	461	#define CFG_IBAT3L (CFG_PCI1_MEM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
2688e2f9	462	#define CFG_IBAT3U (CFG_PCI1_MEM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
6fe16a87	463	#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 \| BATL_PP_10 \| BATL_MEMCOHERENCE)
2688e2f9 KG	464	#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	465	#define CFG_IBAT5L (CFG_PCI1_IO_BASE \| BATL_PP_10 \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	466	#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 \| BATU_BL_16M \| BATU_VS \| BATU_VP)
6fe16a87 RJ	467	#else
	468	#define CFG_IBAT3L (0)
	469	#define CFG_IBAT3U (0)
	470	#define CFG_IBAT4L (0)
	471	#define CFG_IBAT4U (0)
	472	#define CFG_IBAT5L (0)
	473	#define CFG_IBAT5U (0)
	474	#endif
2688e2f9 KG	475
2688e2f9 KG	476	/* IMMRBAR */
d239d74b TT	477	#define CFG_IBAT6L (CFG_IMMR \| BATL_PP_10 \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
d239d74b TT	478	#define CFG_IBAT6U (CFG_IMMR \| BATU_BL_1M \| BATU_VS \| BATU_VP)
2688e2f9 KG	479
	480	/* FLASH */
	481	#define CFG_IBAT7L (CFG_FLASH_BASE \| BATL_PP_10 \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	482	#define CFG_IBAT7U (CFG_FLASH_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	483
	484	#define CFG_DBAT0L CFG_IBAT0L
	485	#define CFG_DBAT0U CFG_IBAT0U
	486	#define CFG_DBAT1L CFG_IBAT1L
	487	#define CFG_DBAT1U CFG_IBAT1U
	488	#define CFG_DBAT2L CFG_IBAT2L
	489	#define CFG_DBAT2U CFG_IBAT2U
	490	#define CFG_DBAT3L CFG_IBAT3L
	491	#define CFG_DBAT3U CFG_IBAT3U
	492	#define CFG_DBAT4L CFG_IBAT4L
	493	#define CFG_DBAT4U CFG_IBAT4U
	494	#define CFG_DBAT5L CFG_IBAT5L
	495	#define CFG_DBAT5U CFG_IBAT5U
	496	#define CFG_DBAT6L CFG_IBAT6L
	497	#define CFG_DBAT6U CFG_IBAT6U
	498	#define CFG_DBAT7L CFG_IBAT7L
	499	#define CFG_DBAT7U CFG_IBAT7U
	500
e6f2e902 MB	501	/*
	502	* Internal Definitions
	503	*
	504	* Boot Flags
	505	*/
	506	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	507	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	508
	509	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	510	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
	511	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	512	#endif
	513
	514	/*
	515	* Environment Configuration
	516	*/
	517
	518	#if defined(CONFIG_TSEC_ENET)
	519	#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
	520	#define CONFIG_HAS_ETH1
	521	#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
	522	#endif
	523
	524	#define CONFIG_IPADDR 192.168.205.1
	525
	526	#define CONFIG_HOSTNAME tqm8349
	527	#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
	528	#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage
	529
	530	#define CONFIG_SERVERIP 192.168.1.1
	531	#define CONFIG_GATEWAYIP 192.168.1.1
	532	#define CONFIG_NETMASK 255.255.255.0
	533
	534	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	535
	536	#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
	537	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	538
	539	#define CONFIG_BAUDRATE 115200
	540
	541	#define CONFIG_PREBOOT "echo;" \
	542	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	543	"echo"
	544
	545	#undef CONFIG_BOOTARGS
	546
	547	#define CONFIG_EXTRA_ENV_SETTINGS \
	548	"netdev=eth0\0" \
	549	"hostname=tqm83xx\0" \
	550	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	551	"nfsroot=${serverip}:${rootpath}\0" \
e6f2e902	552	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	553	"addip=setenv bootargs ${bootargs} " \
	554	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	555	":${hostname}:${netdev}:off panic=1\0" \
	556	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
e6f2e902	557	"flash_nfs=run nfsargs addip addtty;" \
fe126d8b	558	"bootm ${kernel_addr}\0" \
e6f2e902	559	"flash_self=run ramargs addip addtty;" \
fe126d8b WD	560	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	561	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
e6f2e902 MB	562	"bootm\0" \
	563	"rootpath=/opt/eldk/ppc_6xx\0" \
	564	"bootfile=/tftpboot/tqm83xx/uImage\0" \
	565	"kernel_addr=80060000\0" \
	566	"ramdisk_addr=80160000\0" \
	567	"load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \
	568	"update=protect off 80000000 8003ffff; " \
	569	"era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
	570	"upd=run load;run update\0" \
	571	""
	572
	573	#define CONFIG_BOOTCOMMAND "run flash_self"
	574
	575	/*
	576	* JFFS2 partitions
	577	*/
	578	/* mtdparts command line support */
	579	#define CONFIG_JFFS2_CMDLINE
	580	#define MTDIDS_DEFAULT "nor0=TQM834x-0"
	581
	582	/* default mtd partition table */
	583	#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
	584	"1m(kernel),2m(initrd),"\
	585	"-(user);"\
	586
	587	#endif /* __CONFIG_H */