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f4675560 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2000-2005 |
f4675560 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ | |
37 | #define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ | |
38 | ||
39 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
40 | #undef CONFIG_8xx_CONS_SMC2 | |
41 | #undef CONFIG_8xx_CONS_NONE | |
42 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
f4675560 | 43 | |
ae3af05e WD |
44 | #define CONFIG_BOOTCOUNT_LIMIT |
45 | ||
46 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
f4675560 WD |
47 | |
48 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
49 | ||
32bf3d14 | 50 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
f4675560 WD |
51 | |
52 | #undef CONFIG_BOOTARGS | |
6aff3115 WD |
53 | |
54 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
ae3af05e | 55 | "netdev=eth0\0" \ |
6aff3115 | 56 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b | 57 | "nfsroot=${serverip}:${rootpath}\0" \ |
6aff3115 | 58 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
59 | "addip=setenv bootargs ${bootargs} " \ |
60 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
61 | ":${hostname}:${netdev}:off panic=1\0" \ | |
6aff3115 | 62 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 63 | "bootm ${kernel_addr}\0" \ |
6aff3115 | 64 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
65 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
66 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
6aff3115 | 67 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
5e4be00f | 68 | "bootfile=/tftpboot/TQM850L/uImage\0" \ |
eb6da805 WD |
69 | "fdt_addr=40040000\0" \ |
70 | "kernel_addr=40060000\0" \ | |
71 | "ramdisk_addr=40200000\0" \ | |
6aff3115 WD |
72 | "" |
73 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
f4675560 WD |
74 | |
75 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
76 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
77 | ||
78 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
79 | ||
80 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
81 | ||
82 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
83 | ||
37d4bb70 JL |
84 | /* |
85 | * BOOTP options | |
86 | */ | |
87 | #define CONFIG_BOOTP_SUBNETMASK | |
88 | #define CONFIG_BOOTP_GATEWAY | |
89 | #define CONFIG_BOOTP_HOSTNAME | |
90 | #define CONFIG_BOOTP_BOOTPATH | |
91 | #define CONFIG_BOOTP_BOOTFILESIZE | |
92 | ||
f4675560 WD |
93 | |
94 | #define CONFIG_MAC_PARTITION | |
95 | #define CONFIG_DOS_PARTITION | |
96 | ||
97 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
98 | ||
2694690e JL |
99 | /* |
100 | * Command line configuration. | |
101 | */ | |
102 | #include <config_cmd_default.h> | |
103 | ||
104 | #define CONFIG_CMD_ASKENV | |
105 | #define CONFIG_CMD_DATE | |
106 | #define CONFIG_CMD_DHCP | |
107 | #define CONFIG_CMD_IDE | |
108 | #define CONFIG_CMD_NFS | |
109 | #define CONFIG_CMD_SNTP | |
f4675560 | 110 | |
f4675560 WD |
111 | |
112 | /* | |
113 | * Miscellaneous configurable options | |
114 | */ | |
115 | #define CFG_LONGHELP /* undef to save memory */ | |
6aff3115 WD |
116 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
117 | ||
2751a95a WD |
118 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
119 | #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ | |
6aff3115 WD |
120 | #ifdef CFG_HUSH_PARSER |
121 | #define CFG_PROMPT_HUSH_PS2 "> " | |
122 | #endif | |
123 | ||
2694690e | 124 | #if defined(CONFIG_CMD_KGDB) |
6aff3115 | 125 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
f4675560 | 126 | #else |
6aff3115 | 127 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
f4675560 WD |
128 | #endif |
129 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
6aff3115 | 130 | #define CFG_MAXARGS 16 /* max number of command args */ |
f4675560 WD |
131 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
132 | ||
133 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
134 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
135 | ||
136 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
137 | ||
6aff3115 | 138 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
f4675560 WD |
139 | |
140 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
141 | ||
142 | /* | |
143 | * Low Level Configuration Settings | |
144 | * (address mappings, register initial values, etc.) | |
145 | * You should know what you are doing if you make changes here. | |
146 | */ | |
147 | /*----------------------------------------------------------------------- | |
148 | * Internal Memory Mapped Register | |
149 | */ | |
150 | #define CFG_IMMR 0xFFF00000 | |
151 | ||
152 | /*----------------------------------------------------------------------- | |
153 | * Definitions for initial stack pointer and data area (in DPRAM) | |
154 | */ | |
155 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
156 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
157 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
158 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
159 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
160 | ||
161 | /*----------------------------------------------------------------------- | |
162 | * Start addresses for the final memory configuration | |
163 | * (Set up by the startup code) | |
164 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
165 | */ | |
166 | #define CFG_SDRAM_BASE 0x00000000 | |
167 | #define CFG_FLASH_BASE 0x40000000 | |
168 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
169 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
170 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
171 | ||
172 | /* | |
173 | * For booting Linux, the board info and command line data | |
174 | * have to be in the first 8 MB of memory, since this is | |
175 | * the maximum mapped by the Linux kernel during initialization. | |
176 | */ | |
177 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
178 | ||
179 | /*----------------------------------------------------------------------- | |
180 | * FLASH organization | |
181 | */ | |
f4675560 | 182 | |
e318d9e9 MK |
183 | /* use CFI flash driver */ |
184 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ | |
185 | #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
186 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } | |
187 | #define CFG_FLASH_EMPTY_INFO | |
188 | #define CFG_FLASH_USE_BUFFER_WRITE 1 | |
189 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
190 | #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
f4675560 WD |
191 | |
192 | #define CFG_ENV_IS_IN_FLASH 1 | |
193 | #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ | |
194 | #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
195 | ||
196 | /* Address and size of Redundant Environment Sector */ | |
197 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) | |
198 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
199 | ||
67c31036 WD |
200 | #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
201 | ||
f4675560 WD |
202 | /*----------------------------------------------------------------------- |
203 | * Hardware Information Block | |
204 | */ | |
205 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
206 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
207 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
208 | ||
209 | /*----------------------------------------------------------------------- | |
210 | * Cache Configuration | |
211 | */ | |
212 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
2694690e | 213 | #if defined(CONFIG_CMD_KGDB) |
f4675560 WD |
214 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
215 | #endif | |
216 | ||
217 | /*----------------------------------------------------------------------- | |
218 | * SYPCR - System Protection Control 11-9 | |
219 | * SYPCR can only be written once after reset! | |
220 | *----------------------------------------------------------------------- | |
221 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
222 | */ | |
223 | #if defined(CONFIG_WATCHDOG) | |
224 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
225 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
226 | #else | |
227 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
228 | #endif | |
229 | ||
230 | /*----------------------------------------------------------------------- | |
231 | * SIUMCR - SIU Module Configuration 11-6 | |
232 | *----------------------------------------------------------------------- | |
233 | * PCMCIA config., multi-function pin tri-state | |
234 | */ | |
235 | #ifndef CONFIG_CAN_DRIVER | |
236 | #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
237 | #else /* we must activate GPL5 in the SIUMCR for CAN */ | |
238 | #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
239 | #endif /* CONFIG_CAN_DRIVER */ | |
240 | ||
241 | /*----------------------------------------------------------------------- | |
242 | * TBSCR - Time Base Status and Control 11-26 | |
243 | *----------------------------------------------------------------------- | |
244 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
245 | */ | |
246 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
247 | ||
248 | /*----------------------------------------------------------------------- | |
249 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
250 | *----------------------------------------------------------------------- | |
251 | */ | |
252 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
253 | ||
254 | /*----------------------------------------------------------------------- | |
255 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
256 | *----------------------------------------------------------------------- | |
257 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
258 | */ | |
259 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
260 | ||
261 | /*----------------------------------------------------------------------- | |
262 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
263 | *----------------------------------------------------------------------- | |
264 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
265 | * interrupt status bit | |
f4675560 | 266 | */ |
f4675560 | 267 | #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
f4675560 WD |
268 | |
269 | /*----------------------------------------------------------------------- | |
270 | * SCCR - System Clock and reset Control Register 15-27 | |
271 | *----------------------------------------------------------------------- | |
272 | * Set clock output, timebase and RTC source and divider, | |
273 | * power management and some other internal clocks | |
274 | */ | |
275 | #define SCCR_MASK SCCR_EBDF11 | |
e9132ea9 | 276 | #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
f4675560 WD |
277 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
278 | SCCR_DFALCD00) | |
f4675560 WD |
279 | |
280 | /*----------------------------------------------------------------------- | |
281 | * PCMCIA stuff | |
282 | *----------------------------------------------------------------------- | |
283 | * | |
284 | */ | |
285 | #define CFG_PCMCIA_MEM_ADDR (0xE0000000) | |
286 | #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
287 | #define CFG_PCMCIA_DMA_ADDR (0xE4000000) | |
288 | #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
289 | #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) | |
290 | #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
291 | #define CFG_PCMCIA_IO_ADDR (0xEC000000) | |
292 | #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) | |
293 | ||
294 | /*----------------------------------------------------------------------- | |
295 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
296 | *----------------------------------------------------------------------- | |
297 | */ | |
298 | ||
299 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
300 | ||
301 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
302 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
303 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
304 | ||
305 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
306 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
307 | ||
308 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
309 | ||
310 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR | |
311 | ||
312 | /* Offset for data I/O */ | |
313 | #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) | |
314 | ||
315 | /* Offset for normal register accesses */ | |
316 | #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) | |
317 | ||
318 | /* Offset for alternate registers */ | |
319 | #define CFG_ATA_ALT_OFFSET 0x0100 | |
320 | ||
f4675560 WD |
321 | /*----------------------------------------------------------------------- |
322 | * | |
323 | *----------------------------------------------------------------------- | |
324 | * | |
325 | */ | |
f4675560 WD |
326 | #define CFG_DER 0 |
327 | ||
328 | /* | |
329 | * Init Memory Controller: | |
330 | * | |
331 | * BR0/1 and OR0/1 (FLASH) | |
332 | */ | |
333 | ||
334 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
335 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
336 | ||
337 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
338 | * restrict access enough to keep SRAM working (if any) | |
339 | * but not too much to meddle with FLASH accesses | |
340 | */ | |
341 | #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
342 | #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
343 | ||
344 | /* | |
345 | * FLASH timing: | |
346 | */ | |
f4675560 WD |
347 | #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
348 | OR_SCY_3_CLK | OR_EHTR | OR_BI) | |
f4675560 WD |
349 | |
350 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) | |
351 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
352 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
353 | ||
354 | #define CFG_OR1_REMAP CFG_OR0_REMAP | |
355 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM | |
356 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
357 | ||
358 | /* | |
359 | * BR2/3 and OR2/3 (SDRAM) | |
360 | * | |
361 | */ | |
362 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
363 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
364 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
365 | ||
366 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
367 | #define CFG_OR_TIMING_SDRAM 0x00000A00 | |
368 | ||
369 | #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) | |
370 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
371 | ||
372 | #ifndef CONFIG_CAN_DRIVER | |
373 | #define CFG_OR3_PRELIM CFG_OR2_PRELIM | |
374 | #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
375 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ | |
376 | #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ | |
377 | #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
378 | #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) | |
379 | #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ | |
380 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
381 | #endif /* CONFIG_CAN_DRIVER */ | |
382 | ||
383 | /* | |
384 | * Memory Periodic Timer Prescaler | |
385 | * | |
386 | * The Divider for PTA (refresh timer) configuration is based on an | |
387 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
388 | * the number of chip selects (NCS) and the actually needed refresh | |
389 | * rate is done by setting MPTPR. | |
390 | * | |
391 | * PTA is calculated from | |
392 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
393 | * | |
394 | * gclk CPU clock (not bus clock!) | |
395 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
396 | * | |
397 | * 4096 Rows from SDRAM example configuration | |
398 | * 1000 factor s -> ms | |
399 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
400 | * 4 Number of refresh cycles per period | |
401 | * 64 Refresh cycle in ms per number of rows | |
402 | * -------------------------------------------- | |
403 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
404 | * | |
405 | * 50 MHz => 50.000.000 / Divider = 98 | |
406 | * 66 Mhz => 66.000.000 / Divider = 129 | |
407 | * 80 Mhz => 80.000.000 / Divider = 156 | |
408 | */ | |
e9132ea9 WD |
409 | |
410 | #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) | |
411 | #define CFG_MAMR_PTA 98 | |
f4675560 WD |
412 | |
413 | /* | |
414 | * For 16 MBit, refresh rates could be 31.3 us | |
415 | * (= 64 ms / 2K = 125 / quad bursts). | |
416 | * For a simpler initialization, 15.6 us is used instead. | |
417 | * | |
418 | * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks | |
419 | * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
420 | */ | |
421 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ | |
422 | #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
423 | ||
424 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
425 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ | |
426 | #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
427 | ||
428 | /* | |
429 | * MAMR settings for SDRAM | |
430 | */ | |
431 | ||
432 | /* 8 column SDRAM */ | |
433 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
434 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
435 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
436 | /* 9 column SDRAM */ | |
437 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
438 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
439 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
440 | ||
441 | ||
442 | /* | |
443 | * Internal Definitions | |
444 | * | |
445 | * Boot Flags | |
446 | */ | |
447 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
448 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
449 | ||
450 | #endif /* __CONFIG_H */ |