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d96f41e0 SR |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * Wolfgang Denk <wd@denx.de> | |
6 | * Copyright 2004 Freescale Semiconductor. | |
7 | * (C) Copyright 2002,2003 Motorola,Inc. | |
8 | * Xianghua Xiao <X.Xiao@motorola.com> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | /* | |
30 | * TQM85xx (8560/40/55/41) board configuration file | |
31 | */ | |
32 | ||
33 | #ifndef __CONFIG_H | |
34 | #define __CONFIG_H | |
35 | ||
36 | /* High Level Configuration Options */ | |
37 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
38 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
39 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ | |
40 | ||
41 | #define CONFIG_PCI | |
42 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
43 | ||
44 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
45 | ||
46 | /* | |
47 | * Only MPC8540 doesn't have CPM module | |
48 | */ | |
49 | #ifndef CONFIG_MPC8540 | |
50 | #define CONFIG_CPM2 1 /* has CPM2 */ | |
51 | #endif | |
52 | ||
53 | /* | |
54 | * sysclk for MPC85xx | |
55 | * | |
56 | * Two valid values are: | |
57 | * 33000000 | |
58 | * 66000000 | |
59 | * | |
60 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
61 | * is likely the desired value here, so that is now the default. | |
62 | * The board, however, can run at 66MHz. In any event, this value | |
63 | * must match the settings of some switches. Details can be found | |
64 | * in the README.mpc85xxads. | |
65 | */ | |
66 | ||
67 | #ifndef CONFIG_SYS_CLK_FREQ | |
68 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
69 | #endif | |
70 | ||
71 | /* | |
72 | * These can be toggled for performance analysis, otherwise use default. | |
73 | */ | |
74 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
75 | #define CONFIG_BTB /* toggle branch predition */ | |
76 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
77 | ||
78 | #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ | |
79 | ||
80 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
81 | #define CFG_MEMTEST_START 0x00000000 | |
82 | #define CFG_MEMTEST_END 0x10000000 | |
83 | ||
84 | /* | |
85 | * Base addresses -- Note these are effective addresses where the | |
86 | * actual resources get mapped (not physical addresses) | |
87 | */ | |
88 | #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ | |
89 | #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ | |
90 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ | |
91 | ||
92 | /* | |
93 | * DDR Setup | |
94 | */ | |
95 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ | |
96 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
97 | #define CONFIG_ADD_RAM_INFO 1 /* print additional info*/ | |
98 | ||
99 | #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) | |
100 | /* TQM8540 & 8560 need DLL-override */ | |
101 | #define CONFIG_DDR_DLL /* DLL fix needed */ | |
102 | #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ | |
103 | #endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */ | |
104 | ||
105 | #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) | |
106 | #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ | |
107 | #endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */ | |
108 | ||
109 | /* | |
110 | * Flash on the Local Bus | |
111 | */ | |
112 | #define CFG_FLASH0 0xFC000000 | |
113 | #define CFG_FLASH1 0xF8000000 | |
114 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } | |
115 | ||
116 | #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ | |
117 | #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ | |
118 | ||
119 | #define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ | |
120 | #define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ | |
121 | #define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ | |
122 | #define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */ | |
123 | ||
124 | #define CFG_FLASH_CFI /* flash is CFI compat. */ | |
125 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ | |
126 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ | |
127 | #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ | |
128 | ||
129 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ | |
130 | #define CFG_MAX_FLASH_SECT 512 /* sectors per device */ | |
131 | #undef CFG_FLASH_CHECKSUM | |
132 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
133 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
134 | ||
135 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
136 | ||
137 | #define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ | |
138 | #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ | |
139 | #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
140 | #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ | |
141 | ||
142 | #define CONFIG_L1_INIT_RAM | |
143 | #define CFG_INIT_RAM_LOCK 1 | |
144 | #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
145 | #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ | |
146 | ||
147 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ | |
148 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
149 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
150 | ||
151 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ | |
152 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
153 | ||
154 | /* Serial Port */ | |
155 | #if defined(CONFIG_TQM8560) | |
156 | ||
157 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
158 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
159 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
160 | ||
966083e9 | 161 | #else /* ! TQM8560 */ |
d96f41e0 SR |
162 | |
163 | #define CONFIG_CONS_INDEX 1 | |
164 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
165 | #define CFG_NS16550 | |
166 | #define CFG_NS16550_SERIAL | |
167 | #define CFG_NS16550_REG_SIZE 1 | |
168 | #define CFG_NS16550_CLK get_bus_freq(0) | |
169 | ||
170 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
171 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
172 | ||
bc8bb6d4 | 173 | /* PS/2 Keyboard */ |
bd3143f0 | 174 | #if !defined(CONFIG_TQM8560) |
bc8bb6d4 WD |
175 | #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ |
176 | #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ | |
177 | #define CONFIG_PS2SERIAL 2 /* .. on DUART2 */ | |
178 | #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ | |
179 | #define CONFIG_BOARD_EARLY_INIT_R 1 | |
bd3143f0 | 180 | #endif /* !CONFIG_TQM8560 */ |
bc8bb6d4 | 181 | |
966083e9 WD |
182 | #endif /* CONFIG_TQM8560 */ |
183 | ||
184 | #define CONFIG_BAUDRATE 115200 | |
185 | ||
186 | #define CFG_BAUDRATE_TABLE \ | |
187 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
188 | ||
d96f41e0 SR |
189 | /* Use the HUSH parser */ |
190 | #define CFG_HUSH_PARSER | |
191 | #ifdef CFG_HUSH_PARSER | |
192 | #define CFG_PROMPT_HUSH_PS2 "> " | |
193 | #endif | |
194 | ||
195 | /* I2C */ | |
196 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
197 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
198 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
199 | #define CFG_I2C_SLAVE 0x7F | |
200 | #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ | |
201 | ||
202 | /* I2C RTC */ | |
203 | #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ | |
204 | #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
205 | ||
206 | /* I2C EEPROM */ | |
207 | /* | |
208 | * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also). | |
209 | */ | |
210 | #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ | |
211 | #define CFG_I2C_EEPROM_ADDR_LEN 2 | |
212 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
213 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
214 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
215 | #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ | |
216 | ||
217 | /* I2C SYSMON (LM75) */ | |
218 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
219 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
220 | #define CFG_DTT_MAX_TEMP 70 | |
221 | #define CFG_DTT_LOW_TEMP -30 | |
222 | #define CFG_DTT_HYSTERESIS 3 | |
223 | ||
224 | /* RapidIO MMU */ | |
225 | #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ | |
226 | #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE | |
227 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ | |
228 | ||
229 | /* | |
230 | * General PCI | |
231 | * Addresses are mapped 1-1. | |
232 | */ | |
233 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
234 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
235 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
236 | #define CFG_PCI1_IO_BASE 0xe2000000 | |
237 | #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE | |
238 | #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ | |
239 | ||
240 | #if defined(CONFIG_PCI) | |
241 | ||
242 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
243 | ||
244 | #define CONFIG_EEPRO100 | |
245 | #undef CONFIG_TULIP | |
246 | ||
247 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
248 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
249 | ||
250 | #endif /* CONFIG_PCI */ | |
251 | ||
252 | ||
253 | #define CONFIG_NET_MULTI 1 | |
254 | ||
255 | #define CONFIG_MII 1 /* MII PHY management */ | |
256 | #define CONFIG_MPC85XX_TSEC1 1 | |
257 | #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" | |
258 | #define CONFIG_MPC85XX_TSEC2 1 | |
259 | #define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" | |
260 | #define TSEC1_PHY_ADDR 2 | |
261 | #define TSEC2_PHY_ADDR 1 | |
262 | #define TSEC1_PHYIDX 0 | |
263 | #define TSEC2_PHYIDX 0 | |
264 | #define FEC_PHY_ADDR 3 | |
265 | #define FEC_PHYIDX 0 | |
266 | #define CONFIG_HAS_ETH1 | |
267 | #define CONFIG_HAS_ETH2 | |
268 | ||
269 | /* Options are TSEC[0-1], FEC */ | |
270 | #define CONFIG_ETHPRIME "TSEC0" | |
271 | ||
272 | #if defined(CONFIG_TQM8540) | |
273 | /* | |
274 | * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC. | |
275 | * The FEC port is connected on the same signals as the FCC3 port | |
276 | * of the TQM8560 to the baseboard (STK85xx Starterkit). | |
277 | * | |
278 | * On the STK85xx Starterkit the X47/X50 jumper has to be set to | |
279 | * a - d (X50.2 - 3) to enable the FEC port. | |
280 | */ | |
281 | #define CONFIG_MPC85XX_FEC 1 | |
282 | #define CONFIG_MPC85XX_FEC_NAME "FEC" | |
283 | #endif | |
284 | ||
285 | #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) | |
286 | /* | |
287 | * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port | |
288 | * can be used at once, since only one FCC port is available on the STK85xx | |
289 | * Starterkit. | |
290 | * | |
291 | * To use this port you have to configure U-Boot to use the FCC port 1...2 | |
292 | * and set the X47/X50 jumper to: | |
293 | * FCC1: a - b (X47.2 - X50.2) | |
294 | * FCC2: a - c (X50.2 - 1) | |
295 | */ | |
296 | #define CONFIG_ETHER_ON_FCC | |
297 | #define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ | |
298 | #endif | |
299 | ||
300 | #if defined(CONFIG_TQM8560) | |
301 | /* | |
302 | * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port | |
303 | * can be used at once, since only one FCC port is available on the STK85xx | |
304 | * Starterkit. | |
305 | * | |
306 | * To use this port you have to configure U-Boot to use the FCC port 1...3 | |
307 | * and set the X47/X50 jumper to: | |
308 | * FCC1: a - b (X47.2 - X50.2) | |
309 | * FCC2: a - c (X50.2 - 1) | |
310 | * FCC3: a - d (X50.2 - 3) | |
311 | */ | |
312 | #define CONFIG_ETHER_ON_FCC | |
313 | #define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ | |
314 | #endif | |
315 | ||
316 | #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) | |
317 | #define CONFIG_ETHER_ON_FCC1 | |
318 | #define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) | |
319 | #define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) | |
320 | #define CFG_CPMFCR_RAMTYPE 0 | |
321 | #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
322 | #endif | |
323 | ||
324 | #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
325 | #define CONFIG_ETHER_ON_FCC2 | |
326 | #define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) | |
327 | #define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13) | |
328 | #define CFG_CPMFCR_RAMTYPE 0 | |
329 | #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
330 | #endif | |
331 | ||
332 | #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) | |
333 | #define CONFIG_ETHER_ON_FCC3 | |
334 | #define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) | |
335 | #define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) | |
336 | #define CFG_CPMFCR_RAMTYPE 0 | |
337 | #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
338 | #endif | |
339 | ||
340 | /* | |
341 | * Environment | |
342 | */ | |
343 | #define CFG_ENV_IS_IN_FLASH 1 | |
344 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) | |
345 | #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
346 | #define CFG_ENV_SIZE 0x2000 | |
347 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
348 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
349 | ||
350 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
351 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
352 | ||
353 | #define CONFIG_TIMESTAMP /* Print image info with ts */ | |
354 | ||
355 | #if defined(CONFIG_PCI) | |
356 | # define ADD_PCI_CMD (CFG_CMD_PCI) | |
357 | #else | |
358 | # define ADD_PCI_CMD 0 | |
359 | #endif | |
360 | ||
361 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ | |
362 | CFG_CMD_DHCP | \ | |
363 | CFG_CMD_NFS | \ | |
364 | CFG_CMD_SNTP | \ | |
365 | ADD_PCI_CMD | \ | |
366 | CFG_CMD_I2C | \ | |
367 | CFG_CMD_DATE | \ | |
368 | CFG_CMD_EEPROM | \ | |
369 | CFG_CMD_DTT | \ | |
370 | CFG_CMD_MII | \ | |
371 | CFG_CMD_PING ) | |
372 | #include <cmd_confdefs.h> | |
373 | ||
374 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
375 | ||
376 | /* | |
377 | * Miscellaneous configurable options | |
378 | */ | |
379 | #define CFG_LONGHELP /* undef to save memory */ | |
380 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
381 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
382 | ||
383 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
384 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
385 | #else | |
386 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
387 | #endif | |
388 | ||
389 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ | |
390 | #define CFG_MAXARGS 16 /* max number of command args */ | |
391 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
392 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
393 | ||
394 | /* | |
395 | * For booting Linux, the board info and command line data | |
396 | * have to be in the first 8 MB of memory, since this is | |
397 | * the maximum mapped by the Linux kernel during initialization. | |
398 | */ | |
399 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
400 | ||
401 | /* Cache Configuration */ | |
402 | #define CFG_DCACHE_SIZE 32768 | |
403 | #define CFG_CACHELINE_SIZE 32 | |
404 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
405 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ | |
406 | #endif | |
407 | ||
408 | /* | |
409 | * Internal Definitions | |
410 | * | |
411 | * Boot Flags | |
412 | */ | |
413 | #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ | |
414 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
415 | ||
416 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
417 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ | |
418 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
419 | #endif | |
420 | ||
421 | ||
422 | #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ | |
423 | ||
424 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ | |
425 | ||
426 | #define CONFIG_PREBOOT "echo;" \ | |
d8519dc7 | 427 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
d96f41e0 SR |
428 | "echo" |
429 | ||
430 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
431 | ||
432 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
433 | CFG_BOOTFILE \ | |
434 | "netdev=eth0\0" \ | |
435 | "consdev=ttyS0\0" \ | |
436 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
437 | "nfsroot=$serverip:$rootpath\0" \ | |
438 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
439 | "addip=setenv bootargs $bootargs " \ | |
440 | "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ | |
441 | ":$hostname:$netdev:off panic=1\0" \ | |
442 | "addcons=setenv bootargs $bootargs " \ | |
443 | "console=$consdev,$baudrate\0" \ | |
444 | "flash_nfs=run nfsargs addip addcons;" \ | |
445 | "bootm $kernel_addr\0" \ | |
446 | "flash_self=run ramargs addip addcons;" \ | |
447 | "bootm $kernel_addr $ramdisk_addr\0" \ | |
448 | "net_nfs=tftp $loadaddr $bootfile;" \ | |
449 | "run nfsargs addip addcons;bootm\0" \ | |
450 | "rootpath=/opt/eldk/ppc_85xx\0" \ | |
451 | "kernel_addr=FE000000\0" \ | |
015c200b | 452 | "ramdisk_addr=FE180000\0" \ |
d96f41e0 SR |
453 | "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ |
454 | "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ | |
455 | "cp.b 100000 fffc0000 40000;" \ | |
456 | "setenv filesize;saveenv\0" \ | |
457 | "upd=run load;run update\0" \ | |
458 | "" | |
459 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
460 | ||
461 | #endif /* __CONFIG_H */ |