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090eb735 MK |
1 | /* |
2 | * (C) Copyright 2000-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* | |
28 | * board/config.h - configuration options, board specific | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
34 | /* | |
35 | * High Level Configuration Options | |
36 | * (easy to change) | |
37 | */ | |
38 | ||
39 | #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ | |
40 | #define CONFIG_TQM885D 1 /* ...on a TQM88D module */ | |
41 | ||
2ae18241 WD |
42 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
43 | ||
090eb735 | 44 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ |
6d0f6bcf JCPV |
45 | #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ |
46 | #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ | |
22d1a56c | 47 | #define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ |
090eb735 MK |
48 | /* (it will be used if there is no */ |
49 | /* 'cpuclk' variable with valid value) */ | |
50 | ||
090eb735 | 51 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
3cb7a480 WD |
52 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
53 | #define CONFIG_SYS_MAXIDLE 10 | |
090eb735 MK |
54 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
55 | ||
56 | #define CONFIG_BOOTCOUNT_LIMIT | |
57 | ||
58 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
59 | ||
60 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
61 | ||
62 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 63 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
090eb735 MK |
64 | "echo" |
65 | ||
66 | #undef CONFIG_BOOTARGS | |
67 | ||
68 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
69 | "netdev=eth0\0" \ | |
70 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
71 | "nfsroot=${serverip}:${rootpath}\0" \ | |
72 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
73 | "addip=setenv bootargs ${bootargs} " \ | |
74 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
75 | ":${hostname}:${netdev}:off panic=1\0" \ | |
76 | "flash_nfs=run nfsargs addip;" \ | |
77 | "bootm ${kernel_addr}\0" \ | |
78 | "flash_self=run ramargs addip;" \ | |
79 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
80 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
81 | "rootpath=/opt/eldk/ppc_8xx\0" \ | |
11d9eec4 MK |
82 | "bootfile=/tftpboot/TQM885D/uImage\0" \ |
83 | "fdt_addr=400C0000\0" \ | |
84 | "kernel_addr=40100000\0" \ | |
85 | "ramdisk_addr=40280000\0" \ | |
86 | "load=tftp 200000 ${u-boot}\0" \ | |
87 | "update=protect off 40000000 +${filesize};" \ | |
88 | "erase 40000000 +${filesize};" \ | |
89 | "cp.b 200000 40000000 ${filesize};" \ | |
90 | "protect on 40000000 +${filesize}\0" \ | |
090eb735 MK |
91 | "" |
92 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
93 | ||
94 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 95 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
090eb735 MK |
96 | |
97 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
98 | ||
99 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
100 | ||
101 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
102 | ||
103 | /* enable I2C and select the hardware/software driver */ | |
104 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
105 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
106 | ||
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ |
108 | #define CONFIG_SYS_I2C_SLAVE 0xFE | |
090eb735 MK |
109 | |
110 | #ifdef CONFIG_SOFT_I2C | |
111 | /* | |
112 | * Software (bit-bang) I2C driver configuration | |
113 | */ | |
114 | #define PB_SCL 0x00000020 /* PB 26 */ | |
115 | #define PB_SDA 0x00000010 /* PB 27 */ | |
116 | ||
117 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
118 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
119 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
120 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
121 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
122 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
123 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
124 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
125 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ | |
126 | #endif /* CONFIG_SOFT_I2C */ | |
127 | ||
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ |
129 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ | |
130 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
131 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
090eb735 MK |
132 | |
133 | # define CONFIG_RTC_DS1337 1 | |
6d0f6bcf | 134 | # define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
090eb735 | 135 | |
37d4bb70 JL |
136 | /* |
137 | * BOOTP options | |
138 | */ | |
139 | #define CONFIG_BOOTP_SUBNETMASK | |
140 | #define CONFIG_BOOTP_GATEWAY | |
141 | #define CONFIG_BOOTP_HOSTNAME | |
142 | #define CONFIG_BOOTP_BOOTPATH | |
143 | #define CONFIG_BOOTP_BOOTFILESIZE | |
144 | ||
090eb735 MK |
145 | |
146 | #define CONFIG_MAC_PARTITION | |
147 | #define CONFIG_DOS_PARTITION | |
148 | ||
11d9eec4 | 149 | #undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ |
090eb735 MK |
150 | |
151 | #define CONFIG_TIMESTAMP /* but print image timestmps */ | |
152 | ||
2694690e JL |
153 | |
154 | /* | |
155 | * Command line configuration. | |
156 | */ | |
157 | #include <config_cmd_default.h> | |
158 | ||
159 | #define CONFIG_CMD_ASKENV | |
160 | #define CONFIG_CMD_DATE | |
161 | #define CONFIG_CMD_DHCP | |
162 | #define CONFIG_CMD_EEPROM | |
9a63b7f4 | 163 | #define CONFIG_CMD_EXT2 |
2694690e JL |
164 | #define CONFIG_CMD_I2C |
165 | #define CONFIG_CMD_IDE | |
166 | #define CONFIG_CMD_MII | |
167 | #define CONFIG_CMD_NFS | |
168 | #define CONFIG_CMD_PING | |
169 | ||
090eb735 MK |
170 | |
171 | /* | |
172 | * Miscellaneous configurable options | |
173 | */ | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
175 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
090eb735 | 176 | |
2751a95a | 177 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
6d0f6bcf | 178 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
090eb735 | 179 | |
2694690e | 180 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 181 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
090eb735 | 182 | #else |
6d0f6bcf | 183 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
090eb735 | 184 | #endif |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
186 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
187 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
090eb735 | 188 | |
6d0f6bcf JCPV |
189 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
190 | #define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ | |
191 | #define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive | |
090eb735 MK |
192 | memory test.*/ |
193 | ||
6d0f6bcf | 194 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
090eb735 | 195 | |
6d0f6bcf | 196 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
090eb735 | 197 | |
090eb735 | 198 | /* |
a1aa0bb5 | 199 | * Enable loopw command. |
090eb735 MK |
200 | */ |
201 | #define CONFIG_LOOPW | |
202 | ||
203 | /* | |
204 | * Low Level Configuration Settings | |
205 | * (address mappings, register initial values, etc.) | |
206 | * You should know what you are doing if you make changes here. | |
207 | */ | |
208 | /*----------------------------------------------------------------------- | |
209 | * Internal Memory Mapped Register | |
210 | */ | |
6d0f6bcf | 211 | #define CONFIG_SYS_IMMR 0xFFF00000 |
090eb735 MK |
212 | |
213 | /*----------------------------------------------------------------------- | |
214 | * Definitions for initial stack pointer and data area (in DPRAM) | |
215 | */ | |
6d0f6bcf | 216 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 217 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 218 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 219 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
090eb735 MK |
220 | |
221 | /*----------------------------------------------------------------------- | |
222 | * Start addresses for the final memory configuration | |
223 | * (Set up by the startup code) | |
6d0f6bcf | 224 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
090eb735 | 225 | */ |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
227 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
228 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
229 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
230 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ | |
090eb735 MK |
231 | |
232 | /* | |
233 | * For booting Linux, the board info and command line data | |
234 | * have to be in the first 8 MB of memory, since this is | |
235 | * the maximum mapped by the Linux kernel during initialization. | |
236 | */ | |
6d0f6bcf | 237 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
090eb735 MK |
238 | |
239 | /*----------------------------------------------------------------------- | |
240 | * FLASH organization | |
241 | */ | |
090eb735 | 242 | |
e318d9e9 | 243 | /* use CFI flash driver */ |
6d0f6bcf | 244 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 245 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
247 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
248 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
249 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
250 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
090eb735 | 251 | |
5a1aceb0 | 252 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
253 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
254 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ | |
255 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ | |
090eb735 MK |
256 | |
257 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
258 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
259 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
090eb735 MK |
260 | |
261 | /*----------------------------------------------------------------------- | |
262 | * Hardware Information Block | |
263 | */ | |
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
265 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
266 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
090eb735 MK |
267 | |
268 | /*----------------------------------------------------------------------- | |
269 | * Cache Configuration | |
270 | */ | |
6d0f6bcf | 271 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
2694690e | 272 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 273 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
090eb735 MK |
274 | #endif |
275 | ||
276 | /*----------------------------------------------------------------------- | |
277 | * SYPCR - System Protection Control 11-9 | |
278 | * SYPCR can only be written once after reset! | |
279 | *----------------------------------------------------------------------- | |
280 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
281 | */ | |
282 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 283 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
090eb735 MK |
284 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
285 | #else | |
6d0f6bcf | 286 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
090eb735 MK |
287 | #endif |
288 | ||
289 | /*----------------------------------------------------------------------- | |
290 | * SIUMCR - SIU Module Configuration 11-6 | |
291 | *----------------------------------------------------------------------- | |
292 | * PCMCIA config., multi-function pin tri-state | |
293 | */ | |
294 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf | 295 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
090eb735 | 296 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 297 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
090eb735 MK |
298 | #endif /* CONFIG_CAN_DRIVER */ |
299 | ||
300 | /*----------------------------------------------------------------------- | |
301 | * TBSCR - Time Base Status and Control 11-26 | |
302 | *----------------------------------------------------------------------- | |
303 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
304 | */ | |
6d0f6bcf | 305 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
090eb735 MK |
306 | |
307 | /*----------------------------------------------------------------------- | |
308 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
309 | *----------------------------------------------------------------------- | |
310 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
311 | */ | |
6d0f6bcf | 312 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
090eb735 MK |
313 | |
314 | /*----------------------------------------------------------------------- | |
315 | * SCCR - System Clock and reset Control Register 15-27 | |
316 | *----------------------------------------------------------------------- | |
317 | * Set clock output, timebase and RTC source and divider, | |
318 | * power management and some other internal clocks | |
319 | */ | |
320 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 321 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
090eb735 MK |
322 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
323 | SCCR_DFALCD00) | |
324 | ||
325 | /*----------------------------------------------------------------------- | |
326 | * PCMCIA stuff | |
327 | *----------------------------------------------------------------------- | |
328 | * | |
329 | */ | |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
331 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
332 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
333 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
334 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
335 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
336 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
337 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
090eb735 MK |
338 | |
339 | /*----------------------------------------------------------------------- | |
340 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
341 | *----------------------------------------------------------------------- | |
342 | */ | |
343 | ||
8d1165e1 | 344 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
090eb735 MK |
345 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
346 | ||
347 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
348 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
349 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
350 | ||
6d0f6bcf JCPV |
351 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
352 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
090eb735 | 353 | |
6d0f6bcf | 354 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
090eb735 | 355 | |
6d0f6bcf | 356 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
090eb735 MK |
357 | |
358 | /* Offset for data I/O */ | |
6d0f6bcf | 359 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
090eb735 MK |
360 | |
361 | /* Offset for normal register accesses */ | |
6d0f6bcf | 362 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
090eb735 MK |
363 | |
364 | /* Offset for alternate registers */ | |
6d0f6bcf | 365 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
090eb735 MK |
366 | |
367 | /*----------------------------------------------------------------------- | |
368 | * | |
369 | *----------------------------------------------------------------------- | |
370 | * | |
371 | */ | |
6d0f6bcf | 372 | #define CONFIG_SYS_DER 0 |
090eb735 MK |
373 | |
374 | /* | |
375 | * Init Memory Controller: | |
376 | * | |
377 | * BR0/1 and OR0/1 (FLASH) | |
378 | */ | |
379 | ||
380 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
381 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
382 | ||
383 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
384 | * restrict access enough to keep SRAM working (if any) | |
385 | * but not too much to meddle with FLASH accesses | |
386 | */ | |
6d0f6bcf JCPV |
387 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
388 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
090eb735 MK |
389 | |
390 | /* | |
391 | * FLASH timing: Default value of OR0 after reset | |
392 | */ | |
6d0f6bcf | 393 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ |
090eb735 MK |
394 | OR_SCY_6_CLK | OR_TRLX) |
395 | ||
6d0f6bcf JCPV |
396 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
397 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
398 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
090eb735 | 399 | |
6d0f6bcf JCPV |
400 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
401 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
402 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
090eb735 MK |
403 | |
404 | /* | |
405 | * BR2/3 and OR2/3 (SDRAM) | |
406 | * | |
407 | */ | |
408 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
409 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
410 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ | |
411 | ||
412 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 413 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
090eb735 | 414 | |
6d0f6bcf JCPV |
415 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
416 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
090eb735 MK |
417 | |
418 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf JCPV |
419 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
420 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
090eb735 | 421 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
6d0f6bcf JCPV |
422 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
423 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
424 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
425 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
090eb735 MK |
426 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
427 | #endif /* CONFIG_CAN_DRIVER */ | |
428 | ||
429 | /* | |
430 | * 4096 Rows from SDRAM example configuration | |
431 | * 1000 factor s -> ms | |
432 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
433 | * 4 Number of refresh cycles per period | |
434 | * 64 Refresh cycle in ms per number of rows | |
435 | */ | |
6d0f6bcf | 436 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) |
090eb735 MK |
437 | |
438 | /* | |
492c7049 JG |
439 | * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) |
440 | * | |
441 | * CPUclock(MHz) * 31.2 | |
6d0f6bcf | 442 | * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 |
492c7049 JG |
443 | * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 |
444 | * | |
6d0f6bcf JCPV |
445 | * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us |
446 | * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us | |
447 | * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us | |
448 | * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us | |
492c7049 JG |
449 | * |
450 | * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will | |
451 | * be met also in the default configuration, i.e. if environment variable | |
452 | * 'cpuclk' is not set. | |
090eb735 | 453 | */ |
6d0f6bcf | 454 | #define CONFIG_SYS_MAMR_PTA 128 |
090eb735 MK |
455 | |
456 | /* | |
492c7049 | 457 | * Memory Periodic Timer Prescaler Register (MPTPR) values. |
090eb735 | 458 | */ |
492c7049 | 459 | /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ |
6d0f6bcf | 460 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 |
492c7049 | 461 | /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ |
6d0f6bcf | 462 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 |
090eb735 MK |
463 | |
464 | /* | |
465 | * MAMR settings for SDRAM | |
466 | */ | |
467 | ||
468 | /* 8 column SDRAM */ | |
6d0f6bcf | 469 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
090eb735 MK |
470 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
471 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
472 | /* 9 column SDRAM */ | |
6d0f6bcf | 473 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
090eb735 MK |
474 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
475 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
476 | /* 10 column SDRAM */ | |
6d0f6bcf | 477 | #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
090eb735 MK |
478 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ |
479 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
480 | ||
090eb735 MK |
481 | /* |
482 | * Network configuration | |
483 | */ | |
484 | #define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ | |
485 | #define CONFIG_FEC_ENET /* enable ethernet on FEC */ | |
486 | #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ | |
487 | #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ | |
488 | ||
2694690e | 489 | #if defined(CONFIG_CMD_MII) |
6d0f6bcf | 490 | #define CONFIG_SYS_DISCOVER_PHY |
0f3ba7e9 | 491 | #define CONFIG_MII_INIT 1 |
090eb735 MK |
492 | #endif |
493 | ||
494 | #define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before | |
495 | switching to another netwok (if the | |
496 | tried network is unreachable) */ | |
497 | ||
48690d80 | 498 | #define CONFIG_ETHPRIME "SCC" |
090eb735 | 499 | |
7026ead0 HS |
500 | /* pass open firmware flat tree */ |
501 | #define CONFIG_OF_LIBFDT 1 | |
502 | #define CONFIG_OF_BOARD_SETUP 1 | |
503 | #define CONFIG_HWCONFIG 1 | |
504 | ||
090eb735 | 505 | #endif /* __CONFIG_H */ |