[people/ms/u-boot.git] / include / configs / TQM885D.h

/*
 * (C) Copyright 2000-2014
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2006
 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC885		1	/* This is a MPC885 CPU		*/
#define CONFIG_TQM885D		1	/* ...on a TQM88D module	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
#define CONFIG_SYS_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
#define CONFIG_8xx_CPUCLK_DEFAULT	66000000	/*  66 MHz - CPU default clock	*/
						/* (it will be used if there is no	*/
						/* 'cpuclk' variable with valid value)	*/

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#define CONFIG_SYS_SMC_RXBUFLEN	128
#define CONFIG_SYS_MAXIDLE	10
#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#define CONFIG_BOOTCOUNT_LIMIT


#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_8xx\0"					\
	"bootfile=/tftpboot/TQM885D/uImage\0"				\
	"fdt_addr=400C0000\0"						\
	"kernel_addr=40100000\0"					\
	"ramdisk_addr=40280000\0"					\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=protect off 40000000 +${filesize};"			\
		"erase 40000000 +${filesize};"				\
		"cp.b 200000 40000000 ${filesize};"			\
		"protect on 40000000 +${filesize}\0"			\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/* enable I2C and select the hardware/software driver */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C??	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

# define CONFIG_RTC_DS1337 1
# define CONFIG_SYS_I2C_RTC_ADDR 0x68

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_DOS_PARTITION

#undef CONFIG_RTC_MPC8xx		/* MPC885 does not support RTC	*/

#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/

/*
 * Command line configuration.
 */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IDE

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0300000	/* 1 ... 3 MB in DRAM	*/
#define CONFIG_SYS_ALT_MEMTEST				/* alternate, more extensive
						   memory test.*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */

/* use CFI flash driver */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x08000 /* Total Size of Environment		*/
#define CONFIG_ENV_SECT_SIZE	0x40000 /* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef CONFIG_CAN_DRIVER
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing: Default value of OR0 after reset
 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
				 OR_SCY_6_CLK | OR_TRLX)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef CONFIG_CAN_DRIVER
#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * 4096	Rows from SDRAM example configuration
 * 1000	factor s -> ms
 * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
 * 4	Number of refresh cycles per period
 * 64	Refresh cycle in ms per number of rows
 */
#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))

/*
 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
 *
 *                        CPUclock(MHz) * 31.2
 * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
 *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
 *
 * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
 * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
 * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
 * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
 *
 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
 * be met also in the default configuration, i.e. if environment variable
 * 'cpuclk' is not set.
 */
#define CONFIG_SYS_MAMR_PTA		128

/*
 * Memory Periodic Timer Prescaler Register (MPTPR) values.
 */
/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16
/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 10 column SDRAM */
#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/*
 * Network configuration
 */
#define CONFIG_SCC2_ENET		/* enable ethernet on SCC2 */
#define CONFIG_FEC_ENET			/* enable ethernet on FEC */
#define CONFIG_ETHER_ON_FEC1		/* ... for FEC1 */
#define CONFIG_ETHER_ON_FEC2		/* ... for FEC2 */

#if defined(CONFIG_CMD_MII)
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_MII_INIT	1
#endif

#define CONFIG_NET_RETRY_COUNT 1	/* reduce max. timeout before
					   switching to another netwok (if the
					   tried network is unreachable) */

#define CONFIG_ETHPRIME		"SCC"

#define CONFIG_HWCONFIG		1

#endif	/* __CONFIG_H */
Commit	Line	Data
090eb735	1	/*
23c5d253	2	* (C) Copyright 2000-2014
090eb735 MK	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2006
	6	* Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
090eb735 MK	9	*/
	10
	11	/*
	12	* board/config.h - configuration options, board specific
	13	*/
	14
	15	#ifndef __CONFIG_H
	16	#define __CONFIG_H
	17
	18	/*
	19	* High Level Configuration Options
	20	* (easy to change)
	21	*/
	22
	23	#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
	24	#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
	25
2ae18241 WD	26	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	27
090eb735	28	#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
6d0f6bcf JCPV	29	#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
6d0f6bcf JCPV	30	#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
22d1a56c	31	#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
090eb735 MK	32	/* (it will be used if there is no */
	33	/* 'cpuclk' variable with valid value) */
	34
090eb735	35	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
3cb7a480 WD	36	#define CONFIG_SYS_SMC_RXBUFLEN 128
3cb7a480 WD	37	#define CONFIG_SYS_MAXIDLE 10
090eb735 MK	38	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	39
	40	#define CONFIG_BOOTCOUNT_LIMIT
	41
090eb735 MK	42
	43	#define CONFIG_BOARD_TYPES 1 /* support board types */
	44
	45	#define CONFIG_PREBOOT "echo;" \
32bf3d14	46	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
090eb735 MK	47	"echo"
	48
	49	#undef CONFIG_BOOTARGS
	50
	51	#define CONFIG_EXTRA_ENV_SETTINGS \
	52	"netdev=eth0\0" \
	53	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	54	"nfsroot=${serverip}:${rootpath}\0" \
	55	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	56	"addip=setenv bootargs ${bootargs} " \
	57	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	58	":${hostname}:${netdev}:off panic=1\0" \
	59	"flash_nfs=run nfsargs addip;" \
	60	"bootm ${kernel_addr}\0" \
	61	"flash_self=run ramargs addip;" \
	62	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	63	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
	64	"rootpath=/opt/eldk/ppc_8xx\0" \
11d9eec4 MK	65	"bootfile=/tftpboot/TQM885D/uImage\0" \
	66	"fdt_addr=400C0000\0" \
	67	"kernel_addr=40100000\0" \
	68	"ramdisk_addr=40280000\0" \
	69	"load=tftp 200000 ${u-boot}\0" \
	70	"update=protect off 40000000 +${filesize};" \
	71	"erase 40000000 +${filesize};" \
	72	"cp.b 200000 40000000 ${filesize};" \
	73	"protect on 40000000 +${filesize}\0" \
090eb735 MK	74	""
	75	#define CONFIG_BOOTCOMMAND "run flash_self"
	76
	77	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	78	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
090eb735 MK	79
	80	#undef CONFIG_WATCHDOG /* watchdog disabled */
	81
090eb735 MK	82	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	83
	84	/* enable I2C and select the hardware/software driver */
ea818dbb HS	85	#define CONFIG_SYS_I2C
	86	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	87	#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
	88	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
090eb735 MK	89	/*
	90	* Software (bit-bang) I2C driver configuration
	91	*/
	92	#define PB_SCL 0x00000020 /* PB 26 */
	93	#define PB_SDA 0x00000010 /* PB 27 */
	94
	95	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	96	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	97	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	98	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	99	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	100	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	101	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	102	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	103	#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
090eb735	104
6d0f6bcf JCPV	105	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
	106	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
	107	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	108	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
090eb735 MK	109
090eb735 MK	110	# define CONFIG_RTC_DS1337 1
6d0f6bcf	111	# define CONFIG_SYS_I2C_RTC_ADDR 0x68
090eb735	112
37d4bb70 JL	113	/*
	114	* BOOTP options
	115	*/
	116	#define CONFIG_BOOTP_SUBNETMASK
	117	#define CONFIG_BOOTP_GATEWAY
	118	#define CONFIG_BOOTP_HOSTNAME
	119	#define CONFIG_BOOTP_BOOTPATH
	120	#define CONFIG_BOOTP_BOOTFILESIZE
	121
090eb735 MK	122	#define CONFIG_DOS_PARTITION
090eb735 MK	123
11d9eec4	124	#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
090eb735 MK	125
	126	#define CONFIG_TIMESTAMP /* but print image timestmps */
	127
2694690e JL	128	/*
	129	* Command line configuration.
	130	*/
2694690e	131	#define CONFIG_CMD_DATE
2694690e	132	#define CONFIG_CMD_EEPROM
2694690e	133	#define CONFIG_CMD_IDE
090eb735 MK	134
	135	/*
	136	* Miscellaneous configurable options
	137	*/
6d0f6bcf	138	#define CONFIG_SYS_LONGHELP /* undef to save memory */
090eb735	139
2751a95a	140	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
090eb735	141
2694690e	142	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	143	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
090eb735	144	#else
6d0f6bcf	145	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
090eb735	146	#endif
6d0f6bcf JCPV	147	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	148	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	149	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
090eb735	150
6d0f6bcf JCPV	151	#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
	152	#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
	153	#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
090eb735 MK	154	memory test.*/
090eb735 MK	155
6d0f6bcf	156	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
090eb735	157
090eb735 MK	158	/*
	159	* Low Level Configuration Settings
	160	* (address mappings, register initial values, etc.)
	161	* You should know what you are doing if you make changes here.
	162	*/
	163	/*-----------------------------------------------------------------------
	164	* Internal Memory Mapped Register
	165	*/
6d0f6bcf	166	#define CONFIG_SYS_IMMR 0xFFF00000
090eb735 MK	167
	168	/*-----------------------------------------------------------------------
	169	* Definitions for initial stack pointer and data area (in DPRAM)
	170	*/
6d0f6bcf	171	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	172	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	173	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	174	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
090eb735 MK	175
	176	/*-----------------------------------------------------------------------
	177	* Start addresses for the final memory configuration
	178	* (Set up by the startup code)
6d0f6bcf	179	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
090eb735	180	*/
6d0f6bcf JCPV	181	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	182	#define CONFIG_SYS_FLASH_BASE 0x40000000
	183	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	184	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	185	#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
090eb735 MK	186
	187	/*
	188	* For booting Linux, the board info and command line data
	189	* have to be in the first 8 MB of memory, since this is
	190	* the maximum mapped by the Linux kernel during initialization.
	191	*/
6d0f6bcf	192	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
090eb735 MK	193
	194	/*-----------------------------------------------------------------------
	195	* FLASH organization
	196	*/
090eb735	197
e318d9e9	198	/* use CFI flash driver */
6d0f6bcf	199	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	200	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	201	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	202	#define CONFIG_SYS_FLASH_EMPTY_INFO
	203	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	204	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	205	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
090eb735	206
5a1aceb0	207	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	208	#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
	209	#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
	210	#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
090eb735 MK	211
090eb735 MK	212	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	213	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	214	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
090eb735 MK	215
	216	/*-----------------------------------------------------------------------
	217	* Hardware Information Block
	218	*/
6d0f6bcf JCPV	219	#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
	220	#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
	221	#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
090eb735 MK	222
	223	/*-----------------------------------------------------------------------
	224	* Cache Configuration
	225	*/
6d0f6bcf	226	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
2694690e	227	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	228	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
090eb735 MK	229	#endif
	230
	231	/*-----------------------------------------------------------------------
	232	* SYPCR - System Protection Control 11-9
	233	* SYPCR can only be written once after reset!
	234	*-----------------------------------------------------------------------
	235	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	236	*/
	237	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	238	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
090eb735 MK	239	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
090eb735 MK	240	#else
6d0f6bcf	241	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
090eb735 MK	242	#endif
	243
	244	/*-----------------------------------------------------------------------
	245	* SIUMCR - SIU Module Configuration 11-6
	246	*-----------------------------------------------------------------------
	247	* PCMCIA config., multi-function pin tri-state
	248	*/
	249	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf	250	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
090eb735	251	#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf	252	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
090eb735 MK	253	#endif /* CONFIG_CAN_DRIVER */
	254
	255	/*-----------------------------------------------------------------------
	256	* TBSCR - Time Base Status and Control 11-26
	257	*-----------------------------------------------------------------------
	258	* Clear Reference Interrupt Status, Timebase freezing enabled
	259	*/
6d0f6bcf	260	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
090eb735 MK	261
	262	/*-----------------------------------------------------------------------
	263	* PISCR - Periodic Interrupt Status and Control 11-31
	264	*-----------------------------------------------------------------------
	265	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	266	*/
6d0f6bcf	267	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
090eb735 MK	268
	269	/*-----------------------------------------------------------------------
	270	* SCCR - System Clock and reset Control Register 15-27
	271	*-----------------------------------------------------------------------
	272	* Set clock output, timebase and RTC source and divider,
	273	* power management and some other internal clocks
	274	*/
	275	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	276	#define CONFIG_SYS_SCCR (SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
090eb735 MK	277	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	278	SCCR_DFALCD00)
	279
	280	/*-----------------------------------------------------------------------
	281	* PCMCIA stuff
	282	*-----------------------------------------------------------------------
	283	*
	284	*/
6d0f6bcf JCPV	285	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	286	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	287	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	288	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	289	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	290	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	291	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	292	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
090eb735 MK	293
	294	/*-----------------------------------------------------------------------
	295	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	296	*-----------------------------------------------------------------------
	297	*/
	298
8d1165e1	299	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
090eb735 MK	300	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	301
	302	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	303	#undef CONFIG_IDE_LED /* LED for ide not supported */
	304	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	305
6d0f6bcf JCPV	306	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	307	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
090eb735	308
6d0f6bcf	309	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
090eb735	310
6d0f6bcf	311	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
090eb735 MK	312
090eb735 MK	313	/* Offset for data I/O */
6d0f6bcf	314	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
090eb735 MK	315
090eb735 MK	316	/* Offset for normal register accesses */
6d0f6bcf	317	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
090eb735 MK	318
090eb735 MK	319	/* Offset for alternate registers */
6d0f6bcf	320	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
090eb735 MK	321
	322	/*-----------------------------------------------------------------------
	323	*
	324	*-----------------------------------------------------------------------
	325	*
	326	*/
6d0f6bcf	327	#define CONFIG_SYS_DER 0
090eb735 MK	328
	329	/*
	330	* Init Memory Controller:
	331	*
	332	* BR0/1 and OR0/1 (FLASH)
	333	*/
	334
	335	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	336	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	337
	338	/* used to re-map FLASH both when starting from SRAM or FLASH:
	339	* restrict access enough to keep SRAM working (if any)
	340	* but not too much to meddle with FLASH accesses
	341	*/
6d0f6bcf JCPV	342	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	343	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
090eb735 MK	344
	345	/*
	346	* FLASH timing: Default value of OR0 after reset
	347	*/
6d0f6bcf	348	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_MSK \| OR_BI \| \
090eb735 MK	349	OR_SCY_6_CLK \| OR_TRLX)
090eb735 MK	350
6d0f6bcf JCPV	351	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	352	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	353	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
090eb735	354
6d0f6bcf JCPV	355	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
	356	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	357	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
090eb735 MK	358
	359	/*
	360	* BR2/3 and OR2/3 (SDRAM)
	361	*
	362	*/
	363	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	364	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
	365	#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
	366
	367	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	368	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
090eb735	369
6d0f6bcf JCPV	370	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	371	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
090eb735 MK	372
090eb735 MK	373	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf JCPV	374	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
6d0f6bcf JCPV	375	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
090eb735	376	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
6d0f6bcf JCPV	377	#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
	378	#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	379	#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM \| OR_G5LA \| OR_BI)
	380	#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) \| \
090eb735 MK	381	BR_PS_8 \| BR_MS_UPMB \| BR_V )
	382	#endif /* CONFIG_CAN_DRIVER */
	383
	384	/*
	385	* 4096 Rows from SDRAM example configuration
	386	* 1000 factor s -> ms
	387	* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
	388	* 4 Number of refresh cycles per period
	389	* 64 Refresh cycle in ms per number of rows
	390	*/
6d0f6bcf	391	#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
090eb735 MK	392
090eb735 MK	393	/*
492c7049 JG	394	* Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
	395	*
	396	* CPUclock(MHz) * 31.2
6d0f6bcf	397	* CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
492c7049 JG	398	* 2^(2SCCR[DFBRG]) MPTPR_PTP_DIV16
492c7049 JG	399	*
6d0f6bcf JCPV	400	* CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
	401	* CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
	402	* CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
	403	* CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
492c7049 JG	404	*
	405	* Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
	406	* be met also in the default configuration, i.e. if environment variable
	407	* 'cpuclk' is not set.
090eb735	408	*/
6d0f6bcf	409	#define CONFIG_SYS_MAMR_PTA 128
090eb735 MK	410
090eb735 MK	411	/*
492c7049	412	* Memory Periodic Timer Prescaler Register (MPTPR) values.
090eb735	413	*/
492c7049	414	/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
6d0f6bcf	415	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
492c7049	416	/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
6d0f6bcf	417	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
090eb735 MK	418
	419	/*
	420	* MAMR settings for SDRAM
	421	*/
	422
	423	/* 8 column SDRAM */
6d0f6bcf	424	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
090eb735 MK	425	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	426	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	427	/* 9 column SDRAM */
6d0f6bcf	428	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
090eb735 MK	429	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	430	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	431	/* 10 column SDRAM */
6d0f6bcf	432	#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
090eb735 MK	433	MAMR_AMA_TYPE_2 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A9 \| \
	434	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	435
090eb735 MK	436	/*
	437	* Network configuration
	438	*/
	439	#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
	440	#define CONFIG_FEC_ENET /* enable ethernet on FEC */
	441	#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
	442	#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
	443
2694690e	444	#if defined(CONFIG_CMD_MII)
6d0f6bcf	445	#define CONFIG_SYS_DISCOVER_PHY
0f3ba7e9	446	#define CONFIG_MII_INIT 1
090eb735 MK	447	#endif
	448
	449	#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
	450	switching to another netwok (if the
	451	tried network is unreachable) */
	452
48690d80	453	#define CONFIG_ETHPRIME "SCC"
090eb735	454
7026ead0 HS	455	#define CONFIG_HWCONFIG 1
7026ead0 HS	456
090eb735	457	#endif /* __CONFIG_H */