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6c7a1408 WD |
1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* | |
31 | * Check valid setting of revision define. | |
32 | * Total5100 and Total5200 Rev.1 are identical except for the processor. | |
33 | */ | |
34 | #if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2) | |
35 | #error CONFIG_TOTAL5200_REV must be 1 or 2 | |
36 | #endif | |
37 | ||
38 | /* | |
39 | * High Level Configuration Options | |
40 | * (easy to change) | |
41 | */ | |
42 | ||
43 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
fd428c05 | 44 | #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ |
6c7a1408 WD |
45 | #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ |
46 | ||
2ae18241 WD |
47 | /* |
48 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
49 | * 0xFFF00000 boot high (standard configuration) | |
50 | * 0xFE000000 boot low | |
51 | * 0x00100000 boot from RAM (for testing only) | |
52 | */ | |
53 | #ifndef CONFIG_SYS_TEXT_BASE | |
54 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
55 | #endif | |
56 | ||
6d0f6bcf | 57 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
6c7a1408 | 58 | |
31d82672 BB |
59 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
60 | ||
6c7a1408 WD |
61 | /* |
62 | * Serial console configuration | |
63 | */ | |
64 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ | |
65 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 66 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
6c7a1408 | 67 | |
81050926 WD |
68 | /* |
69 | * Video console | |
70 | */ | |
281e00a3 | 71 | #define CONFIG_VIDEO |
81050926 WD |
72 | #define CONFIG_VIDEO_SED13806 |
73 | #define CONFIG_VIDEO_SED13806_16BPP | |
74 | ||
75 | #define CONFIG_CFB_CONSOLE | |
76 | #define CONFIG_VIDEO_LOGO | |
77 | /* #define CONFIG_VIDEO_BMP_LOGO */ | |
78 | #define CONFIG_CONSOLE_EXTRA_INFO | |
79 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
80 | #define CONFIG_VIDEO_SW_CURSOR | |
81 | #define CONFIG_SPLASH_SCREEN | |
82 | ||
6c7a1408 | 83 | |
6c7a1408 WD |
84 | /* |
85 | * PCI Mapping: | |
86 | * 0x40000000 - 0x4fffffff - PCI Memory | |
87 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
88 | */ | |
89 | #define CONFIG_PCI 1 | |
90 | #define CONFIG_PCI_PNP 1 | |
91 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 92 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
6c7a1408 WD |
93 | |
94 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
95 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
96 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
97 | ||
98 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
99 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
100 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
101 | ||
63ff004c | 102 | #define CONFIG_MII 1 |
6c7a1408 | 103 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 104 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
6c7a1408 WD |
105 | #define CONFIG_NS8382X 1 |
106 | ||
6c7a1408 WD |
107 | /* Partitions */ |
108 | #define CONFIG_MAC_PARTITION | |
109 | #define CONFIG_DOS_PARTITION | |
110 | ||
111 | /* USB */ | |
6c7a1408 | 112 | #define CONFIG_USB_OHCI |
6c7a1408 | 113 | #define CONFIG_USB_STORAGE |
d794cfef | 114 | |
6c7a1408 | 115 | |
a1aa0bb5 JL |
116 | /* |
117 | * BOOTP options | |
118 | */ | |
119 | #define CONFIG_BOOTP_BOOTFILESIZE | |
120 | #define CONFIG_BOOTP_BOOTPATH | |
121 | #define CONFIG_BOOTP_GATEWAY | |
122 | #define CONFIG_BOOTP_HOSTNAME | |
123 | ||
124 | ||
6c7a1408 | 125 | /* |
d794cfef | 126 | * Command line configuration. |
6c7a1408 | 127 | */ |
d794cfef JL |
128 | #include <config_cmd_default.h> |
129 | ||
fd428c05 | 130 | #define CONFIG_CMD_PCI |
d794cfef JL |
131 | |
132 | #define CONFIG_CMD_BMP | |
133 | #define CONFIG_CMD_EEPROM | |
134 | #define CONFIG_CMD_FAT | |
135 | #define CONFIG_CMD_I2C | |
136 | #define CONFIG_CMD_IDE | |
137 | #define CONFIG_CMD_PING | |
138 | #define CONFIG_CMD_USB | |
139 | ||
6c7a1408 | 140 | |
14d0a02a | 141 | #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */ |
6d0f6bcf | 142 | # define CONFIG_SYS_LOWBOOT 1 |
6c7a1408 WD |
143 | #endif |
144 | ||
145 | /* | |
146 | * Autobooting | |
147 | */ | |
148 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
149 | ||
81050926 WD |
150 | #define CONFIG_PREBOOT \ |
151 | "setenv stdout serial;setenv stderr serial;" \ | |
152 | "echo;" \ | |
32bf3d14 | 153 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
6c7a1408 WD |
154 | "echo" |
155 | ||
156 | #undef CONFIG_BOOTARGS | |
157 | ||
158 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
159 | "netdev=eth0\0" \ | |
160 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 161 | "nfsroot=${serverip}:${rootpath}\0" \ |
6c7a1408 | 162 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
163 | "addip=setenv bootargs ${bootargs} " \ |
164 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
165 | ":${hostname}:${netdev}:off panic=1\0" \ | |
6c7a1408 | 166 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 167 | "bootm ${kernel_addr}\0" \ |
6c7a1408 | 168 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
169 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
170 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
6c7a1408 WD |
171 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
172 | "bootfile=/tftpboot/MPC5200/uImage\0" \ | |
173 | "" | |
174 | ||
175 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
176 | ||
6c7a1408 WD |
177 | /* |
178 | * IPB Bus clocking configuration. | |
179 | */ | |
6d0f6bcf | 180 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
6c7a1408 WD |
181 | |
182 | /* | |
183 | * I2C configuration | |
184 | */ | |
185 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 186 | #define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ |
6c7a1408 | 187 | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
189 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
6c7a1408 WD |
190 | |
191 | /* | |
192 | * EEPROM configuration | |
193 | */ | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
195 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
196 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
197 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
6c7a1408 WD |
198 | |
199 | /* | |
200 | * Flash configuration | |
201 | */ | |
6d0f6bcf | 202 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 203 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6c7a1408 | 204 | #if CONFIG_TOTAL5200_REV==2 |
6d0f6bcf JCPV |
205 | # define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ |
206 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START } | |
6c7a1408 | 207 | #else |
6d0f6bcf JCPV |
208 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
209 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } | |
6c7a1408 | 210 | #endif |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
212 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
6c7a1408 WD |
213 | |
214 | #if CONFIG_TOTAL5200_REV==1 | |
6d0f6bcf JCPV |
215 | # define CONFIG_SYS_FLASH_BASE 0xFE000000 |
216 | # define CONFIG_SYS_FLASH_SIZE 0x02000000 | |
6c7a1408 | 217 | #elif CONFIG_TOTAL5200_REV==2 |
6d0f6bcf JCPV |
218 | # define CONFIG_SYS_FLASH_BASE 0xFA000000 |
219 | # define CONFIG_SYS_FLASH_SIZE 0x06000000 | |
6c7a1408 WD |
220 | #endif /* CONFIG_TOTAL5200_REV */ |
221 | ||
6d0f6bcf | 222 | #if defined(CONFIG_SYS_LOWBOOT) |
0e8d1586 | 223 | # define CONFIG_ENV_ADDR 0xFE040000 |
6d0f6bcf | 224 | #else /* CONFIG_SYS_LOWBOOT */ |
0e8d1586 | 225 | # define CONFIG_ENV_ADDR 0xFFF40000 |
6d0f6bcf | 226 | #endif /* CONFIG_SYS_LOWBOOT */ |
6c7a1408 WD |
227 | |
228 | /* | |
229 | * Environment settings | |
230 | */ | |
5a1aceb0 | 231 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
232 | #define CONFIG_ENV_SIZE 0x40000 |
233 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
6c7a1408 WD |
234 | #define CONFIG_ENV_OVERWRITE 1 |
235 | ||
236 | /* | |
237 | * Memory map | |
238 | */ | |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
240 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
241 | #define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */ | |
242 | #define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */ | |
243 | #define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */ | |
244 | #define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */ | |
6c7a1408 WD |
245 | |
246 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 247 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 248 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
6c7a1408 | 249 | |
25ddd1fb | 250 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 251 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
6c7a1408 | 252 | |
14d0a02a | 253 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
254 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
255 | # define CONFIG_SYS_RAMBOOT 1 | |
6c7a1408 WD |
256 | #endif |
257 | ||
6d0f6bcf JCPV |
258 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
259 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
260 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
6c7a1408 WD |
261 | |
262 | /* | |
263 | * Ethernet configuration | |
264 | */ | |
265 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 266 | #define CONFIG_MPC5xxx_FEC_SEVENWIRE |
6c7a1408 WD |
267 | /* dummy, 7-wire FEC does not have phy address */ |
268 | #define CONFIG_PHY_ADDR 0x00 | |
269 | ||
270 | /* | |
271 | * GPIO configuration | |
272 | * | |
273 | * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0 | |
274 | * Reserved 0 | |
275 | * ALTs: CAN1/2 on PSC2, SPI on PSC3 00 | |
276 | * CS7: Interrupt GPIO on PSC3_5 0 | |
277 | * CS8: Interrupt GPIO on PSC3_4 0 | |
278 | * ATA: reset default, changed in ATA driver 00 | |
279 | * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0 | |
280 | * IRDA: reset default, changed in IrDA driver 000 | |
281 | * ETHER: reset default, changed in Ethernet driver 0000 | |
282 | * PCI_DIS: reset default, changed in PCI driver 0 | |
283 | * USB_SE: reset default, changed in USB driver 0 | |
284 | * USB: reset default, changed in USB driver 00 | |
285 | * PSC3: SPI and UART functionality without CD 1100 | |
286 | * Reserved 0 | |
287 | * PSC2: CAN1/2 001 | |
288 | * Reserved 0 | |
289 | * PSC1: reset default, changed in AC'97 driver 000 | |
290 | * | |
291 | */ | |
6d0f6bcf | 292 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10 |
6c7a1408 WD |
293 | |
294 | /* | |
295 | * Miscellaneous configurable options | |
296 | */ | |
6d0f6bcf JCPV |
297 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
298 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
d794cfef | 299 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 300 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
6c7a1408 | 301 | #else |
6d0f6bcf | 302 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
6c7a1408 | 303 | #endif |
6d0f6bcf JCPV |
304 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
305 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
306 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
6c7a1408 | 307 | |
6d0f6bcf JCPV |
308 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
309 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
6c7a1408 | 310 | |
6d0f6bcf | 311 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
6c7a1408 | 312 | |
6d0f6bcf | 313 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
6c7a1408 | 314 | |
6d0f6bcf | 315 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
d794cfef | 316 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 317 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
d794cfef JL |
318 | #endif |
319 | ||
320 | ||
6c7a1408 WD |
321 | /* |
322 | * Various low-level settings | |
323 | */ | |
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
325 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
6c7a1408 WD |
326 | |
327 | #if CONFIG_TOTAL5200_REV==1 | |
6d0f6bcf JCPV |
328 | # define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
329 | # define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ | |
330 | # define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ | |
331 | # define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
332 | # define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */ | |
6c7a1408 | 333 | #else |
6d0f6bcf JCPV |
334 | # define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE) |
335 | # define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ | |
336 | # define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ | |
337 | # define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE) | |
338 | # define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */ | |
339 | # define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ | |
340 | # define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE | |
341 | # define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */ | |
342 | # define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ | |
6c7a1408 WD |
343 | #endif |
344 | ||
6d0f6bcf JCPV |
345 | #define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE |
346 | #define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */ | |
347 | #define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */ | |
6c7a1408 | 348 | |
6d0f6bcf JCPV |
349 | #define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE |
350 | #define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */ | |
351 | #define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */ | |
6c7a1408 WD |
352 | |
353 | #if CONFIG_TOTAL5200_REV==1 | |
6d0f6bcf JCPV |
354 | # define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE |
355 | # define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ | |
356 | # define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */ | |
6c7a1408 | 357 | #else |
6d0f6bcf JCPV |
358 | # define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE |
359 | # define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ | |
360 | # define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */ | |
6c7a1408 WD |
361 | #endif |
362 | ||
6d0f6bcf JCPV |
363 | #define CONFIG_SYS_CS_BURST 0x00000000 |
364 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
6c7a1408 WD |
365 | |
366 | /*----------------------------------------------------------------------- | |
367 | * USB stuff | |
368 | *----------------------------------------------------------------------- | |
369 | */ | |
370 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
371 | #define CONFIG_USB_CONFIG 0x00001000 | |
372 | ||
373 | /*----------------------------------------------------------------------- | |
374 | * IDE/ATA stuff Supports IDE harddisk | |
375 | *----------------------------------------------------------------------- | |
376 | */ | |
377 | ||
378 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
379 | ||
380 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
381 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
382 | ||
383 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
384 | #define CONFIG_IDE_PREINIT | |
385 | ||
6a397ef0 | 386 | #define CONFIG_SYS_ATA_CS_ON_I2C2 |
6d0f6bcf JCPV |
387 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
388 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
6c7a1408 | 389 | |
6d0f6bcf | 390 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
6c7a1408 | 391 | |
6d0f6bcf | 392 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
6c7a1408 WD |
393 | |
394 | /* Offset for data I/O */ | |
6d0f6bcf | 395 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
6c7a1408 WD |
396 | |
397 | /* Offset for normal register accesses */ | |
6d0f6bcf | 398 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
6c7a1408 WD |
399 | |
400 | /* Offset for alternate registers */ | |
6d0f6bcf | 401 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
6c7a1408 WD |
402 | |
403 | /* Interval between registers */ | |
6d0f6bcf | 404 | #define CONFIG_SYS_ATA_STRIDE 4 |
6c7a1408 WD |
405 | |
406 | #endif /* __CONFIG_H */ |