[people/ms/u-boot.git] / include / configs / Total5200.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Check valid setting of revision define.
 * Total5100 and Total5200 Rev.1 are identical except for the processor.
 */
#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
#error CONFIG_TOTAL5200_REV must be 1 or 2
#endif

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU) */
#define CONFIG_TOTAL5200	1	/* ... on Total5200 board */

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Video console
 */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SED13806
#define CONFIG_VIDEO_SED13806_16BPP

#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
/* #define CONFIG_VIDEO_BMP_LOGO */
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN


/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1
#define CONFIG_EEPRO100		1
#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI

#define CONFIG_CMD_BMP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB


#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low */
#   define CONFIG_SYS_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	\
	"setenv stdout serial;setenv stderr serial;" \
	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#if CONFIG_TOTAL5200_REV==2
#   define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max num of flash banks */
#   define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
#else
#   define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks  */
#   define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
#endif
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#if CONFIG_TOTAL5200_REV==1
#   define CONFIG_SYS_FLASH_BASE	0xFE000000
#   define CONFIG_SYS_FLASH_SIZE	0x02000000
#elif CONFIG_TOTAL5200_REV==2
#   define CONFIG_SYS_FLASH_BASE	0xFA000000
#   define CONFIG_SYS_FLASH_SIZE	0x06000000
#endif /* CONFIG_TOTAL5200_REV */

#if defined(CONFIG_SYS_LOWBOOT)
#   define CONFIG_ENV_ADDR		0xFE040000
#else	/* CONFIG_SYS_LOWBOOT */
#   define CONFIG_ENV_ADDR		0xFFF40000
#endif	/* CONFIG_SYS_LOWBOOT */

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x40000
#define CONFIG_ENV_SECT_SIZE	0x40000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
#define CONFIG_SYS_MBAR		0xF0000000	/*   64 kB */
#define CONFIG_SYS_FPGA_BASE		0xF0010000	/*   64 kB */
#define CONFIG_SYS_CPLD_BASE		0xF0020000	/*   64 kB */
#define CONFIG_SYS_LCD_BASE		0xF1000000	/* 4096 kB */

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_SEVENWIRE
/* dummy, 7-wire FEC does not have phy address */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 *
 * CS1:   SDRAM CS1 disabled, gpio_wkup_6 enabled                0
 * Reserved                                                      0
 * ALTs:  CAN1/2 on PSC2, SPI on PSC3                            00
 * CS7:   Interrupt GPIO on PSC3_5                               0
 * CS8:   Interrupt GPIO on PSC3_4                               0
 * ATA:   reset default, changed in ATA driver                   00
 * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO       0
 * IRDA:  reset default, changed in IrDA driver                  000
 * ETHER: reset default, changed in Ethernet driver              0000
 * PCI_DIS: reset default, changed in PCI driver                 0
 * USB_SE: reset default, changed in USB driver                  0
 * USB:   reset default, changed in USB driver                   00
 * PSC3:  SPI and UART functionality without CD                  1100
 * Reserved                                                      0
 * PSC2:  CAN1/2                                                 001
 * Reserved                                                      0
 * PSC1:  reset default, changed in AC'97 driver                 000
 *
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x00000C10

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif


/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#if CONFIG_TOTAL5200_REV==1
#   define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#   define CONFIG_SYS_BOOTCS_SIZE	0x02000000	/* 32 MB */
#   define CONFIG_SYS_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#   define CONFIG_SYS_CS0_START	CONFIG_SYS_FLASH_BASE
#   define CONFIG_SYS_CS0_SIZE		0x02000000	/* 32 MB */
#else
#   define CONFIG_SYS_BOOTCS_START	(CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
#   define CONFIG_SYS_BOOTCS_SIZE	0x02000000	/* 32 MB */
#   define CONFIG_SYS_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#   define CONFIG_SYS_CS4_START	(CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
#   define CONFIG_SYS_CS4_SIZE		0x02000000	/* 32 MB */
#   define CONFIG_SYS_CS4_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#   define CONFIG_SYS_CS5_START	CONFIG_SYS_FLASH_BASE
#   define CONFIG_SYS_CS5_SIZE		0x02000000	/* 32 MB */
#   define CONFIG_SYS_CS5_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#endif

#define CONFIG_SYS_CS1_START		CONFIG_SYS_FPGA_BASE
#define CONFIG_SYS_CS1_SIZE		0x00010000	/* 64 kB */
#define CONFIG_SYS_CS1_CFG		0x0019FF00	/* 25WS, MX, AL, AA, CE, AS_25, DS_32 */

#define CONFIG_SYS_CS2_START		CONFIG_SYS_LCD_BASE
#define CONFIG_SYS_CS2_SIZE		0x00400000	/* 4096 kB */
#define CONFIG_SYS_CS2_CFG		0x0032FD0C	/* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */

#if CONFIG_TOTAL5200_REV==1
#   define CONFIG_SYS_CS3_START	CONFIG_SYS_CPLD_BASE
#   define CONFIG_SYS_CS3_SIZE		0x00010000	/* 64 kB */
#   define CONFIG_SYS_CS3_CFG		0x000ADF00	/* 10WS, MX, AL, CE, AS_25, DS_32 */
#else
#   define CONFIG_SYS_CS3_START	CONFIG_SYS_CPLD_BASE
#   define CONFIG_SYS_CS3_SIZE		0x00010000	/* 64 kB */
#   define CONFIG_SYS_CS3_CFG		0x000AD800	/* 10WS, MX, AL, CE, AS_24, DS_8 */
#endif

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_ATA_CS_ON_I2C2
#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CONFIG_SYS_ATA_STRIDE          4

#endif /* __CONFIG_H */
Commit	Line	Data
6c7a1408 WD	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*
	31	* Check valid setting of revision define.
	32	* Total5100 and Total5200 Rev.1 are identical except for the processor.
	33	*/
	34	#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
	35	#error CONFIG_TOTAL5200_REV must be 1 or 2
	36	#endif
	37
	38	/*
	39	* High Level Configuration Options
	40	* (easy to change)
	41	*/
	42
	43	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
fd428c05	44	#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
6c7a1408 WD	45	#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
6c7a1408 WD	46
6d0f6bcf	47	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
6c7a1408 WD	48
	49	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	50	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	51
31d82672 BB	52	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	53
6c7a1408 WD	54	/*
	55	* Serial console configuration
	56	*/
	57	#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
	58	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	59	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
6c7a1408	60
81050926 WD	61	/*
	62	* Video console
	63	*/
281e00a3	64	#define CONFIG_VIDEO
81050926 WD	65	#define CONFIG_VIDEO_SED13806
	66	#define CONFIG_VIDEO_SED13806_16BPP
	67
	68	#define CONFIG_CFB_CONSOLE
	69	#define CONFIG_VIDEO_LOGO
	70	/* #define CONFIG_VIDEO_BMP_LOGO */
	71	#define CONFIG_CONSOLE_EXTRA_INFO
	72	#define CONFIG_VGA_AS_SINGLE_DEVICE
	73	#define CONFIG_VIDEO_SW_CURSOR
	74	#define CONFIG_SPLASH_SCREEN
	75
6c7a1408	76
6c7a1408 WD	77	/*
	78	* PCI Mapping:
	79	* 0x40000000 - 0x4fffffff - PCI Memory
	80	* 0x50000000 - 0x50ffffff - PCI IO Space
	81	*/
	82	#define CONFIG_PCI 1
	83	#define CONFIG_PCI_PNP 1
	84	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	85	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
6c7a1408 WD	86
	87	#define CONFIG_PCI_MEM_BUS 0x40000000
	88	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	89	#define CONFIG_PCI_MEM_SIZE 0x10000000
	90
	91	#define CONFIG_PCI_IO_BUS 0x50000000
	92	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	93	#define CONFIG_PCI_IO_SIZE 0x01000000
	94
	95	#define CONFIG_NET_MULTI 1
63ff004c	96	#define CONFIG_MII 1
6c7a1408	97	#define CONFIG_EEPRO100 1
6d0f6bcf	98	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
6c7a1408 WD	99	#define CONFIG_NS8382X 1
6c7a1408 WD	100
6c7a1408 WD	101	/* Partitions */
	102	#define CONFIG_MAC_PARTITION
	103	#define CONFIG_DOS_PARTITION
	104
	105	/* USB */
6c7a1408	106	#define CONFIG_USB_OHCI
6c7a1408	107	#define CONFIG_USB_STORAGE
d794cfef	108
6c7a1408	109
a1aa0bb5 JL	110	/*
	111	* BOOTP options
	112	*/
	113	#define CONFIG_BOOTP_BOOTFILESIZE
	114	#define CONFIG_BOOTP_BOOTPATH
	115	#define CONFIG_BOOTP_GATEWAY
	116	#define CONFIG_BOOTP_HOSTNAME
	117
	118
6c7a1408	119	/*
d794cfef	120	* Command line configuration.
6c7a1408	121	*/
d794cfef JL	122	#include <config_cmd_default.h>
d794cfef JL	123
fd428c05	124	#define CONFIG_CMD_PCI
d794cfef JL	125
	126	#define CONFIG_CMD_BMP
	127	#define CONFIG_CMD_EEPROM
	128	#define CONFIG_CMD_FAT
	129	#define CONFIG_CMD_I2C
	130	#define CONFIG_CMD_IDE
	131	#define CONFIG_CMD_PING
	132	#define CONFIG_CMD_USB
	133
6c7a1408	134
14d0a02a	135	#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
6d0f6bcf	136	# define CONFIG_SYS_LOWBOOT 1
6c7a1408 WD	137	#endif
	138
	139	/*
	140	* Autobooting
	141	*/
	142	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	143
81050926 WD	144	#define CONFIG_PREBOOT \
	145	"setenv stdout serial;setenv stderr serial;" \
	146	"echo;" \
32bf3d14	147	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
6c7a1408 WD	148	"echo"
	149
	150	#undef CONFIG_BOOTARGS
	151
	152	#define CONFIG_EXTRA_ENV_SETTINGS \
	153	"netdev=eth0\0" \
	154	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	155	"nfsroot=${serverip}:${rootpath}\0" \
6c7a1408	156	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	157	"addip=setenv bootargs ${bootargs} " \
	158	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	159	":${hostname}:${netdev}:off panic=1\0" \
6c7a1408	160	"flash_nfs=run nfsargs addip;" \
fe126d8b	161	"bootm ${kernel_addr}\0" \
6c7a1408	162	"flash_self=run ramargs addip;" \
fe126d8b WD	163	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	164	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
6c7a1408 WD	165	"rootpath=/opt/eldk/ppc_82xx\0" \
	166	"bootfile=/tftpboot/MPC5200/uImage\0" \
	167	""
	168
	169	#define CONFIG_BOOTCOMMAND "run flash_self"
	170
6c7a1408 WD	171	/*
	172	* IPB Bus clocking configuration.
	173	*/
6d0f6bcf	174	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
6c7a1408 WD	175
	176	/*
	177	* I2C configuration
	178	*/
	179	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	180	#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
6c7a1408	181
6d0f6bcf JCPV	182	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	183	#define CONFIG_SYS_I2C_SLAVE 0x7F
6c7a1408 WD	184
	185	/*
	186	* EEPROM configuration
	187	*/
6d0f6bcf JCPV	188	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	189	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	190	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	191	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
6c7a1408 WD	192
	193	/*
	194	* Flash configuration
	195	*/
6d0f6bcf	196	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	197	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6c7a1408	198	#if CONFIG_TOTAL5200_REV==2
6d0f6bcf JCPV	199	# define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
6d0f6bcf JCPV	200	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
6c7a1408	201	#else
6d0f6bcf JCPV	202	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
6d0f6bcf JCPV	203	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
6c7a1408	204	#endif
6d0f6bcf JCPV	205	#define CONFIG_SYS_FLASH_EMPTY_INFO
6d0f6bcf JCPV	206	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
6c7a1408 WD	207
6c7a1408 WD	208	#if CONFIG_TOTAL5200_REV==1
6d0f6bcf JCPV	209	# define CONFIG_SYS_FLASH_BASE 0xFE000000
6d0f6bcf JCPV	210	# define CONFIG_SYS_FLASH_SIZE 0x02000000
6c7a1408	211	#elif CONFIG_TOTAL5200_REV==2
6d0f6bcf JCPV	212	# define CONFIG_SYS_FLASH_BASE 0xFA000000
6d0f6bcf JCPV	213	# define CONFIG_SYS_FLASH_SIZE 0x06000000
6c7a1408 WD	214	#endif /* CONFIG_TOTAL5200_REV */
6c7a1408 WD	215
6d0f6bcf	216	#if defined(CONFIG_SYS_LOWBOOT)
0e8d1586	217	# define CONFIG_ENV_ADDR 0xFE040000
6d0f6bcf	218	#else /* CONFIG_SYS_LOWBOOT */
0e8d1586	219	# define CONFIG_ENV_ADDR 0xFFF40000
6d0f6bcf	220	#endif /* CONFIG_SYS_LOWBOOT */
6c7a1408 WD	221
	222	/*
	223	* Environment settings
	224	*/
5a1aceb0	225	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	226	#define CONFIG_ENV_SIZE 0x40000
0e8d1586 JCPV	227	#define CONFIG_ENV_SECT_SIZE 0x40000
6c7a1408 WD	228	#define CONFIG_ENV_OVERWRITE 1
	229
	230	/*
	231	* Memory map
	232	*/
6d0f6bcf JCPV	233	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	234	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	235	#define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */
	236	#define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */
	237	#define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */
	238	#define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */
6c7a1408 WD	239
6c7a1408 WD	240	/* Use SRAM until RAM will be available */
6d0f6bcf JCPV	241	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
6d0f6bcf JCPV	242	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
6c7a1408	243
6d0f6bcf JCPV	244	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	245	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	246	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6c7a1408	247
14d0a02a	248	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	249	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	250	# define CONFIG_SYS_RAMBOOT 1
6c7a1408 WD	251	#endif
6c7a1408 WD	252
6d0f6bcf JCPV	253	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	254	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	255	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
6c7a1408 WD	256
	257	/*
	258	* Ethernet configuration
	259	*/
	260	#define CONFIG_MPC5xxx_FEC 1
86321fc1	261	#define CONFIG_MPC5xxx_FEC_SEVENWIRE
6c7a1408 WD	262	/* dummy, 7-wire FEC does not have phy address */
	263	#define CONFIG_PHY_ADDR 0x00
	264
	265	/*
	266	* GPIO configuration
	267	*
	268	* CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0
	269	* Reserved 0
	270	* ALTs: CAN1/2 on PSC2, SPI on PSC3 00
	271	* CS7: Interrupt GPIO on PSC3_5 0
	272	* CS8: Interrupt GPIO on PSC3_4 0
	273	* ATA: reset default, changed in ATA driver 00
	274	* IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0
	275	* IRDA: reset default, changed in IrDA driver 000
	276	* ETHER: reset default, changed in Ethernet driver 0000
	277	* PCI_DIS: reset default, changed in PCI driver 0
	278	* USB_SE: reset default, changed in USB driver 0
	279	* USB: reset default, changed in USB driver 00
	280	* PSC3: SPI and UART functionality without CD 1100
	281	* Reserved 0
	282	* PSC2: CAN1/2 001
	283	* Reserved 0
	284	* PSC1: reset default, changed in AC'97 driver 000
	285	*
	286	*/
6d0f6bcf	287	#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10
6c7a1408 WD	288
	289	/*
	290	* Miscellaneous configurable options
	291	*/
6d0f6bcf JCPV	292	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	293	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
d794cfef	294	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	295	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
6c7a1408	296	#else
6d0f6bcf	297	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
6c7a1408	298	#endif
6d0f6bcf JCPV	299	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	300	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	301	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
6c7a1408	302
6d0f6bcf JCPV	303	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	304	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
6c7a1408	305
6d0f6bcf	306	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6c7a1408	307
6d0f6bcf	308	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
6c7a1408	309
6d0f6bcf	310	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
d794cfef	311	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	312	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
d794cfef JL	313	#endif
	314
	315
6c7a1408 WD	316	/*
	317	* Various low-level settings
	318	*/
6d0f6bcf JCPV	319	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	320	#define CONFIG_SYS_HID0_FINAL HID0_ICE
6c7a1408 WD	321
6c7a1408 WD	322	#if CONFIG_TOTAL5200_REV==1
6d0f6bcf JCPV	323	# define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	324	# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
	325	# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
	326	# define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	327	# define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */
6c7a1408	328	#else
6d0f6bcf JCPV	329	# define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
	330	# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
	331	# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
	332	# define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
	333	# define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */
	334	# define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
	335	# define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE
	336	# define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */
	337	# define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
6c7a1408 WD	338	#endif
6c7a1408 WD	339
6d0f6bcf JCPV	340	#define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE
	341	#define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */
	342	#define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
6c7a1408	343
6d0f6bcf JCPV	344	#define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE
	345	#define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */
	346	#define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
6c7a1408 WD	347
6c7a1408 WD	348	#if CONFIG_TOTAL5200_REV==1
6d0f6bcf JCPV	349	# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
	350	# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
	351	# define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */
6c7a1408	352	#else
6d0f6bcf JCPV	353	# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
	354	# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
	355	# define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */
6c7a1408 WD	356	#endif
6c7a1408 WD	357
6d0f6bcf JCPV	358	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	359	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
6c7a1408 WD	360
	361	/*-----------------------------------------------------------------------
	362	* USB stuff
	363	*-----------------------------------------------------------------------
	364	*/
	365	#define CONFIG_USB_CLOCK 0x0001BBBB
	366	#define CONFIG_USB_CONFIG 0x00001000
	367
	368	/*-----------------------------------------------------------------------
	369	* IDE/ATA stuff Supports IDE harddisk
	370	*-----------------------------------------------------------------------
	371	*/
	372
	373	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	374
	375	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	376	#undef CONFIG_IDE_LED /* LED for ide not supported */
	377
	378	#define CONFIG_IDE_RESET /* reset for ide supported */
	379	#define CONFIG_IDE_PREINIT
	380
6a397ef0	381	#define CONFIG_SYS_ATA_CS_ON_I2C2
6d0f6bcf JCPV	382	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	383	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
6c7a1408	384
6d0f6bcf	385	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
6c7a1408	386
6d0f6bcf	387	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
6c7a1408 WD	388
6c7a1408 WD	389	/* Offset for data I/O */
6d0f6bcf	390	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
6c7a1408 WD	391
6c7a1408 WD	392	/* Offset for normal register accesses */
6d0f6bcf	393	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
6c7a1408 WD	394
6c7a1408 WD	395	/* Offset for alternate registers */
6d0f6bcf	396	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
6c7a1408 WD	397
6c7a1408 WD	398	/* Interval between registers */
6d0f6bcf	399	#define CONFIG_SYS_ATA_STRIDE 4
6c7a1408 WD	400
6c7a1408 WD	401	#endif /* __CONFIG_H */