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6c7a1408 WD |
1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. | |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
6c7a1408 WD |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * Check valid setting of revision define. | |
16 | * Total5100 and Total5200 Rev.1 are identical except for the processor. | |
17 | */ | |
18 | #if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2) | |
19 | #error CONFIG_TOTAL5200_REV must be 1 or 2 | |
20 | #endif | |
21 | ||
22 | /* | |
23 | * High Level Configuration Options | |
24 | * (easy to change) | |
25 | */ | |
26 | ||
27 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
fd428c05 | 28 | #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ |
6c7a1408 WD |
29 | #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ |
30 | ||
2ae18241 WD |
31 | /* |
32 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
33 | * 0xFFF00000 boot high (standard configuration) | |
34 | * 0xFE000000 boot low | |
35 | * 0x00100000 boot from RAM (for testing only) | |
36 | */ | |
37 | #ifndef CONFIG_SYS_TEXT_BASE | |
38 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
39 | #endif | |
40 | ||
6d0f6bcf | 41 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
6c7a1408 | 42 | |
31d82672 BB |
43 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
44 | ||
6c7a1408 WD |
45 | /* |
46 | * Serial console configuration | |
47 | */ | |
48 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ | |
49 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 50 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
6c7a1408 | 51 | |
81050926 WD |
52 | /* |
53 | * Video console | |
54 | */ | |
281e00a3 | 55 | #define CONFIG_VIDEO |
81050926 WD |
56 | #define CONFIG_VIDEO_SED13806 |
57 | #define CONFIG_VIDEO_SED13806_16BPP | |
58 | ||
59 | #define CONFIG_CFB_CONSOLE | |
60 | #define CONFIG_VIDEO_LOGO | |
61 | /* #define CONFIG_VIDEO_BMP_LOGO */ | |
62 | #define CONFIG_CONSOLE_EXTRA_INFO | |
63 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
64 | #define CONFIG_VIDEO_SW_CURSOR | |
65 | #define CONFIG_SPLASH_SCREEN | |
66 | ||
6c7a1408 | 67 | |
6c7a1408 WD |
68 | /* |
69 | * PCI Mapping: | |
70 | * 0x40000000 - 0x4fffffff - PCI Memory | |
71 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
72 | */ | |
73 | #define CONFIG_PCI 1 | |
74 | #define CONFIG_PCI_PNP 1 | |
75 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 76 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
6c7a1408 WD |
77 | |
78 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
79 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
80 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
81 | ||
82 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
83 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
84 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
85 | ||
63ff004c | 86 | #define CONFIG_MII 1 |
6c7a1408 | 87 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 88 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
6c7a1408 WD |
89 | #define CONFIG_NS8382X 1 |
90 | ||
6c7a1408 WD |
91 | /* Partitions */ |
92 | #define CONFIG_MAC_PARTITION | |
93 | #define CONFIG_DOS_PARTITION | |
94 | ||
95 | /* USB */ | |
6c7a1408 | 96 | #define CONFIG_USB_OHCI |
6c7a1408 | 97 | #define CONFIG_USB_STORAGE |
d794cfef | 98 | |
6c7a1408 | 99 | |
a1aa0bb5 JL |
100 | /* |
101 | * BOOTP options | |
102 | */ | |
103 | #define CONFIG_BOOTP_BOOTFILESIZE | |
104 | #define CONFIG_BOOTP_BOOTPATH | |
105 | #define CONFIG_BOOTP_GATEWAY | |
106 | #define CONFIG_BOOTP_HOSTNAME | |
107 | ||
108 | ||
6c7a1408 | 109 | /* |
d794cfef | 110 | * Command line configuration. |
6c7a1408 | 111 | */ |
d794cfef JL |
112 | #include <config_cmd_default.h> |
113 | ||
fd428c05 | 114 | #define CONFIG_CMD_PCI |
d794cfef JL |
115 | |
116 | #define CONFIG_CMD_BMP | |
117 | #define CONFIG_CMD_EEPROM | |
118 | #define CONFIG_CMD_FAT | |
119 | #define CONFIG_CMD_I2C | |
120 | #define CONFIG_CMD_IDE | |
121 | #define CONFIG_CMD_PING | |
122 | #define CONFIG_CMD_USB | |
123 | ||
6c7a1408 | 124 | |
14d0a02a | 125 | #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */ |
6d0f6bcf | 126 | # define CONFIG_SYS_LOWBOOT 1 |
6c7a1408 WD |
127 | #endif |
128 | ||
129 | /* | |
130 | * Autobooting | |
131 | */ | |
132 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
133 | ||
81050926 WD |
134 | #define CONFIG_PREBOOT \ |
135 | "setenv stdout serial;setenv stderr serial;" \ | |
136 | "echo;" \ | |
32bf3d14 | 137 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
6c7a1408 WD |
138 | "echo" |
139 | ||
140 | #undef CONFIG_BOOTARGS | |
141 | ||
142 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
143 | "netdev=eth0\0" \ | |
144 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 145 | "nfsroot=${serverip}:${rootpath}\0" \ |
6c7a1408 | 146 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
147 | "addip=setenv bootargs ${bootargs} " \ |
148 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
149 | ":${hostname}:${netdev}:off panic=1\0" \ | |
6c7a1408 | 150 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 151 | "bootm ${kernel_addr}\0" \ |
6c7a1408 | 152 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
153 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
154 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
6c7a1408 WD |
155 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
156 | "bootfile=/tftpboot/MPC5200/uImage\0" \ | |
157 | "" | |
158 | ||
159 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
160 | ||
6c7a1408 WD |
161 | /* |
162 | * IPB Bus clocking configuration. | |
163 | */ | |
6d0f6bcf | 164 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
6c7a1408 WD |
165 | |
166 | /* | |
167 | * I2C configuration | |
168 | */ | |
169 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 170 | #define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ |
6c7a1408 | 171 | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
173 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
6c7a1408 WD |
174 | |
175 | /* | |
176 | * EEPROM configuration | |
177 | */ | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
179 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
180 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
181 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
6c7a1408 WD |
182 | |
183 | /* | |
184 | * Flash configuration | |
185 | */ | |
6d0f6bcf | 186 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 187 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6c7a1408 | 188 | #if CONFIG_TOTAL5200_REV==2 |
6d0f6bcf JCPV |
189 | # define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ |
190 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START } | |
6c7a1408 | 191 | #else |
6d0f6bcf JCPV |
192 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
193 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } | |
6c7a1408 | 194 | #endif |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
196 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
6c7a1408 WD |
197 | |
198 | #if CONFIG_TOTAL5200_REV==1 | |
6d0f6bcf JCPV |
199 | # define CONFIG_SYS_FLASH_BASE 0xFE000000 |
200 | # define CONFIG_SYS_FLASH_SIZE 0x02000000 | |
6c7a1408 | 201 | #elif CONFIG_TOTAL5200_REV==2 |
6d0f6bcf JCPV |
202 | # define CONFIG_SYS_FLASH_BASE 0xFA000000 |
203 | # define CONFIG_SYS_FLASH_SIZE 0x06000000 | |
6c7a1408 WD |
204 | #endif /* CONFIG_TOTAL5200_REV */ |
205 | ||
6d0f6bcf | 206 | #if defined(CONFIG_SYS_LOWBOOT) |
0e8d1586 | 207 | # define CONFIG_ENV_ADDR 0xFE040000 |
6d0f6bcf | 208 | #else /* CONFIG_SYS_LOWBOOT */ |
0e8d1586 | 209 | # define CONFIG_ENV_ADDR 0xFFF40000 |
6d0f6bcf | 210 | #endif /* CONFIG_SYS_LOWBOOT */ |
6c7a1408 WD |
211 | |
212 | /* | |
213 | * Environment settings | |
214 | */ | |
5a1aceb0 | 215 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
216 | #define CONFIG_ENV_SIZE 0x40000 |
217 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
6c7a1408 WD |
218 | #define CONFIG_ENV_OVERWRITE 1 |
219 | ||
220 | /* | |
221 | * Memory map | |
222 | */ | |
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
224 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
225 | #define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */ | |
226 | #define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */ | |
227 | #define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */ | |
228 | #define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */ | |
6c7a1408 WD |
229 | |
230 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 231 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 232 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
6c7a1408 | 233 | |
25ddd1fb | 234 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 235 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
6c7a1408 | 236 | |
14d0a02a | 237 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
238 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
239 | # define CONFIG_SYS_RAMBOOT 1 | |
6c7a1408 WD |
240 | #endif |
241 | ||
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
243 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
244 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
6c7a1408 WD |
245 | |
246 | /* | |
247 | * Ethernet configuration | |
248 | */ | |
249 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 250 | #define CONFIG_MPC5xxx_FEC_SEVENWIRE |
6c7a1408 WD |
251 | /* dummy, 7-wire FEC does not have phy address */ |
252 | #define CONFIG_PHY_ADDR 0x00 | |
253 | ||
254 | /* | |
255 | * GPIO configuration | |
256 | * | |
257 | * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0 | |
258 | * Reserved 0 | |
259 | * ALTs: CAN1/2 on PSC2, SPI on PSC3 00 | |
260 | * CS7: Interrupt GPIO on PSC3_5 0 | |
261 | * CS8: Interrupt GPIO on PSC3_4 0 | |
262 | * ATA: reset default, changed in ATA driver 00 | |
263 | * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0 | |
264 | * IRDA: reset default, changed in IrDA driver 000 | |
265 | * ETHER: reset default, changed in Ethernet driver 0000 | |
266 | * PCI_DIS: reset default, changed in PCI driver 0 | |
267 | * USB_SE: reset default, changed in USB driver 0 | |
268 | * USB: reset default, changed in USB driver 00 | |
269 | * PSC3: SPI and UART functionality without CD 1100 | |
270 | * Reserved 0 | |
271 | * PSC2: CAN1/2 001 | |
272 | * Reserved 0 | |
273 | * PSC1: reset default, changed in AC'97 driver 000 | |
274 | * | |
275 | */ | |
6d0f6bcf | 276 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10 |
6c7a1408 WD |
277 | |
278 | /* | |
279 | * Miscellaneous configurable options | |
280 | */ | |
6d0f6bcf JCPV |
281 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
282 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
d794cfef | 283 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 284 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
6c7a1408 | 285 | #else |
6d0f6bcf | 286 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
6c7a1408 | 287 | #endif |
6d0f6bcf JCPV |
288 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
289 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
290 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
6c7a1408 | 291 | |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
293 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
6c7a1408 | 294 | |
6d0f6bcf | 295 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
6c7a1408 | 296 | |
6d0f6bcf | 297 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
6c7a1408 | 298 | |
6d0f6bcf | 299 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
d794cfef | 300 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 301 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
d794cfef JL |
302 | #endif |
303 | ||
304 | ||
6c7a1408 WD |
305 | /* |
306 | * Various low-level settings | |
307 | */ | |
6d0f6bcf JCPV |
308 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
309 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
6c7a1408 WD |
310 | |
311 | #if CONFIG_TOTAL5200_REV==1 | |
6d0f6bcf JCPV |
312 | # define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
313 | # define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ | |
314 | # define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ | |
315 | # define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
316 | # define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */ | |
6c7a1408 | 317 | #else |
6d0f6bcf JCPV |
318 | # define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE) |
319 | # define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ | |
320 | # define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ | |
321 | # define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE) | |
322 | # define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */ | |
323 | # define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ | |
324 | # define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE | |
325 | # define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */ | |
326 | # define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ | |
6c7a1408 WD |
327 | #endif |
328 | ||
6d0f6bcf JCPV |
329 | #define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE |
330 | #define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */ | |
331 | #define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */ | |
6c7a1408 | 332 | |
6d0f6bcf JCPV |
333 | #define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE |
334 | #define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */ | |
335 | #define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */ | |
6c7a1408 WD |
336 | |
337 | #if CONFIG_TOTAL5200_REV==1 | |
6d0f6bcf JCPV |
338 | # define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE |
339 | # define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ | |
340 | # define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */ | |
6c7a1408 | 341 | #else |
6d0f6bcf JCPV |
342 | # define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE |
343 | # define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ | |
344 | # define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */ | |
6c7a1408 WD |
345 | #endif |
346 | ||
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_CS_BURST 0x00000000 |
348 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
6c7a1408 WD |
349 | |
350 | /*----------------------------------------------------------------------- | |
351 | * USB stuff | |
352 | *----------------------------------------------------------------------- | |
353 | */ | |
354 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
355 | #define CONFIG_USB_CONFIG 0x00001000 | |
356 | ||
357 | /*----------------------------------------------------------------------- | |
358 | * IDE/ATA stuff Supports IDE harddisk | |
359 | *----------------------------------------------------------------------- | |
360 | */ | |
361 | ||
362 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
363 | ||
364 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
365 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
366 | ||
367 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
368 | #define CONFIG_IDE_PREINIT | |
369 | ||
6a397ef0 | 370 | #define CONFIG_SYS_ATA_CS_ON_I2C2 |
6d0f6bcf JCPV |
371 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
372 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
6c7a1408 | 373 | |
6d0f6bcf | 374 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
6c7a1408 | 375 | |
6d0f6bcf | 376 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
6c7a1408 WD |
377 | |
378 | /* Offset for data I/O */ | |
6d0f6bcf | 379 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
6c7a1408 WD |
380 | |
381 | /* Offset for normal register accesses */ | |
6d0f6bcf | 382 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
6c7a1408 WD |
383 | |
384 | /* Offset for alternate registers */ | |
6d0f6bcf | 385 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
6c7a1408 WD |
386 | |
387 | /* Interval between registers */ | |
6d0f6bcf | 388 | #define CONFIG_SYS_ATA_STRIDE 4 |
6c7a1408 WD |
389 | |
390 | #endif /* __CONFIG_H */ |