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Commit | Line | Data |
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13fdf8a6 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
13fdf8a6 SR |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
c837dcb1 WD |
21 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
22 | #define CONFIG_VOH405 1 /* ...on a VOH405 board */ | |
13fdf8a6 | 23 | |
2ae18241 WD |
24 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
25 | ||
c837dcb1 WD |
26 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
27 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
13fdf8a6 | 28 | |
a20b27a3 | 29 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ |
13fdf8a6 SR |
30 | |
31 | #define CONFIG_BAUDRATE 9600 | |
32 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
33 | ||
34 | #undef CONFIG_BOOTARGS | |
a20b27a3 SR |
35 | #undef CONFIG_BOOTCOMMAND |
36 | ||
37 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
38 | ||
6d0f6bcf | 39 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
13fdf8a6 | 40 | |
b56bd0fc MF |
41 | #undef CONFIG_HAS_ETH1 |
42 | ||
96e21f86 | 43 | #define CONFIG_PPC4xx_EMAC |
13fdf8a6 | 44 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 45 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 46 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
b56bd0fc | 47 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
a20b27a3 SR |
48 | |
49 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
13fdf8a6 | 50 | |
a5562901 | 51 | |
a1aa0bb5 JL |
52 | /* |
53 | * BOOTP options | |
54 | */ | |
55 | #define CONFIG_BOOTP_BOOTFILESIZE | |
56 | #define CONFIG_BOOTP_BOOTPATH | |
57 | #define CONFIG_BOOTP_GATEWAY | |
58 | #define CONFIG_BOOTP_HOSTNAME | |
59 | ||
60 | ||
a5562901 JL |
61 | /* |
62 | * Command line configuration. | |
63 | */ | |
64 | #include <config_cmd_default.h> | |
65 | ||
66 | #define CONFIG_CMD_DHCP | |
67 | #define CONFIG_CMD_PCI | |
68 | #define CONFIG_CMD_IRQ | |
69 | #define CONFIG_CMD_IDE | |
70 | #define CONFIG_CMD_FAT | |
71 | #define CONFIG_CMD_ELF | |
72 | #define CONFIG_CMD_NAND | |
73 | #define CONFIG_CMD_DATE | |
74 | #define CONFIG_CMD_I2C | |
75 | #define CONFIG_CMD_MII | |
76 | #define CONFIG_CMD_PING | |
77 | #define CONFIG_CMD_EEPROM | |
78 | ||
13fdf8a6 SR |
79 | |
80 | #define CONFIG_MAC_PARTITION | |
81 | #define CONFIG_DOS_PARTITION | |
82 | ||
a20b27a3 SR |
83 | #define CONFIG_SUPPORT_VFAT |
84 | ||
c837dcb1 | 85 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
13fdf8a6 | 86 | |
c837dcb1 | 87 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ |
6d0f6bcf | 88 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ |
13fdf8a6 | 89 | |
c837dcb1 | 90 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
13fdf8a6 SR |
91 | |
92 | /* | |
93 | * Miscellaneous configurable options | |
94 | */ | |
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
96 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
13fdf8a6 | 97 | |
6d0f6bcf | 98 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
13fdf8a6 | 99 | |
a5562901 | 100 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 101 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
13fdf8a6 | 102 | #else |
6d0f6bcf | 103 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
13fdf8a6 | 104 | #endif |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
106 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
107 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
13fdf8a6 | 108 | |
6d0f6bcf | 109 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
13fdf8a6 | 110 | |
6d0f6bcf | 111 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
13fdf8a6 | 112 | |
a20b27a3 SR |
113 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
114 | ||
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
116 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
13fdf8a6 | 117 | |
550650dd SR |
118 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
119 | #define CONFIG_SYS_NS16550 | |
120 | #define CONFIG_SYS_NS16550_SERIAL | |
121 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
122 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
123 | ||
6d0f6bcf | 124 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 125 | #define CONFIG_SYS_BASE_BAUD 691200 |
13fdf8a6 SR |
126 | |
127 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 128 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
13fdf8a6 SR |
129 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
130 | 57600, 115200, 230400, 460800, 921600 } | |
131 | ||
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
133 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
13fdf8a6 | 134 | |
6d0f6bcf | 135 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
13fdf8a6 SR |
136 | |
137 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
138 | ||
c837dcb1 | 139 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
13fdf8a6 | 140 | |
6d0f6bcf | 141 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
13fdf8a6 SR |
142 | |
143 | /*----------------------------------------------------------------------- | |
144 | * NAND-FLASH stuff | |
145 | *----------------------------------------------------------------------- | |
146 | */ | |
6d0f6bcf | 147 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
6d0f6bcf | 148 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
bd84ee4c MF |
149 | #define NAND_BIG_DELAY_US 25 |
150 | ||
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
152 | #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
153 | #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
154 | #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
13fdf8a6 | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
157 | #define CONFIG_SYS_NAND_QUIET 1 | |
a20b27a3 | 158 | |
13fdf8a6 SR |
159 | /*----------------------------------------------------------------------- |
160 | * PCI stuff | |
161 | *----------------------------------------------------------------------- | |
162 | */ | |
a20b27a3 SR |
163 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
164 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
165 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
166 | ||
167 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 168 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
a20b27a3 SR |
169 | #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ |
170 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
171 | /* resource configuration */ | |
172 | ||
173 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
174 | ||
175 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
176 | ||
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
178 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
179 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
180 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
181 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
182 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
183 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
184 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
185 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
13fdf8a6 SR |
186 | |
187 | /*----------------------------------------------------------------------- | |
188 | * IDE/ATA stuff | |
189 | *----------------------------------------------------------------------- | |
190 | */ | |
c837dcb1 WD |
191 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
192 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
13fdf8a6 SR |
193 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
194 | ||
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
196 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ | |
13fdf8a6 | 197 | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
199 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
200 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0010 | |
13fdf8a6 | 201 | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
203 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
204 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
13fdf8a6 SR |
205 | |
206 | /* | |
207 | * For booting Linux, the board info and command line data | |
208 | * have to be in the first 8 MB of memory, since this is | |
209 | * the maximum mapped by the Linux kernel during initialization. | |
210 | */ | |
6d0f6bcf | 211 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
13fdf8a6 SR |
212 | /*----------------------------------------------------------------------- |
213 | * FLASH organization | |
214 | */ | |
215 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
216 | ||
6d0f6bcf JCPV |
217 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
218 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
13fdf8a6 | 219 | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
221 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
13fdf8a6 | 222 | |
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
224 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
225 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
13fdf8a6 SR |
226 | /* |
227 | * The following defines are added for buggy IOP480 byte interface. | |
228 | * All other boards should use the standard values (CPCI405 etc.) | |
229 | */ | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
231 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
232 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
13fdf8a6 | 233 | |
6d0f6bcf | 234 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
13fdf8a6 | 235 | |
13fdf8a6 SR |
236 | /*----------------------------------------------------------------------- |
237 | * Start addresses for the final memory configuration | |
238 | * (Set up by the startup code) | |
6d0f6bcf | 239 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
13fdf8a6 | 240 | */ |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
242 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 | |
14d0a02a | 243 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ |
245 | #define CONFIG_SYS_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */ | |
246 | ||
247 | #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) | |
248 | # define CONFIG_SYS_RAMBOOT 1 | |
13fdf8a6 | 249 | #else |
6d0f6bcf | 250 | # undef CONFIG_SYS_RAMBOOT |
13fdf8a6 SR |
251 | #endif |
252 | ||
253 | /*----------------------------------------------------------------------- | |
254 | * Environment Variable setup | |
255 | */ | |
bb1f8b4f | 256 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
257 | #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
258 | #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ | |
13fdf8a6 SR |
259 | /* total size of a CAT24WC16 is 2048 bytes */ |
260 | ||
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ |
262 | #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ | |
13fdf8a6 SR |
263 | |
264 | /*----------------------------------------------------------------------- | |
265 | * I2C EEPROM (CAT24WC16) for environment | |
266 | */ | |
880540de DE |
267 | #define CONFIG_SYS_I2C |
268 | #define CONFIG_SYS_I2C_PPC4XX | |
269 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
270 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 | |
271 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
13fdf8a6 | 272 | |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ |
274 | #define CONFIG_SYS_EEPROM_WREN 1 | |
b56bd0fc | 275 | |
13fdf8a6 | 276 | /* CAT24WC32/64... */ |
6d0f6bcf | 277 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ |
c837dcb1 | 278 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
279 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 |
280 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ | |
13fdf8a6 | 281 | /* 32 byte page write mode using*/ |
c837dcb1 | 282 | /* last 5 bits of the address */ |
6d0f6bcf | 283 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
13fdf8a6 | 284 | |
13fdf8a6 SR |
285 | /*----------------------------------------------------------------------- |
286 | * External Bus Controller (EBC) Setup | |
287 | */ | |
288 | ||
c837dcb1 WD |
289 | #define CAN_BA 0xF0000000 /* CAN Base Address */ |
290 | #define DUART0_BA 0xF0000400 /* DUART Base Address */ | |
291 | #define DUART1_BA 0xF0000408 /* DUART Base Address */ | |
292 | #define RTC_BA 0xF0000500 /* RTC Base Address */ | |
293 | #define VGA_BA 0xF1000000 /* Epson VGA Base Address */ | |
6d0f6bcf | 294 | #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ |
13fdf8a6 | 295 | |
c837dcb1 | 296 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
6d0f6bcf JCPV |
297 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
298 | /*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ | |
299 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
13fdf8a6 | 300 | |
c837dcb1 | 301 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
303 | #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ | |
13fdf8a6 | 304 | |
c837dcb1 | 305 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
6d0f6bcf JCPV |
306 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
307 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
13fdf8a6 | 308 | |
c837dcb1 | 309 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
311 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
13fdf8a6 | 312 | |
c837dcb1 | 313 | /* Memory Bank 4 (Epson VGA) initialization */ |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ |
315 | #define CONFIG_SYS_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ | |
13fdf8a6 | 316 | |
a20b27a3 SR |
317 | /*----------------------------------------------------------------------- |
318 | * LCD Setup | |
319 | */ | |
320 | ||
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ |
322 | #define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ | |
323 | #define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ | |
324 | #define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ | |
a20b27a3 | 325 | |
6d0f6bcf | 326 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20) |
a20b27a3 | 327 | |
13fdf8a6 SR |
328 | /*----------------------------------------------------------------------- |
329 | * FPGA stuff | |
330 | */ | |
331 | ||
6d0f6bcf | 332 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ |
13fdf8a6 SR |
333 | |
334 | /* FPGA internal regs */ | |
6d0f6bcf | 335 | #define CONFIG_SYS_FPGA_CTRL 0x000 |
13fdf8a6 SR |
336 | |
337 | /* FPGA Control Reg */ | |
6d0f6bcf JCPV |
338 | #define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001 |
339 | #define CONFIG_SYS_FPGA_CTRL_WDI 0x0002 | |
340 | #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020 | |
13fdf8a6 | 341 | |
6d0f6bcf JCPV |
342 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
343 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
13fdf8a6 SR |
344 | |
345 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
346 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
347 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
348 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
349 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
350 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
13fdf8a6 SR |
351 | |
352 | /*----------------------------------------------------------------------- | |
353 | * Definitions for initial stack pointer and data area (in data cache) | |
354 | */ | |
355 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 356 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
13fdf8a6 SR |
357 | |
358 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
359 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
360 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
361 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 362 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
13fdf8a6 | 363 | |
25ddd1fb | 364 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 365 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
13fdf8a6 SR |
366 | |
367 | /*----------------------------------------------------------------------- | |
368 | * Definitions for GPIO setup (PPC405EP specific) | |
369 | * | |
c837dcb1 WD |
370 | * GPIO0[0] - External Bus Controller BLAST output |
371 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
13fdf8a6 SR |
372 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
373 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
374 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
375 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
376 | * GPIO0[28-29] - UART1 data signal input/output | |
a20b27a3 | 377 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO |
13fdf8a6 | 378 | */ |
afabb498 SR |
379 | #define CONFIG_SYS_GPIO0_OSRL 0x00000550 |
380 | #define CONFIG_SYS_GPIO0_OSRH 0x00000110 | |
381 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 | |
382 | #define CONFIG_SYS_GPIO0_ISR1H 0x15555440 | |
6d0f6bcf | 383 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 |
afabb498 | 384 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 |
6d0f6bcf JCPV |
385 | #define CONFIG_SYS_GPIO0_TCR 0x777E0017 |
386 | ||
387 | #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) | |
388 | #define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7) | |
389 | #define CONFIG_SYS_IIC_ON (0x80000000 >> 8) | |
390 | #define CONFIG_SYS_LCD0_RST (0x80000000 >> 30) | |
391 | #define CONFIG_SYS_LCD1_RST (0x80000000 >> 31) | |
392 | #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0) | |
13fdf8a6 | 393 | |
13fdf8a6 SR |
394 | /* |
395 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
396 | * This value will be set if iic boot eprom is disabled. | |
397 | */ | |
398 | #if 1 | |
c837dcb1 WD |
399 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
400 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
13fdf8a6 SR |
401 | #endif |
402 | #if 0 | |
c837dcb1 WD |
403 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 |
404 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
13fdf8a6 SR |
405 | #endif |
406 | #if 0 | |
c837dcb1 WD |
407 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
408 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
13fdf8a6 SR |
409 | #endif |
410 | ||
411 | #endif /* __CONFIG_H */ |