]>
Commit | Line | Data |
---|---|---|
13fdf8a6 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
c837dcb1 WD |
37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
38 | #define CONFIG_VOH405 1 /* ...on a VOH405 board */ | |
13fdf8a6 | 39 | |
c837dcb1 WD |
40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
41 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
13fdf8a6 | 42 | |
a20b27a3 | 43 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ |
13fdf8a6 SR |
44 | |
45 | #define CONFIG_BAUDRATE 9600 | |
46 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
47 | ||
48 | #undef CONFIG_BOOTARGS | |
a20b27a3 SR |
49 | #undef CONFIG_BOOTCOMMAND |
50 | ||
51 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
52 | ||
13fdf8a6 SR |
53 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
54 | ||
55 | #define CONFIG_MII 1 /* MII PHY management */ | |
c837dcb1 | 56 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 SR |
57 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
58 | ||
59 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
13fdf8a6 | 60 | |
a5562901 | 61 | |
a1aa0bb5 JL |
62 | /* |
63 | * BOOTP options | |
64 | */ | |
65 | #define CONFIG_BOOTP_BOOTFILESIZE | |
66 | #define CONFIG_BOOTP_BOOTPATH | |
67 | #define CONFIG_BOOTP_GATEWAY | |
68 | #define CONFIG_BOOTP_HOSTNAME | |
69 | ||
70 | ||
a5562901 JL |
71 | /* |
72 | * Command line configuration. | |
73 | */ | |
74 | #include <config_cmd_default.h> | |
75 | ||
76 | #define CONFIG_CMD_DHCP | |
77 | #define CONFIG_CMD_PCI | |
78 | #define CONFIG_CMD_IRQ | |
79 | #define CONFIG_CMD_IDE | |
80 | #define CONFIG_CMD_FAT | |
81 | #define CONFIG_CMD_ELF | |
82 | #define CONFIG_CMD_NAND | |
83 | #define CONFIG_CMD_DATE | |
84 | #define CONFIG_CMD_I2C | |
85 | #define CONFIG_CMD_MII | |
86 | #define CONFIG_CMD_PING | |
87 | #define CONFIG_CMD_EEPROM | |
88 | ||
13fdf8a6 SR |
89 | |
90 | #define CONFIG_MAC_PARTITION | |
91 | #define CONFIG_DOS_PARTITION | |
92 | ||
a20b27a3 SR |
93 | #define CONFIG_SUPPORT_VFAT |
94 | ||
c837dcb1 | 95 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
13fdf8a6 | 96 | |
c837dcb1 WD |
97 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ |
98 | #define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ | |
13fdf8a6 | 99 | |
c837dcb1 | 100 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
13fdf8a6 SR |
101 | |
102 | /* | |
103 | * Miscellaneous configurable options | |
104 | */ | |
105 | #define CFG_LONGHELP /* undef to save memory */ | |
106 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
107 | ||
108 | #undef CFG_HUSH_PARSER /* use "hush" command parser */ | |
109 | #ifdef CFG_HUSH_PARSER | |
c837dcb1 | 110 | #define CFG_PROMPT_HUSH_PS2 "> " |
13fdf8a6 SR |
111 | #endif |
112 | ||
a5562901 | 113 | #if defined(CONFIG_CMD_KGDB) |
c837dcb1 | 114 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
13fdf8a6 | 115 | #else |
c837dcb1 | 116 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
13fdf8a6 SR |
117 | #endif |
118 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
119 | #define CFG_MAXARGS 16 /* max number of command args */ | |
120 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
121 | ||
c837dcb1 | 122 | #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ |
13fdf8a6 | 123 | |
c837dcb1 | 124 | #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
13fdf8a6 | 125 | |
a20b27a3 SR |
126 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
127 | ||
13fdf8a6 SR |
128 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
129 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
130 | ||
a20b27a3 SR |
131 | #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ |
132 | #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ | |
133 | #define CFG_BASE_BAUD 691200 | |
134 | #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ | |
13fdf8a6 SR |
135 | |
136 | /* The following table includes the supported baudrates */ | |
c837dcb1 | 137 | #define CFG_BAUDRATE_TABLE \ |
13fdf8a6 SR |
138 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
139 | 57600, 115200, 230400, 460800, 921600 } | |
140 | ||
141 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
142 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
143 | ||
c837dcb1 | 144 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
13fdf8a6 SR |
145 | |
146 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
147 | ||
c837dcb1 | 148 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
13fdf8a6 | 149 | |
c837dcb1 | 150 | #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
13fdf8a6 SR |
151 | |
152 | /*----------------------------------------------------------------------- | |
153 | * NAND-FLASH stuff | |
154 | *----------------------------------------------------------------------- | |
155 | */ | |
addb2e16 BS |
156 | #define CFG_NAND_LEGACY |
157 | ||
13fdf8a6 SR |
158 | #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
159 | #define SECTORSIZE 512 | |
160 | ||
161 | #define ADDR_COLUMN 1 | |
162 | #define ADDR_PAGE 2 | |
163 | #define ADDR_COLUMN_PAGE 3 | |
164 | ||
c837dcb1 | 165 | #define NAND_ChipID_UNKNOWN 0x00 |
13fdf8a6 SR |
166 | #define NAND_MAX_FLOORS 1 |
167 | #define NAND_MAX_CHIPS 1 | |
168 | ||
c837dcb1 WD |
169 | #define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
170 | #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
171 | #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
172 | #define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
13fdf8a6 SR |
173 | |
174 | #define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) | |
175 | #define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) | |
176 | #define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) | |
177 | #define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) | |
178 | #define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) | |
179 | #define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) | |
180 | #define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) | |
181 | ||
182 | #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) | |
183 | #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) | |
184 | #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) | |
185 | #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) | |
186 | ||
a20b27a3 SR |
187 | #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
188 | ||
13fdf8a6 SR |
189 | /*----------------------------------------------------------------------- |
190 | * PCI stuff | |
191 | *----------------------------------------------------------------------- | |
192 | */ | |
a20b27a3 SR |
193 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
194 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
195 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
196 | ||
197 | #define CONFIG_PCI /* include pci support */ | |
198 | #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ | |
199 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
200 | /* resource configuration */ | |
201 | ||
202 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
203 | ||
204 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
205 | ||
206 | #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ | |
207 | #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
208 | #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
209 | #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
210 | #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
211 | #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
212 | #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
213 | #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
214 | #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
13fdf8a6 SR |
215 | |
216 | /*----------------------------------------------------------------------- | |
217 | * IDE/ATA stuff | |
218 | *----------------------------------------------------------------------- | |
219 | */ | |
c837dcb1 WD |
220 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
221 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
13fdf8a6 SR |
222 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
223 | ||
c837dcb1 WD |
224 | #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
225 | #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ | |
13fdf8a6 | 226 | |
c837dcb1 | 227 | #define CONFIG_ATAPI 1 /* ATAPI for Travelstar */ |
13fdf8a6 | 228 | |
c837dcb1 WD |
229 | #define CFG_ATA_BASE_ADDR 0xF0100000 |
230 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
231 | #define CFG_ATA_IDE1_OFFSET 0x0010 | |
13fdf8a6 SR |
232 | |
233 | #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ | |
c837dcb1 | 234 | #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ |
13fdf8a6 SR |
235 | #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ |
236 | ||
237 | /* | |
238 | * For booting Linux, the board info and command line data | |
239 | * have to be in the first 8 MB of memory, since this is | |
240 | * the maximum mapped by the Linux kernel during initialization. | |
241 | */ | |
242 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
243 | /*----------------------------------------------------------------------- | |
244 | * FLASH organization | |
245 | */ | |
246 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
247 | ||
248 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
249 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
250 | ||
251 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
252 | #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
253 | ||
c837dcb1 WD |
254 | #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
255 | #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
256 | #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
13fdf8a6 SR |
257 | /* |
258 | * The following defines are added for buggy IOP480 byte interface. | |
259 | * All other boards should use the standard values (CPCI405 etc.) | |
260 | */ | |
c837dcb1 WD |
261 | #define CFG_FLASH_READ0 0x0000 /* 0 is standard */ |
262 | #define CFG_FLASH_READ1 0x0001 /* 1 is standard */ | |
263 | #define CFG_FLASH_READ2 0x0002 /* 2 is standard */ | |
13fdf8a6 | 264 | |
c837dcb1 | 265 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
13fdf8a6 SR |
266 | |
267 | #if 0 /* test-only */ | |
c837dcb1 WD |
268 | #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ |
269 | #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ | |
13fdf8a6 SR |
270 | #endif |
271 | ||
272 | /*----------------------------------------------------------------------- | |
273 | * Start addresses for the final memory configuration | |
274 | * (Set up by the startup code) | |
275 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
276 | */ | |
277 | #define CFG_SDRAM_BASE 0x00000000 | |
a20b27a3 | 278 | #define CFG_FLASH_BASE 0xFFF80000 |
13fdf8a6 | 279 | #define CFG_MONITOR_BASE TEXT_BASE |
a20b27a3 SR |
280 | #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ |
281 | #define CFG_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */ | |
13fdf8a6 SR |
282 | |
283 | #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) | |
284 | # define CFG_RAMBOOT 1 | |
285 | #else | |
286 | # undef CFG_RAMBOOT | |
287 | #endif | |
288 | ||
289 | /*----------------------------------------------------------------------- | |
290 | * Environment Variable setup | |
291 | */ | |
c837dcb1 WD |
292 | #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
293 | #define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ | |
294 | #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ | |
13fdf8a6 SR |
295 | /* total size of a CAT24WC16 is 2048 bytes */ |
296 | ||
297 | #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ | |
c837dcb1 | 298 | #define CFG_NVRAM_SIZE 242 /* NVRAM size */ |
13fdf8a6 SR |
299 | |
300 | /*----------------------------------------------------------------------- | |
301 | * I2C EEPROM (CAT24WC16) for environment | |
302 | */ | |
303 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
304 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
305 | #define CFG_I2C_SLAVE 0x7F | |
306 | ||
307 | #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ | |
308 | #if 0 /* test-only */ | |
309 | /* CAT24WC08/16... */ | |
c837dcb1 WD |
310 | #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
311 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
13fdf8a6 SR |
312 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
313 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
314 | /* 16 byte page write mode using*/ | |
c837dcb1 | 315 | /* last 4 bits of the address */ |
13fdf8a6 SR |
316 | #else |
317 | /* CAT24WC32/64... */ | |
c837dcb1 WD |
318 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ |
319 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
13fdf8a6 SR |
320 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 |
321 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ | |
322 | /* 32 byte page write mode using*/ | |
c837dcb1 | 323 | /* last 5 bits of the address */ |
13fdf8a6 SR |
324 | #endif |
325 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
326 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
327 | ||
328 | /*----------------------------------------------------------------------- | |
329 | * Cache Configuration | |
330 | */ | |
0c8721a4 | 331 | #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ |
c837dcb1 | 332 | /* have only 8kB, 16kB is save here */ |
13fdf8a6 | 333 | #define CFG_CACHELINE_SIZE 32 /* ... */ |
a5562901 | 334 | #if defined(CONFIG_CMD_KGDB) |
13fdf8a6 SR |
335 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
336 | #endif | |
337 | ||
338 | /*----------------------------------------------------------------------- | |
339 | * External Bus Controller (EBC) Setup | |
340 | */ | |
341 | ||
c837dcb1 WD |
342 | #define CAN_BA 0xF0000000 /* CAN Base Address */ |
343 | #define DUART0_BA 0xF0000400 /* DUART Base Address */ | |
344 | #define DUART1_BA 0xF0000408 /* DUART Base Address */ | |
345 | #define RTC_BA 0xF0000500 /* RTC Base Address */ | |
346 | #define VGA_BA 0xF1000000 /* Epson VGA Base Address */ | |
347 | #define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ | |
13fdf8a6 | 348 | |
c837dcb1 WD |
349 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
350 | #define CFG_EBC_PB0AP 0x92015480 | |
351 | /*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ | |
352 | #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
13fdf8a6 | 353 | |
c837dcb1 WD |
354 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
355 | #define CFG_EBC_PB1AP 0x92015480 | |
356 | #define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ | |
13fdf8a6 | 357 | |
c837dcb1 WD |
358 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
359 | #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
360 | #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
13fdf8a6 | 361 | |
c837dcb1 WD |
362 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ |
363 | #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
364 | #define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
13fdf8a6 | 365 | |
c837dcb1 WD |
366 | /* Memory Bank 4 (Epson VGA) initialization */ |
367 | #define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ | |
368 | #define CFG_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ | |
13fdf8a6 | 369 | |
a20b27a3 SR |
370 | /*----------------------------------------------------------------------- |
371 | * LCD Setup | |
372 | */ | |
373 | ||
374 | #define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ | |
375 | #define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ | |
376 | #define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ | |
377 | #define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ | |
378 | ||
c29ab9d7 | 379 | #define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20) |
a20b27a3 | 380 | |
13fdf8a6 SR |
381 | /*----------------------------------------------------------------------- |
382 | * FPGA stuff | |
383 | */ | |
384 | ||
c837dcb1 | 385 | #define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ |
13fdf8a6 SR |
386 | |
387 | /* FPGA internal regs */ | |
c837dcb1 | 388 | #define CFG_FPGA_CTRL 0x000 |
13fdf8a6 SR |
389 | |
390 | /* FPGA Control Reg */ | |
c837dcb1 WD |
391 | #define CFG_FPGA_CTRL_CF_RESET 0x0001 |
392 | #define CFG_FPGA_CTRL_WDI 0x0002 | |
13fdf8a6 SR |
393 | #define CFG_FPGA_CTRL_PS2_RESET 0x0020 |
394 | ||
c837dcb1 WD |
395 | #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
396 | #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
13fdf8a6 SR |
397 | |
398 | /* FPGA program pin configuration */ | |
c837dcb1 WD |
399 | #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
400 | #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
401 | #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
402 | #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
403 | #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
13fdf8a6 SR |
404 | |
405 | /*----------------------------------------------------------------------- | |
406 | * Definitions for initial stack pointer and data area (in data cache) | |
407 | */ | |
408 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
c837dcb1 | 409 | #define CFG_TEMP_STACK_OCM 1 |
13fdf8a6 SR |
410 | |
411 | /* On Chip Memory location */ | |
412 | #define CFG_OCM_DATA_ADDR 0xF8000000 | |
413 | #define CFG_OCM_DATA_SIZE 0x1000 | |
414 | #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ | |
415 | #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ | |
416 | ||
417 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
418 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
c837dcb1 | 419 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
13fdf8a6 SR |
420 | |
421 | /*----------------------------------------------------------------------- | |
422 | * Definitions for GPIO setup (PPC405EP specific) | |
423 | * | |
c837dcb1 WD |
424 | * GPIO0[0] - External Bus Controller BLAST output |
425 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
13fdf8a6 SR |
426 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
427 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
428 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
429 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
430 | * GPIO0[28-29] - UART1 data signal input/output | |
a20b27a3 | 431 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO |
13fdf8a6 | 432 | */ |
c837dcb1 WD |
433 | #define CFG_GPIO0_OSRH 0x40000550 |
434 | #define CFG_GPIO0_OSRL 0x00000110 | |
435 | #define CFG_GPIO0_ISR1H 0x00000000 | |
a20b27a3 | 436 | #define CFG_GPIO0_ISR1L 0x15555440 |
c837dcb1 WD |
437 | #define CFG_GPIO0_TSRH 0x00000000 |
438 | #define CFG_GPIO0_TSRL 0x00000000 | |
a20b27a3 | 439 | #define CFG_GPIO0_TCR 0xF7FE0017 |
13fdf8a6 | 440 | |
c837dcb1 | 441 | #define CFG_DUART_RST (0x80000000 >> 14) |
a20b27a3 SR |
442 | #define CFG_LCD_ENDIAN (0x80000000 >> 7) |
443 | #define CFG_LCD0_RST (0x80000000 >> 30) | |
444 | #define CFG_LCD1_RST (0x80000000 >> 31) | |
13fdf8a6 SR |
445 | |
446 | /* | |
447 | * Internal Definitions | |
448 | * | |
449 | * Boot Flags | |
450 | */ | |
451 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
452 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
453 | ||
454 | /* | |
455 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
456 | * This value will be set if iic boot eprom is disabled. | |
457 | */ | |
458 | #if 1 | |
c837dcb1 WD |
459 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
460 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
13fdf8a6 SR |
461 | #endif |
462 | #if 0 | |
c837dcb1 WD |
463 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 |
464 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
13fdf8a6 SR |
465 | #endif |
466 | #if 0 | |
c837dcb1 WD |
467 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
468 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
13fdf8a6 SR |
469 | #endif |
470 | ||
471 | #endif /* __CONFIG_H */ |