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13fdf8a6 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
38 | #define CONFIG_VOH405 1 /* ...on a VOH405 board */ | |
39 | ||
40 | #define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */ | |
41 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
42 | ||
43 | #define CONFIG_SYS_CLK_FREQ 33333334 /* external frequency to pll */ | |
44 | ||
45 | #define CONFIG_BAUDRATE 9600 | |
46 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
47 | ||
48 | #undef CONFIG_BOOTARGS | |
49 | #define CONFIG_RAMBOOTCOMMAND \ | |
50 | "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \ | |
51 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ | |
52 | "bootm ffc00000 ffca0000" | |
53 | #define CONFIG_NFSBOOTCOMMAND \ | |
54 | "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ | |
55 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ | |
56 | "bootm ffc00000" | |
57 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
58 | ||
59 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
60 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
61 | ||
62 | #define CONFIG_MII 1 /* MII PHY management */ | |
63 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
64 | ||
65 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ | |
66 | CFG_CMD_DHCP | \ | |
67 | CFG_CMD_PCI | \ | |
68 | CFG_CMD_IRQ | \ | |
69 | CFG_CMD_IDE | \ | |
70 | CFG_CMD_ELF | \ | |
71 | CFG_CMD_NAND | \ | |
72 | CFG_CMD_DATE | \ | |
73 | CFG_CMD_I2C | \ | |
74 | CFG_CMD_MII | \ | |
75 | CFG_CMD_PING | \ | |
76 | CFG_CMD_EEPROM ) | |
77 | ||
78 | #define CONFIG_MAC_PARTITION | |
79 | #define CONFIG_DOS_PARTITION | |
80 | ||
81 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
82 | #include <cmd_confdefs.h> | |
83 | ||
84 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
85 | ||
86 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ | |
87 | #define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ | |
88 | ||
89 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
90 | ||
91 | /* | |
92 | * Miscellaneous configurable options | |
93 | */ | |
94 | #define CFG_LONGHELP /* undef to save memory */ | |
95 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
96 | ||
97 | #undef CFG_HUSH_PARSER /* use "hush" command parser */ | |
98 | #ifdef CFG_HUSH_PARSER | |
99 | #define CFG_PROMPT_HUSH_PS2 "> " | |
100 | #endif | |
101 | ||
102 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
103 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
104 | #else | |
105 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
106 | #endif | |
107 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
108 | #define CFG_MAXARGS 16 /* max number of command args */ | |
109 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
110 | ||
111 | #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ | |
112 | ||
113 | #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ | |
114 | ||
115 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
116 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
117 | ||
118 | #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ | |
119 | #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ | |
120 | #define CFG_BASE_BAUD 691200 | |
121 | #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ | |
122 | ||
123 | /* The following table includes the supported baudrates */ | |
124 | #define CFG_BAUDRATE_TABLE \ | |
125 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ | |
126 | 57600, 115200, 230400, 460800, 921600 } | |
127 | ||
128 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
129 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
130 | ||
131 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
132 | ||
133 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
134 | ||
135 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
136 | ||
137 | #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ | |
138 | ||
139 | /*----------------------------------------------------------------------- | |
140 | * NAND-FLASH stuff | |
141 | *----------------------------------------------------------------------- | |
142 | */ | |
143 | #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
144 | #define SECTORSIZE 512 | |
145 | ||
146 | #define ADDR_COLUMN 1 | |
147 | #define ADDR_PAGE 2 | |
148 | #define ADDR_COLUMN_PAGE 3 | |
149 | ||
150 | #define NAND_ChipID_UNKNOWN 0x00 | |
151 | #define NAND_MAX_FLOORS 1 | |
152 | #define NAND_MAX_CHIPS 1 | |
153 | ||
154 | #define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ | |
155 | #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
156 | #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
157 | #define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
158 | ||
159 | #define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) | |
160 | #define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) | |
161 | #define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) | |
162 | #define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) | |
163 | #define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) | |
164 | #define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) | |
165 | #define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) | |
166 | ||
167 | #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) | |
168 | #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) | |
169 | #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) | |
170 | #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) | |
171 | ||
172 | /*----------------------------------------------------------------------- | |
173 | * PCI stuff | |
174 | *----------------------------------------------------------------------- | |
175 | */ | |
176 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
177 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
178 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
179 | ||
180 | #define CONFIG_PCI /* include pci support */ | |
181 | #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ | |
182 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
183 | /* resource configuration */ | |
184 | ||
185 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
186 | ||
187 | #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ | |
188 | #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
189 | #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
190 | #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
191 | #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
192 | #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
193 | #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
194 | #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
195 | #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
196 | ||
197 | /*----------------------------------------------------------------------- | |
198 | * IDE/ATA stuff | |
199 | *----------------------------------------------------------------------- | |
200 | */ | |
201 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
202 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
203 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ | |
204 | ||
205 | #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ | |
206 | #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ | |
207 | ||
208 | #define CONFIG_ATAPI 1 /* ATAPI for Travelstar */ | |
209 | ||
210 | #define CFG_ATA_BASE_ADDR 0xF0100000 | |
211 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
212 | #define CFG_ATA_IDE1_OFFSET 0x0010 | |
213 | ||
214 | #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ | |
215 | #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
216 | #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
217 | ||
218 | /* | |
219 | * For booting Linux, the board info and command line data | |
220 | * have to be in the first 8 MB of memory, since this is | |
221 | * the maximum mapped by the Linux kernel during initialization. | |
222 | */ | |
223 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
224 | /*----------------------------------------------------------------------- | |
225 | * FLASH organization | |
226 | */ | |
227 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
228 | ||
229 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
230 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
231 | ||
232 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
233 | #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
234 | ||
235 | #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ | |
236 | #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
237 | #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
238 | /* | |
239 | * The following defines are added for buggy IOP480 byte interface. | |
240 | * All other boards should use the standard values (CPCI405 etc.) | |
241 | */ | |
242 | #define CFG_FLASH_READ0 0x0000 /* 0 is standard */ | |
243 | #define CFG_FLASH_READ1 0x0001 /* 1 is standard */ | |
244 | #define CFG_FLASH_READ2 0x0002 /* 2 is standard */ | |
245 | ||
246 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
247 | ||
248 | #if 0 /* test-only */ | |
249 | #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ | |
250 | #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ | |
251 | #endif | |
252 | ||
253 | /*----------------------------------------------------------------------- | |
254 | * Start addresses for the final memory configuration | |
255 | * (Set up by the startup code) | |
256 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
257 | */ | |
258 | #define CFG_SDRAM_BASE 0x00000000 | |
259 | #define CFG_FLASH_BASE 0xFFFC0000 | |
260 | #define CFG_MONITOR_BASE TEXT_BASE | |
261 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
262 | #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ | |
263 | ||
264 | #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) | |
265 | # define CFG_RAMBOOT 1 | |
266 | #else | |
267 | # undef CFG_RAMBOOT | |
268 | #endif | |
269 | ||
270 | /*----------------------------------------------------------------------- | |
271 | * Environment Variable setup | |
272 | */ | |
273 | #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ | |
274 | #define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ | |
275 | #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ | |
276 | /* total size of a CAT24WC16 is 2048 bytes */ | |
277 | ||
278 | #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ | |
279 | #define CFG_NVRAM_SIZE 242 /* NVRAM size */ | |
280 | ||
281 | /*----------------------------------------------------------------------- | |
282 | * I2C EEPROM (CAT24WC16) for environment | |
283 | */ | |
284 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
285 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
286 | #define CFG_I2C_SLAVE 0x7F | |
287 | ||
288 | #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ | |
289 | #if 0 /* test-only */ | |
290 | /* CAT24WC08/16... */ | |
291 | #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
292 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
293 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
294 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
295 | /* 16 byte page write mode using*/ | |
296 | /* last 4 bits of the address */ | |
297 | #else | |
298 | /* CAT24WC32/64... */ | |
299 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
300 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
301 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 | |
302 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ | |
303 | /* 32 byte page write mode using*/ | |
304 | /* last 5 bits of the address */ | |
305 | #endif | |
306 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
307 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
308 | ||
309 | /*----------------------------------------------------------------------- | |
310 | * Cache Configuration | |
311 | */ | |
312 | #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ | |
313 | /* have only 8kB, 16kB is save here */ | |
314 | #define CFG_CACHELINE_SIZE 32 /* ... */ | |
315 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
316 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
317 | #endif | |
318 | ||
319 | /*----------------------------------------------------------------------- | |
320 | * External Bus Controller (EBC) Setup | |
321 | */ | |
322 | ||
323 | #define CAN_BA 0xF0000000 /* CAN Base Address */ | |
324 | #define DUART0_BA 0xF0000400 /* DUART Base Address */ | |
325 | #define DUART1_BA 0xF0000408 /* DUART Base Address */ | |
326 | #define RTC_BA 0xF0000500 /* RTC Base Address */ | |
327 | #define VGA_BA 0xF1000000 /* Epson VGA Base Address */ | |
328 | #define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ | |
329 | ||
330 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
331 | #define CFG_EBC_PB0AP 0x92015480 | |
332 | /*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ | |
333 | #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
334 | ||
335 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ | |
336 | #define CFG_EBC_PB1AP 0x92015480 | |
337 | #define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ | |
338 | ||
339 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ | |
340 | #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
341 | #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
342 | ||
343 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ | |
344 | #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
345 | #define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
346 | ||
347 | /* Memory Bank 4 (Epson VGA) initialization */ | |
348 | #define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ | |
349 | #define CFG_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ | |
350 | ||
351 | /*----------------------------------------------------------------------- | |
352 | * FPGA stuff | |
353 | */ | |
354 | ||
355 | #define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ | |
356 | ||
357 | /* FPGA internal regs */ | |
358 | #define CFG_FPGA_CTRL 0x000 | |
359 | ||
360 | /* FPGA Control Reg */ | |
361 | #define CFG_FPGA_CTRL_CF_RESET 0x0001 | |
362 | #define CFG_FPGA_CTRL_WDI 0x0002 | |
363 | #define CFG_FPGA_CTRL_PS2_RESET 0x0020 | |
364 | ||
365 | #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ | |
366 | #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
367 | ||
368 | /* FPGA program pin configuration */ | |
369 | #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ | |
370 | #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
371 | #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
372 | #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
373 | #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
374 | ||
375 | /*----------------------------------------------------------------------- | |
376 | * Definitions for initial stack pointer and data area (in data cache) | |
377 | */ | |
378 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
379 | #define CFG_TEMP_STACK_OCM 1 | |
380 | ||
381 | /* On Chip Memory location */ | |
382 | #define CFG_OCM_DATA_ADDR 0xF8000000 | |
383 | #define CFG_OCM_DATA_SIZE 0x1000 | |
384 | #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ | |
385 | #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ | |
386 | ||
387 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
388 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
389 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
390 | ||
391 | /*----------------------------------------------------------------------- | |
392 | * Definitions for GPIO setup (PPC405EP specific) | |
393 | * | |
394 | * GPIO0[0] - External Bus Controller BLAST output | |
395 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
396 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs | |
397 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
398 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
399 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
400 | * GPIO0[28-29] - UART1 data signal input/output | |
401 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
402 | */ | |
403 | #define CFG_GPIO0_OSRH 0x40000550 | |
404 | #define CFG_GPIO0_OSRL 0x00000110 | |
405 | #define CFG_GPIO0_ISR1H 0x00000000 | |
406 | #define CFG_GPIO0_ISR1L 0x15555445 | |
407 | #define CFG_GPIO0_TSRH 0x00000000 | |
408 | #define CFG_GPIO0_TSRL 0x00000000 | |
409 | #define CFG_GPIO0_TCR 0xF7FE0014 | |
410 | ||
411 | #define CFG_DUART_RST (0x80000000 >> 14) | |
412 | ||
413 | /* | |
414 | * Internal Definitions | |
415 | * | |
416 | * Boot Flags | |
417 | */ | |
418 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
419 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
420 | ||
421 | /* | |
422 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
423 | * This value will be set if iic boot eprom is disabled. | |
424 | */ | |
425 | #if 1 | |
426 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 | |
427 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
428 | #endif | |
429 | #if 0 | |
430 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 | |
431 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
432 | #endif | |
433 | #if 0 | |
434 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 | |
435 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
436 | #endif | |
437 | ||
438 | #endif /* __CONFIG_H */ |