[people/ms/u-boot.git] / include / configs / W7OLMC.h

/*
 * (C) Copyright 2001
 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1		/* This is a PPC405GP CPU	*/
#define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
#define CONFIG_W7OLMC		1		/* ...specifically an LMC	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f	*/
#define	CONFIG_MISC_INIT_F	1		/* and misc_init_f()		*/
#define	CONFIG_MISC_INIT_R	1		/* and misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3		/* autoboot after 3 seconds	*/

#if 1
#define CONFIG_BOOTCOMMAND	"bootvx"	/* VxWorks boot command		*/
#else
#define CONFIG_BOOTCOMMAND	"bootp"		/* autoboot command		*/
#endif

#undef CONFIG_BOOTARGS

#define CONFIG_LOADADDR		F0080000

#define CONFIG_ETHADDR		00:06:0D:00:00:00 /* Default, overridden at boot	*/
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_IPADDR		192.168.1.1
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_SERVERIP		192.168.1.2

#define CONFIG_LOADS_ECHO	1		/* echo on for serial download	*/
#undef CONFIG_SYS_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1		/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0		/* PHY address			*/

#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_BSP
#define CONFIG_CMD_REGINFO

#undef CONFIG_WATCHDOG				/* watchdog disabled		*/
#define CONFIG_HW_WATCHDOG			/* HW Watchdog, board specific	*/

#define	CONFIG_SPD_EEPROM			/* SPD EEPROM for SDRAM param.	*/
#define CONFIG_SPDDRAM_SILENT			/* No output if spd fails	*/
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define CONFIG_SYS_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
#undef  CONFIG_SYS_HUSH_PARSER				/* No hush parse for U-Boot       */
#ifdef  CONFIG_SYS_HUSH_PARSER
#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef  CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
#define CONFIG_SYS_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD		384000


/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	{9600}

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
#define CONFIG_SYS_EXTBDINFO		1		/* use extended board_info (bd_t) */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER	0		/* configure as pci adapter	*/
#define PCI_HOST_FORCE		1		/* configure as pci host	*/
#define PCI_HOST_AUTO		2		/* detected via arbiter enable	*/


#define CONFIG_PCI				/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST		PCI_HOST_AUTO	/* select pci host function	*/
#define CONFIG_PCI_PNP				/* pci plug-and-play		*/
/* resource configuration	*/
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014		/* PCI Vendor ID: IBM		*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
#define CONFIG_SYS_PCI_PTM1LA		0x00000000	/* point to sdram		*/
#define CONFIG_SYS_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
#define CONFIG_SYS_PCI_PTM1PCI		0x00000000      /* Host: use this pci address   */
#define CONFIG_SYS_PCI_PTM2LA		0x00000000	/* disabled			*/
#define CONFIG_SYS_PCI_PTM2MS		0x00000000	/* disabled			*/
#define CONFIG_SYS_PCI_PTM2PCI		0x00000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * Set up values for external bus controller
 * used by cpu_init.c
 *-----------------------------------------------------------------------
 */
 /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
#undef CONFIG_USE_PERWE

/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM        1

/* bank 0 is boot flash */
/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
#define CONFIG_SYS_W7O_EBC_PB0AP   0x03050440
/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
#define CONFIG_SYS_W7O_EBC_PB0CR   0xFFE38000

/* bank 1 is main flash */
/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
#define CONFIG_SYS_EBC_PB1AP   0x05850240
/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
#define CONFIG_SYS_EBC_PB1CR   0xF00FC000

/* bank 2 is RTC/NVRAM */
/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
#define CONFIG_SYS_EBC_PB2AP   0x03000440
/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
#define CONFIG_SYS_EBC_PB2CR   0xFC018000

/* bank 3 is FPGA 0 */
/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
#define CONFIG_SYS_EBC_PB3AP   0x02000400
/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
#define CONFIG_SYS_EBC_PB3CR   0xFD01A000

/* bank 4 is FPGA 1 */
/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
#define CONFIG_SYS_EBC_PB4AP   0x02000400
/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
#define CONFIG_SYS_EBC_PB4CR   0xFD11A000

/* bank 5 is FPGA 2 */
/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
#define CONFIG_SYS_EBC_PB5AP   0x02000400
/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
#define CONFIG_SYS_EBC_PB5CR   0xFD21A000

/* bank 6 is unused */
/* PB6AP = 0 */
#define CONFIG_SYS_EBC_PB6AP   0x00000000
/* PB6CR = 0 */
#define CONFIG_SYS_EBC_PB6CR   0x00000000

/* bank 7 is LED register */
/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
#define CONFIG_SYS_W7O_EBC_PB7AP   0x03050440
/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
#define CONFIG_SYS_W7O_EBC_PB7CR   0xFE01C000

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* max number of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max number of sec on 1 chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000		/* Timeout, Flash Erase, in ms	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout, Flash Write, in ms	*/
#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use real Flash protection	*/

#if 1 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CONFIG_ENV_IS_IN_NVRAM	1		/* use NVRAM for env vars	*/
#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfc000000	/* NVRAM base address		*/
#define CONFIG_SYS_NVRAM_SIZE		(32*1024)	/* NVRAM size			*/
#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
/*define CONFIG_ENV_ADDR		 \
	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env  */
#define CONFIG_ENV_ADDR		CONFIG_SYS_NVRAM_BASE_ADDR

#else /* Use Boot Flash for environment variables */
/*-----------------------------------------------------------------------
 * Flash EEPROM for environment
 */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
#define CONFIG_ENV_SIZE		0x10000		/* Total Size of env. sector	*/

#define CONFIG_ENV_SECT_SIZE	0x10000		/* see README - env sec tot sze */
#endif

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"    */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last	4 bits of the address	*/
#define CONFIG_SYS_I2C_MULTI_EEPROMS
/*-----------------------------------------------------------------------
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 */
#define SPD_EEPROM_ADDRESS      0x50	/* XXX conflicting address!!! XXX */

/*
 * Init Memory Controller:
 */
#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0		*/
#define FLASH_BASE1_PRELIM	0xF0000000	/* FLASH bank #1		*/

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in RAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
#endif

/*
 * FPGA(s) configuration
 */
#define CONFIG_SYS_FPGA_IMAGE_LEN	0x80000		/* 512KB FPGA image		*/
#define CONFIG_NUM_FPGAS	3		/* Number of FPGAs on board	*/
#define CONFIG_MAX_FPGAS	6		/* Maximum number of FPGAs	*/
#define CONFIG_FPGAS_BASE	0xFD000000L	/* Base address of FPGAs	*/
#define CONFIG_FPGAS_BANK_SIZE	0x00100000L	/* FPGAs' mmap bank size	*/

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2001
	3	* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
e2211743 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
e2211743 WD	21	#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
	22	#define CONFIG_W7OLMC 1 /* ...specifically an LMC */
	23
2ae18241 WD	24	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	25
c837dcb1 WD	26	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
c837dcb1 WD	27	#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
3a8f28d0	28	#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */
e2211743 WD	29
	30	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	31
	32	#define CONFIG_BAUDRATE 9600
	33	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	34
	35	#if 1
	36	#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
	37	#else
	38	#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
	39	#endif
	40
	41	#undef CONFIG_BOOTARGS
	42
	43	#define CONFIG_LOADADDR F0080000
	44
	45	#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
	46	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	47	#define CONFIG_IPADDR 192.168.1.1
	48	#define CONFIG_NETMASK 255.255.255.0
	49	#define CONFIG_SERVERIP 192.168.1.2
	50
	51	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	52	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
e2211743	53
96e21f86	54	#define CONFIG_PPC4xx_EMAC
e2211743 WD	55	#define CONFIG_MII 1 /* MII PHY management */
	56	#define CONFIG_PHY_ADDR 0 /* PHY address */
	57
	58	#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
	59
a1aa0bb5 JL	60	/*
	61	* BOOTP options
	62	*/
	63	#define CONFIG_BOOTP_BOOTFILESIZE
	64	#define CONFIG_BOOTP_BOOTPATH
	65	#define CONFIG_BOOTP_GATEWAY
	66	#define CONFIG_BOOTP_HOSTNAME
	67
	68
a5562901 JL	69	/*
	70	* Command line configuration.
	71	*/
	72	#include <config_cmd_default.h>
	73
	74	#define CONFIG_CMD_PCI
	75	#define CONFIG_CMD_IRQ
	76	#define CONFIG_CMD_ASKENV
	77	#define CONFIG_CMD_DHCP
	78	#define CONFIG_CMD_BEDBUG
	79	#define CONFIG_CMD_DATE
	80	#define CONFIG_CMD_I2C
	81	#define CONFIG_CMD_EEPROM
	82	#define CONFIG_CMD_ELF
	83	#define CONFIG_CMD_BSP
	84	#define CONFIG_CMD_REGINFO
e2211743 WD	85
	86	#undef CONFIG_WATCHDOG /* watchdog disabled */
	87	#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
	88
	89	#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
db2f721f	90	#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
e2211743 WD	91	/*
	92	* Miscellaneous configurable options
	93	*/
6d0f6bcf JCPV	94	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	95	#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
	96	#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */
	97	#ifdef CONFIG_SYS_HUSH_PARSER
e2211743	98	#endif
a5562901	99	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	100	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743	101	#else
6d0f6bcf	102	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743	103	#endif
6d0f6bcf JCPV	104	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	105	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	106	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e2211743	107
6d0f6bcf JCPV	108	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	109	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
e2211743	110
550650dd SR	111	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	112	#define CONFIG_SYS_NS16550
	113	#define CONFIG_SYS_NS16550_SERIAL
	114	#define CONFIG_SYS_NS16550_REG_SIZE 1
	115	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	116
6d0f6bcf JCPV	117	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
	118	#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
	119	#define CONFIG_SYS_BASE_BAUD 384000
e2211743 WD	120
	121
	122	/* The following table includes the supported baudrates */
6d0f6bcf	123	#define CONFIG_SYS_BAUDRATE_TABLE {9600}
e2211743	124
6d0f6bcf JCPV	125	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	126	#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
e2211743	127
e2211743 WD	128	/*-----------------------------------------------------------------------
	129	* PCI stuff
	130	*-----------------------------------------------------------------------
	131	*/
	132	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	133	#define PCI_HOST_FORCE 1 /* configure as pci host */
	134	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	135
	136
	137	#define CONFIG_PCI /* include pci support */
842033e6	138	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
e2211743 WD	139	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	140	#define CONFIG_PCI_PNP /* pci plug-and-play */
	141	/* resource configuration */
6d0f6bcf JCPV	142	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
	143	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
	144	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	145	#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	146	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	147	#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
	148	#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
	149	#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
e2211743 WD	150
	151	/*-----------------------------------------------------------------------
	152	* Set up values for external bus controller
	153	* used by cpu_init.c
	154	*-----------------------------------------------------------------------
	155	*/
	156	/* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
	157	#undef CONFIG_USE_PERWE
	158
	159	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
6d0f6bcf	160	#define CONFIG_SYS_TEMP_STACK_OCM 1
e2211743 WD	161
	162	/* bank 0 is boot flash */
	163	/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
6d0f6bcf	164	#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440
e2211743	165	/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
6d0f6bcf	166	#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000
e2211743 WD	167
	168	/* bank 1 is main flash */
	169	/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
6d0f6bcf	170	#define CONFIG_SYS_EBC_PB1AP 0x05850240
e2211743	171	/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
6d0f6bcf	172	#define CONFIG_SYS_EBC_PB1CR 0xF00FC000
e2211743 WD	173
	174	/* bank 2 is RTC/NVRAM */
	175	/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
6d0f6bcf	176	#define CONFIG_SYS_EBC_PB2AP 0x03000440
e2211743	177	/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
6d0f6bcf	178	#define CONFIG_SYS_EBC_PB2CR 0xFC018000
e2211743 WD	179
	180	/* bank 3 is FPGA 0 */
	181	/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
6d0f6bcf	182	#define CONFIG_SYS_EBC_PB3AP 0x02000400
e2211743	183	/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
6d0f6bcf	184	#define CONFIG_SYS_EBC_PB3CR 0xFD01A000
e2211743 WD	185
	186	/* bank 4 is FPGA 1 */
	187	/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
6d0f6bcf	188	#define CONFIG_SYS_EBC_PB4AP 0x02000400
e2211743	189	/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
6d0f6bcf	190	#define CONFIG_SYS_EBC_PB4CR 0xFD11A000
e2211743 WD	191
	192	/* bank 5 is FPGA 2 */
	193	/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
6d0f6bcf	194	#define CONFIG_SYS_EBC_PB5AP 0x02000400
e2211743	195	/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
6d0f6bcf	196	#define CONFIG_SYS_EBC_PB5CR 0xFD21A000
e2211743 WD	197
e2211743 WD	198	/* bank 6 is unused */
d1c3b275	199	/* PB6AP = 0 */
6d0f6bcf	200	#define CONFIG_SYS_EBC_PB6AP 0x00000000
d1c3b275	201	/* PB6CR = 0 */
6d0f6bcf	202	#define CONFIG_SYS_EBC_PB6CR 0x00000000
e2211743 WD	203
	204	/* bank 7 is LED register */
	205	/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
6d0f6bcf	206	#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440
e2211743	207	/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
6d0f6bcf	208	#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000
e2211743 WD	209
	210	/*-----------------------------------------------------------------------
	211	* Start addresses for the final memory configuration
	212	* (Set up by the startup code)
6d0f6bcf	213	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e2211743	214	*/
6d0f6bcf JCPV	215	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	216	#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
	217	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	218	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	219	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
e2211743 WD	220
	221	/*
	222	* For booting Linux, the board info and command line data
	223	* have to be in the first 8 MB of memory, since this is
	224	* the maximum mapped by the Linux kernel during initialization.
	225	*/
6d0f6bcf	226	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	227	/*-----------------------------------------------------------------------
	228	* FLASH organization
	229	*/
6d0f6bcf JCPV	230	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	231	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
e2211743	232
6d0f6bcf JCPV	233	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
	234	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
	235	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */
e2211743 WD	236
	237	#if 1 /* Use NVRAM for environment variables */
	238	/*-----------------------------------------------------------------------
	239	* NVRAM organization
	240	*/
9314cee6	241	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
6d0f6bcf JCPV	242	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
6d0f6bcf JCPV	243	#define CONFIG_SYS_NVRAM_SIZE (321024) / NVRAM size */
0e8d1586 JCPV	244	#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
0e8d1586 JCPV	245	/*define CONFIG_ENV_ADDR \
6d0f6bcf JCPV	246	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */
6d0f6bcf JCPV	247	#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
e2211743 WD	248
	249	#else /* Use Boot Flash for environment variables */
	250	/*-----------------------------------------------------------------------
	251	* Flash EEPROM for environment
	252	*/
5a1aceb0	253	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	254	#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
0e8d1586 JCPV	255	#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */
e2211743	256
0e8d1586	257	#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
e2211743 WD	258	#endif
	259
	260	/*-----------------------------------------------------------------------
	261	* I2C EEPROM (CAT24WC08) for environment
	262	*/
880540de DE	263	#define CONFIG_SYS_I2C
	264	#define CONFIG_SYS_I2C_PPC4XX
	265	#define CONFIG_SYS_I2C_PPC4XX_CH0
	266	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	267	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
e2211743	268
6d0f6bcf JCPV	269	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
6d0f6bcf JCPV	270	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
e2211743	271	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	272	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	273	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
e2211743 WD	274	/* 16 byte page write mode using*/
e2211743 WD	275	/* last 4 bits of the address */
6d0f6bcf	276	#define CONFIG_SYS_I2C_MULTI_EEPROMS
e2211743 WD	277	/*-----------------------------------------------------------------------
	278	* Definitions for Serial Presence Detect EEPROM address
	279	* (to get SDRAM settings)
	280	*/
	281	#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
	282
e2211743 WD	283	/*
	284	* Init Memory Controller:
	285	*/
	286	#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
	287	#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
	288
	289	/* On Chip Memory location */
6d0f6bcf JCPV	290	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
6d0f6bcf JCPV	291	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
e2211743 WD	292
	293	/*-----------------------------------------------------------------------
	294	* Definitions for initial stack pointer and data area (in RAM)
	295	*/
6d0f6bcf	296	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
553f0982	297	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
25ddd1fb	298	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	299	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e2211743	300
a5562901	301	#if defined(CONFIG_CMD_KGDB)
e2211743	302	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
e2211743 WD	303	#endif
	304
	305	/*
	306	* FPGA(s) configuration
	307	*/
6d0f6bcf	308	#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
e2211743 WD	309	#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */
	310	#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
	311	#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
	312	#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
	313
	314	#endif /* __CONFIG_H */