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e2211743 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ | |
37 | #define CONFIG_4xx 1 /* ...member of PPC405 family */ | |
38 | #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ | |
39 | #define CONFIG_W7OLMC 1 /* ...specifically an LMC */ | |
40 | ||
c837dcb1 WD |
41 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
42 | #define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ | |
e2211743 WD |
43 | |
44 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
45 | ||
46 | #define CONFIG_BAUDRATE 9600 | |
47 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
48 | ||
49 | #if 1 | |
50 | #define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ | |
51 | #else | |
52 | #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ | |
53 | #endif | |
54 | ||
55 | #undef CONFIG_BOOTARGS | |
56 | ||
57 | #define CONFIG_LOADADDR F0080000 | |
58 | ||
59 | #define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ | |
60 | #define CONFIG_OVERWRITE_ETHADDR_ONCE | |
61 | #define CONFIG_IPADDR 192.168.1.1 | |
62 | #define CONFIG_NETMASK 255.255.255.0 | |
63 | #define CONFIG_SERVERIP 192.168.1.2 | |
64 | ||
65 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 66 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */ |
e2211743 WD |
67 | |
68 | #define CONFIG_MII 1 /* MII PHY management */ | |
69 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
70 | ||
71 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ | |
72 | ||
a1aa0bb5 JL |
73 | /* |
74 | * BOOTP options | |
75 | */ | |
76 | #define CONFIG_BOOTP_BOOTFILESIZE | |
77 | #define CONFIG_BOOTP_BOOTPATH | |
78 | #define CONFIG_BOOTP_GATEWAY | |
79 | #define CONFIG_BOOTP_HOSTNAME | |
80 | ||
81 | ||
a5562901 JL |
82 | /* |
83 | * Command line configuration. | |
84 | */ | |
85 | #include <config_cmd_default.h> | |
86 | ||
87 | #define CONFIG_CMD_PCI | |
88 | #define CONFIG_CMD_IRQ | |
89 | #define CONFIG_CMD_ASKENV | |
90 | #define CONFIG_CMD_DHCP | |
91 | #define CONFIG_CMD_BEDBUG | |
92 | #define CONFIG_CMD_DATE | |
93 | #define CONFIG_CMD_I2C | |
94 | #define CONFIG_CMD_EEPROM | |
95 | #define CONFIG_CMD_ELF | |
96 | #define CONFIG_CMD_BSP | |
97 | #define CONFIG_CMD_REGINFO | |
e2211743 WD |
98 | |
99 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
100 | #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ | |
101 | ||
102 | #define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ | |
db2f721f | 103 | #define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ |
e2211743 WD |
104 | /* |
105 | * Miscellaneous configurable options | |
106 | */ | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
108 | #define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ | |
109 | #undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */ | |
110 | #ifdef CONFIG_SYS_HUSH_PARSER | |
111 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
e2211743 | 112 | #endif |
a5562901 | 113 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 114 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
e2211743 | 115 | #else |
6d0f6bcf | 116 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
e2211743 | 117 | #endif |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
119 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
120 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
e2211743 | 121 | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
123 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
e2211743 | 124 | |
6d0f6bcf JCPV |
125 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
126 | #define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
127 | #define CONFIG_SYS_BASE_BAUD 384000 | |
e2211743 WD |
128 | |
129 | ||
130 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 131 | #define CONFIG_SYS_BAUDRATE_TABLE {9600} |
e2211743 | 132 | |
6d0f6bcf | 133 | #define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ |
e2211743 | 134 | |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
136 | #define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */ | |
e2211743 | 137 | |
6d0f6bcf | 138 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
e2211743 WD |
139 | |
140 | /*----------------------------------------------------------------------- | |
141 | * PCI stuff | |
142 | *----------------------------------------------------------------------- | |
143 | */ | |
144 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
145 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
146 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
147 | ||
148 | ||
149 | #define CONFIG_PCI /* include pci support */ | |
150 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ | |
151 | #define CONFIG_PCI_PNP /* pci plug-and-play */ | |
152 | /* resource configuration */ | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ |
154 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ | |
155 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
156 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
157 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
158 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
159 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
160 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
e2211743 WD |
161 | |
162 | /*----------------------------------------------------------------------- | |
163 | * Set up values for external bus controller | |
164 | * used by cpu_init.c | |
165 | *----------------------------------------------------------------------- | |
166 | */ | |
167 | /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */ | |
168 | #undef CONFIG_USE_PERWE | |
169 | ||
170 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 171 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
e2211743 WD |
172 | |
173 | /* bank 0 is boot flash */ | |
174 | /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ | |
6d0f6bcf | 175 | #define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440 |
e2211743 | 176 | /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ |
6d0f6bcf | 177 | #define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000 |
e2211743 WD |
178 | |
179 | /* bank 1 is main flash */ | |
180 | /* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ | |
6d0f6bcf | 181 | #define CONFIG_SYS_EBC_PB1AP 0x05850240 |
e2211743 | 182 | /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ |
6d0f6bcf | 183 | #define CONFIG_SYS_EBC_PB1CR 0xF00FC000 |
e2211743 WD |
184 | |
185 | /* bank 2 is RTC/NVRAM */ | |
186 | /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ | |
6d0f6bcf | 187 | #define CONFIG_SYS_EBC_PB2AP 0x03000440 |
e2211743 | 188 | /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ |
6d0f6bcf | 189 | #define CONFIG_SYS_EBC_PB2CR 0xFC018000 |
e2211743 WD |
190 | |
191 | /* bank 3 is FPGA 0 */ | |
192 | /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ | |
6d0f6bcf | 193 | #define CONFIG_SYS_EBC_PB3AP 0x02000400 |
e2211743 | 194 | /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ |
6d0f6bcf | 195 | #define CONFIG_SYS_EBC_PB3CR 0xFD01A000 |
e2211743 WD |
196 | |
197 | /* bank 4 is FPGA 1 */ | |
198 | /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ | |
6d0f6bcf | 199 | #define CONFIG_SYS_EBC_PB4AP 0x02000400 |
e2211743 | 200 | /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ |
6d0f6bcf | 201 | #define CONFIG_SYS_EBC_PB4CR 0xFD11A000 |
e2211743 WD |
202 | |
203 | /* bank 5 is FPGA 2 */ | |
204 | /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ | |
6d0f6bcf | 205 | #define CONFIG_SYS_EBC_PB5AP 0x02000400 |
e2211743 | 206 | /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ |
6d0f6bcf | 207 | #define CONFIG_SYS_EBC_PB5CR 0xFD21A000 |
e2211743 WD |
208 | |
209 | /* bank 6 is unused */ | |
210 | /* pb6ap = 0 */ | |
6d0f6bcf | 211 | #define CONFIG_SYS_EBC_PB6AP 0x00000000 |
e2211743 | 212 | /* pb6cr = 0 */ |
6d0f6bcf | 213 | #define CONFIG_SYS_EBC_PB6CR 0x00000000 |
e2211743 WD |
214 | |
215 | /* bank 7 is LED register */ | |
216 | /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ | |
6d0f6bcf | 217 | #define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440 |
e2211743 | 218 | /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ |
6d0f6bcf | 219 | #define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000 |
e2211743 WD |
220 | |
221 | /*----------------------------------------------------------------------- | |
222 | * Start addresses for the final memory configuration | |
223 | * (Set up by the startup code) | |
6d0f6bcf | 224 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
e2211743 | 225 | */ |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
227 | #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 | |
228 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
229 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
230 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
e2211743 WD |
231 | |
232 | /* | |
233 | * For booting Linux, the board info and command line data | |
234 | * have to be in the first 8 MB of memory, since this is | |
235 | * the maximum mapped by the Linux kernel during initialization. | |
236 | */ | |
6d0f6bcf | 237 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
e2211743 WD |
238 | /*----------------------------------------------------------------------- |
239 | * FLASH organization | |
240 | */ | |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
242 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ | |
e2211743 | 243 | |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ |
245 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ | |
246 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */ | |
e2211743 WD |
247 | |
248 | #if 1 /* Use NVRAM for environment variables */ | |
249 | /*----------------------------------------------------------------------- | |
250 | * NVRAM organization | |
251 | */ | |
9314cee6 | 252 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ |
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ |
254 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
0e8d1586 JCPV |
255 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
256 | /*define CONFIG_ENV_ADDR \ | |
6d0f6bcf JCPV |
257 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */ |
258 | #define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR | |
e2211743 WD |
259 | |
260 | #else /* Use Boot Flash for environment variables */ | |
261 | /*----------------------------------------------------------------------- | |
262 | * Flash EEPROM for environment | |
263 | */ | |
5a1aceb0 | 264 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
265 | #define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ |
266 | #define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */ | |
e2211743 | 267 | |
0e8d1586 | 268 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ |
e2211743 WD |
269 | #endif |
270 | ||
271 | /*----------------------------------------------------------------------- | |
272 | * I2C EEPROM (CAT24WC08) for environment | |
273 | */ | |
274 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
276 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
e2211743 | 277 | |
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
279 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
e2211743 | 280 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
281 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
282 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
e2211743 WD |
283 | /* 16 byte page write mode using*/ |
284 | /* last 4 bits of the address */ | |
6d0f6bcf | 285 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
e2211743 WD |
286 | /*----------------------------------------------------------------------- |
287 | * Definitions for Serial Presence Detect EEPROM address | |
288 | * (to get SDRAM settings) | |
289 | */ | |
290 | #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ | |
291 | ||
e2211743 WD |
292 | /* |
293 | * Init Memory Controller: | |
294 | */ | |
295 | #define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ | |
296 | #define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ | |
297 | ||
298 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
299 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
300 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
e2211743 WD |
301 | |
302 | /*----------------------------------------------------------------------- | |
303 | * Definitions for initial stack pointer and data area (in RAM) | |
304 | */ | |
6d0f6bcf JCPV |
305 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
306 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ | |
307 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
308 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
309 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
e2211743 WD |
310 | |
311 | ||
312 | /* | |
313 | * Internal Definitions | |
314 | * | |
315 | * Boot Flags | |
316 | */ | |
317 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
318 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
319 | ||
a5562901 | 320 | #if defined(CONFIG_CMD_KGDB) |
e2211743 WD |
321 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
322 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
323 | #endif | |
324 | ||
325 | /* | |
326 | * FPGA(s) configuration | |
327 | */ | |
6d0f6bcf | 328 | #define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ |
e2211743 WD |
329 | #define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */ |
330 | #define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ | |
331 | #define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ | |
332 | #define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ | |
333 | ||
334 | #endif /* __CONFIG_H */ |