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e2211743 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
e2211743 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ | |
e2211743 WD |
21 | #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ |
22 | #define CONFIG_W7OLMG 1 /* ...specifically an LMG */ | |
23 | ||
2ae18241 WD |
24 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
25 | ||
c837dcb1 WD |
26 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
27 | #define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ | |
3a8f28d0 | 28 | #define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */ |
e2211743 WD |
29 | |
30 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
31 | ||
32 | #define CONFIG_BAUDRATE 9600 | |
33 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
34 | ||
35 | #if 1 | |
36 | #define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ | |
37 | #else | |
38 | #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ | |
39 | #endif | |
40 | ||
41 | #undef CONFIG_BOOTARGS | |
42 | ||
43 | #define CONFIG_LOADADDR F0080000 | |
44 | ||
45 | #define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ | |
46 | #define CONFIG_OVERWRITE_ETHADDR_ONCE | |
47 | #define CONFIG_IPADDR 192.168.1.1 | |
48 | #define CONFIG_NETMASK 255.255.255.0 | |
49 | #define CONFIG_SERVERIP 192.168.1.2 | |
50 | ||
51 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 52 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */ |
e2211743 | 53 | |
96e21f86 | 54 | #define CONFIG_PPC4xx_EMAC |
e2211743 WD |
55 | #define CONFIG_MII 1 /* MII PHY management */ |
56 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
57 | ||
58 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ | |
59 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
60 | #define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */ | |
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
62 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
63 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
e2211743 | 64 | |
e2211743 | 65 | |
a1aa0bb5 JL |
66 | /* |
67 | * BOOTP options | |
68 | */ | |
69 | #define CONFIG_BOOTP_BOOTFILESIZE | |
70 | #define CONFIG_BOOTP_BOOTPATH | |
71 | #define CONFIG_BOOTP_GATEWAY | |
72 | #define CONFIG_BOOTP_HOSTNAME | |
73 | ||
74 | ||
a5562901 JL |
75 | /* |
76 | * Command line configuration. | |
77 | */ | |
78 | #include <config_cmd_default.h> | |
79 | ||
80 | #define CONFIG_CMD_PCI | |
81 | #define CONFIG_CMD_IRQ | |
82 | #define CONFIG_CMD_ASKENV | |
83 | #define CONFIG_CMD_DHCP | |
84 | #define CONFIG_CMD_BEDBUG | |
85 | #define CONFIG_CMD_DATE | |
86 | #define CONFIG_CMD_I2C | |
87 | #define CONFIG_CMD_EEPROM | |
88 | #define CONFIG_CMD_ELF | |
89 | #define CONFIG_CMD_BSP | |
90 | #define CONFIG_CMD_REGINFO | |
91 | #define CONFIG_CMD_DTT | |
92 | ||
e2211743 WD |
93 | |
94 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
95 | #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ | |
96 | ||
97 | #define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ | |
db2f721f | 98 | #define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ |
e2211743 WD |
99 | /* |
100 | * Miscellaneous configurable options | |
101 | */ | |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
103 | #define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ | |
104 | #undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */ | |
105 | #ifdef CONFIG_SYS_HUSH_PARSER | |
e2211743 | 106 | #endif |
a5562901 | 107 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 108 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
e2211743 | 109 | #else |
6d0f6bcf | 110 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
e2211743 | 111 | #endif |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
113 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
114 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
e2211743 | 115 | |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
117 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
e2211743 | 118 | |
550650dd SR |
119 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
120 | #define CONFIG_SYS_NS16550 | |
121 | #define CONFIG_SYS_NS16550_SERIAL | |
122 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
123 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
124 | ||
6d0f6bcf JCPV |
125 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
126 | #define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
127 | #define CONFIG_SYS_BASE_BAUD 384000 | |
e2211743 WD |
128 | |
129 | ||
130 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 131 | #define CONFIG_SYS_BAUDRATE_TABLE {9600} |
e2211743 | 132 | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
134 | #define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */ | |
e2211743 | 135 | |
e2211743 WD |
136 | /*----------------------------------------------------------------------- |
137 | * PCI stuff | |
138 | *----------------------------------------------------------------------- | |
139 | */ | |
140 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
141 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
142 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
143 | ||
144 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 145 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
e2211743 WD |
146 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
147 | #define CONFIG_PCI_PNP /* pci plug-and-play */ | |
148 | /* resource configuration */ | |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ |
150 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ | |
151 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
152 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
153 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
154 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
155 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
156 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
e2211743 WD |
157 | |
158 | /*----------------------------------------------------------------------- | |
159 | * Set up values for external bus controller | |
160 | * used by cpu_init.c | |
161 | *----------------------------------------------------------------------- | |
162 | */ | |
163 | /* use PerWE instead of PCI_INT ( these functions share a pin ) */ | |
164 | #define CONFIG_USE_PERWE 1 | |
165 | ||
166 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 167 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
e2211743 WD |
168 | |
169 | /* bank 0 is boot flash */ | |
170 | /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ | |
6d0f6bcf | 171 | #define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440 |
e2211743 | 172 | /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ |
6d0f6bcf | 173 | #define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000 |
e2211743 WD |
174 | |
175 | /* bank 1 is main flash */ | |
176 | /* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ | |
6d0f6bcf | 177 | #define CONFIG_SYS_EBC_PB1AP 0x04850240 |
e2211743 | 178 | /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ |
6d0f6bcf | 179 | #define CONFIG_SYS_EBC_PB1CR 0xF00FC000 |
e2211743 WD |
180 | |
181 | /* bank 2 is RTC/NVRAM */ | |
182 | /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ | |
6d0f6bcf | 183 | #define CONFIG_SYS_EBC_PB2AP 0x03000440 |
e2211743 | 184 | /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ |
6d0f6bcf | 185 | #define CONFIG_SYS_EBC_PB2CR 0xFC018000 |
e2211743 WD |
186 | |
187 | /* bank 3 is FPGA 0 */ | |
188 | /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ | |
6d0f6bcf | 189 | #define CONFIG_SYS_EBC_PB3AP 0x02000400 |
e2211743 | 190 | /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ |
6d0f6bcf | 191 | #define CONFIG_SYS_EBC_PB3CR 0xFD01A000 |
e2211743 WD |
192 | |
193 | /* bank 4 is SAM 8 bit range */ | |
194 | /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ | |
6d0f6bcf | 195 | #define CONFIG_SYS_EBC_PB4AP 0x02840380 |
e2211743 | 196 | /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ |
6d0f6bcf | 197 | #define CONFIG_SYS_EBC_PB4CR 0xFE878000 |
e2211743 WD |
198 | |
199 | /* bank 5 is SAM 16 bit range */ | |
200 | /* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */ | |
6d0f6bcf | 201 | #define CONFIG_SYS_EBC_PB5AP 0x05040d80 |
e2211743 | 202 | /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ |
6d0f6bcf | 203 | #define CONFIG_SYS_EBC_PB5CR 0xFD87A000 |
e2211743 WD |
204 | |
205 | /* bank 6 is unused */ | |
d1c3b275 | 206 | /* PB6AP = 0 */ |
6d0f6bcf | 207 | #define CONFIG_SYS_EBC_PB6AP 0x00000000 |
d1c3b275 | 208 | /* PB6CR = 0 */ |
6d0f6bcf | 209 | #define CONFIG_SYS_EBC_PB6CR 0x00000000 |
e2211743 WD |
210 | |
211 | /* bank 7 is LED register */ | |
212 | /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ | |
6d0f6bcf | 213 | #define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440 |
e2211743 | 214 | /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ |
6d0f6bcf | 215 | #define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000 |
e2211743 WD |
216 | |
217 | /*----------------------------------------------------------------------- | |
218 | * Start addresses for the final memory configuration | |
219 | * (Set up by the startup code) | |
6d0f6bcf | 220 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
e2211743 | 221 | */ |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
223 | #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 | |
224 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
225 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */ | |
226 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
e2211743 WD |
227 | |
228 | /* | |
229 | * For booting Linux, the board info and command line data | |
230 | * have to be in the first 8 MB of memory, since this is | |
231 | * the maximum mapped by the Linux kernel during initialization. | |
232 | */ | |
6d0f6bcf | 233 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
e2211743 WD |
234 | /*----------------------------------------------------------------------- |
235 | * FLASH organization | |
236 | */ | |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
238 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ | |
e2211743 | 239 | |
6d0f6bcf JCPV |
240 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ |
241 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ | |
242 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */ | |
e2211743 WD |
243 | |
244 | #if 1 /* Use NVRAM for environment variables */ | |
245 | /*----------------------------------------------------------------------- | |
246 | * NVRAM organization | |
247 | */ | |
9314cee6 | 248 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ |
250 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
0e8d1586 JCPV |
251 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
252 | /*define CONFIG_ENV_ADDR \ | |
6d0f6bcf JCPV |
253 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */ |
254 | #define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR | |
e2211743 WD |
255 | |
256 | #else /* Use Boot Flash for environment variables */ | |
257 | /*----------------------------------------------------------------------- | |
258 | * Flash EEPROM for environment | |
259 | */ | |
5a1aceb0 | 260 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
261 | #define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ |
262 | #define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */ | |
e2211743 | 263 | |
0e8d1586 | 264 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ |
e2211743 WD |
265 | #endif |
266 | ||
267 | /*----------------------------------------------------------------------- | |
268 | * I2C EEPROM (ATMEL 24C04N) | |
269 | */ | |
880540de DE |
270 | #define CONFIG_SYS_I2C |
271 | #define CONFIG_SYS_I2C_PPC4XX | |
272 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
273 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
274 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
e2211743 | 275 | |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */ |
277 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
278 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
279 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
e2211743 WD |
280 | /*----------------------------------------------------------------------- |
281 | * Definitions for Serial Presence Detect EEPROM address | |
282 | * (to get SDRAM settings) | |
283 | */ | |
284 | #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ | |
285 | ||
e2211743 WD |
286 | /* |
287 | * Init Memory Controller: | |
288 | */ | |
289 | #define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ | |
290 | #define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ | |
291 | ||
292 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
294 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
e2211743 WD |
295 | |
296 | /*----------------------------------------------------------------------- | |
297 | * Definitions for initial stack pointer and data area (in RAM) | |
298 | */ | |
6d0f6bcf | 299 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
553f0982 | 300 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
25ddd1fb | 301 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 302 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
e2211743 | 303 | |
a5562901 | 304 | #if defined(CONFIG_CMD_KGDB) |
e2211743 | 305 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
e2211743 WD |
306 | #endif |
307 | ||
308 | /* | |
309 | * FPGA(s) configuration | |
310 | */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ |
e2211743 WD |
312 | #define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */ |
313 | #define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ | |
314 | #define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ | |
315 | #define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ | |
316 | ||
317 | #endif /* __CONFIG_H */ |